From 039cd50187c2c76841869cd9ccfb12c798851c24 Mon Sep 17 00:00:00 2001 From: scribam Date: Wed, 6 Oct 2021 22:01:16 +0200 Subject: [PATCH] unicorn_arm: add reg_read/write operations for FPSCR and FPSID --- qemu/target/arm/unicorn_arm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qemu/target/arm/unicorn_arm.c b/qemu/target/arm/unicorn_arm.c index 95bd93b5..32314217 100644 --- a/qemu/target/arm/unicorn_arm.c +++ b/qemu/target/arm/unicorn_arm.c @@ -194,6 +194,12 @@ static void reg_read(CPUARMState *env, unsigned int regid, void *value) case UC_ARM_REG_FPEXC: *(int32_t *)value = env->vfp.xregs[ARM_VFP_FPEXC]; break; + case UC_ARM_REG_FPSCR: + *(int32_t *)value = vfp_get_fpscr(env); + break; + case UC_ARM_REG_FPSID: + *(int32_t *)value = env->vfp.xregs[ARM_VFP_FPSID]; + break; case UC_ARM_REG_IPSR: *(int32_t *)value = v7m_mrs_xpsr(env, 5); break; @@ -291,6 +297,12 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM_REG_FPEXC: env->vfp.xregs[ARM_VFP_FPEXC] = *(int32_t *)value; break; + case UC_ARM_REG_FPSCR: + vfp_set_fpscr(env, *(int32_t *)value); + break; + case UC_ARM_REG_FPSID: + env->vfp.xregs[ARM_VFP_FPSID] = *(int32_t *)value; + break; case UC_ARM_REG_IPSR: v7m_msr_xpsr(env, 0b1000, 5, *(uint32_t *)value); break;