diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index 30b870d8..64c518a8 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -136,7 +136,20 @@ def gen(lang):
 
         previous = {}
         count = 0
-        for line in lines:
+        skip = 0
+        in_comment = False
+        
+        for lno, line in enumerate(lines):
+            if "/*" in line:
+                in_comment = True
+            if "*/" in line:
+                in_comment = False
+            if in_comment:
+                continue
+            if skip > 0:
+                # Due to clang-format, values may come up in the next line
+                skip -= 1
+                continue
             line = line.strip()
 
             if line.startswith(MARKUP):  # markup for comments
@@ -148,6 +161,8 @@ def gen(lang):
                 continue
 
             tmp = line.strip().split(',')
+            if len(tmp) >= 2 and tmp[0] != "#define" and not tmp[0].startswith("UC_"):
+                continue
             for t in tmp:
                 t = t.strip()
                 if not t or t.startswith('//'): continue
@@ -159,18 +174,52 @@ def gen(lang):
                     define = True
                     f.pop(0)
                     f.insert(1, '=')
-
-                if f[0].startswith("UC_" + prefix.upper()):
+                if f[0].startswith("UC_" + prefix.upper()) or f[0].startswith("UC_CPU"):
                     if len(f) > 1 and f[1] not in ('//', '='):
                         print("WARNING: Unable to convert %s" % f)
                         print("  Line =", line)
                         continue
                     elif len(f) > 1 and f[1] == '=':
-                        rhs = ''.join(f[2:])
+                        # Like:
+                        # UC_A = 
+                        #       (1 << 2)
+                        # #define UC_B \
+                        #              (UC_A | UC_C)
+                        # Let's search the next line
+                        if len(f) == 2:
+                            if lno == len(lines) - 1:
+                                print("WARNING: Unable to convert %s" % f)
+                                print("  Line =", line)
+                                continue
+                            skip += 1
+                            next_line = lines[lno + 1]
+                            next_line_tmp = next_line.strip().split(",")
+                            rhs = next_line_tmp[0]
+                        elif f[-1] == "\\":
+                            idx = 0
+                            rhs = ""
+                            while True:
+                                idx += 1
+                                if lno + idx == len(lines):
+                                    print("WARNING: Unable to convert %s" % f)
+                                    print("  Line =", line)
+                                    continue
+                                skip += 1
+                                next_line = lines[lno + idx]
+                                next_line_f = re.split('\s+', next_line.strip())
+                                if next_line_f[-1] == "\\":
+                                    rhs += "".join(next_line_f[:-1])
+                                else:
+                                    rhs += next_line.strip()
+                                    break
+                        else:
+                            rhs = ''.join(f[2:])
                     else:
                         rhs = str(count)
 
+                    
                     lhs = f[0].strip()
+                    #print(f'lhs: {lhs} rhs: {rhs} f:{f}')
                     # evaluate bitshifts in constants e.g. "UC_X86 = 1 << 1"
                     match = re.match(r'(?P<rhs>\s*\d+\s*<<\s*\d+\s*)', rhs)
                     if match:
diff --git a/bindings/dotnet/UnicornManaged/Const/Arm.fs b/bindings/dotnet/UnicornManaged/Const/Arm.fs
index 76deda67..d0e039fe 100644
--- a/bindings/dotnet/UnicornManaged/Const/Arm.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Arm.fs
@@ -7,6 +7,40 @@ open System
 [<AutoOpen>]
 module Arm =
 
+    let UC_CPU_ARM_926 = 0
+    let UC_CPU_ARM_946 = 1
+    let UC_CPU_ARM_1026 = 2
+    let UC_CPU_ARM_1136_R2 = 3
+    let UC_CPU_ARM_1136 = 4
+    let UC_CPU_ARM_1176 = 5
+    let UC_CPU_ARM_11MPCORE = 6
+    let UC_CPU_ARM_CORTEX_M0 = 7
+    let UC_CPU_ARM_CORTEX_M3 = 8
+    let UC_CPU_ARM_CORTEX_M4 = 9
+    let UC_CPU_ARM_CORTEX_M7 = 10
+    let UC_CPU_ARM_CORTEX_M33 = 11
+    let UC_CPU_ARM_CORTEX_R5 = 12
+    let UC_CPU_ARM_CORTEX_R5F = 13
+    let UC_CPU_ARM_CORTEX_A8 = 14
+    let UC_CPU_ARM_CORTEX_A9 = 15
+    let UC_CPU_ARM_CORTEX_A7 = 16
+    let UC_CPU_ARM_CORTEX_A15 = 17
+    let UC_CPU_ARM_TI925T = 18
+    let UC_CPU_ARM_SA1100 = 19
+    let UC_CPU_ARM_SA1110 = 20
+    let UC_CPU_ARM_PXA250 = 21
+    let UC_CPU_ARM_PXA255 = 22
+    let UC_CPU_ARM_PXA260 = 23
+    let UC_CPU_ARM_PXA261 = 24
+    let UC_CPU_ARM_PXA262 = 25
+    let UC_CPU_ARM_PXA270A0 = 26
+    let UC_CPU_ARM_PXA270A1 = 27
+    let UC_CPU_ARM_PXA270B0 = 28
+    let UC_CPU_ARM_PXA270B1 = 29
+    let UC_CPU_ARM_PXA270C0 = 30
+    let UC_CPU_ARM_PXA270C5 = 31
+    let UC_CPU_ARM_MAX = 32
+
     // ARM registers
 
     let UC_ARM_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Arm64.fs b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
index a2ec894e..56d0de58 100644
--- a/bindings/dotnet/UnicornManaged/Const/Arm64.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Arm64.fs
@@ -7,6 +7,11 @@ open System
 [<AutoOpen>]
 module Arm64 =
 
+    let UC_CPU_AARCH64_A57 = 0
+    let UC_CPU_AARCH64_A53 = 1
+    let UC_CPU_AARCH64_A72 = 2
+    let UC_CPU_AARCH64_MAX = 3
+
     // ARM64 registers
 
     let UC_ARM64_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Common.fs b/bindings/dotnet/UnicornManaged/Const/Common.fs
index 0b91cac1..9ec83525 100644
--- a/bindings/dotnet/UnicornManaged/Const/Common.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Common.fs
@@ -112,6 +112,22 @@ module Common =
     let UC_QUERY_ARCH = 3
     let UC_QUERY_TIMEOUT = 4
 
+    let UC_CTL_IO_NONE = 0
+    let UC_CTL_IO_WRITE = 1
+    let UC_CTL_IO_READ = 2
+    let UC_CTL_IO_READ_WRITE = 3
+
+    let UC_CTL_UC_MODE = 0
+    let UC_CTL_UC_PAGE_SIZE = 1
+    let UC_CTL_UC_ARCH = 2
+    let UC_CTL_UC_TIMEOUT = 3
+    let UC_CTL_UC_EXITS_CNT = 4
+    let UC_CTL_UC_EXITS = 5
+    let UC_CTL_CPU_MODEL = 6
+    let UC_CTL_TB_EDGE = 7
+    let UC_CTL_TB_REQUEST_CACHE = 8
+    let UC_CTL_TB_REMOVE_CACHE = 9
+
     let UC_PROT_NONE = 0
     let UC_PROT_READ = 1
     let UC_PROT_WRITE = 2
diff --git a/bindings/dotnet/UnicornManaged/Const/M68k.fs b/bindings/dotnet/UnicornManaged/Const/M68k.fs
index 8fc5157e..36808a79 100644
--- a/bindings/dotnet/UnicornManaged/Const/M68k.fs
+++ b/bindings/dotnet/UnicornManaged/Const/M68k.fs
@@ -7,6 +7,16 @@ open System
 [<AutoOpen>]
 module M68k =
 
+    let UC_CPU_M5206_CPU = 0
+    let UC_CPU_M68000_CPU = 1
+    let UC_CPU_M68020_CPU = 2
+    let UC_CPU_M68030_CPU = 3
+    let UC_CPU_M68040_CPU = 4
+    let UC_CPU_M68060_CPU = 5
+    let UC_CPU_M5208_CPU = 6
+    let UC_CPU_CFV4E_CPU = 7
+    let UC_CPU_ANY_CPU = 8
+
     // M68K registers
 
     let UC_M68K_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Mips.fs b/bindings/dotnet/UnicornManaged/Const/Mips.fs
index a8ac5925..48a65287 100644
--- a/bindings/dotnet/UnicornManaged/Const/Mips.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Mips.fs
@@ -7,6 +7,36 @@ open System
 [<AutoOpen>]
 module Mips =
 
+    let UC_CPU_MIPS_4KC = 0
+    let UC_CPU_MIPS_4KM = 1
+    let UC_CPU_MIPS_4KECR1 = 2
+    let UC_CPU_MIPS_4KEMR1 = 3
+    let UC_CPU_MIPS_4KEC = 4
+    let UC_CPU_MIPS_4KEM = 5
+    let UC_CPU_MIPS_24KC = 6
+    let UC_CPU_MIPS_24KEC = 7
+    let UC_CPU_MIPS_24KF = 8
+    let UC_CPU_MIPS_34KF = 9
+    let UC_CPU_MIPS_74KF = 10
+    let UC_CPU_MIPS_M14K = 11
+    let UC_CPU_MIPS_M14KC = 12
+    let UC_CPU_MIPS_P5600 = 13
+    let UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+    let UC_CPU_MIPS_I7200 = 15
+    let UC_CPU_MIPS_R4000 = 16
+    let UC_CPU_MIPS_VR5432 = 17
+    let UC_CPU_MIPS_5KC = 18
+    let UC_CPU_MIPS_5KF = 19
+    let UC_CPU_MIPS_20KC = 20
+    let UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+    let UC_CPU_MIPS_5KEC = 22
+    let UC_CPU_MIPS_5KEF = 23
+    let UC_CPU_MIPS_I6400 = 24
+    let UC_CPU_MIPS_I6500 = 25
+    let UC_CPU_MIPS_LOONGSON_2E = 26
+    let UC_CPU_MIPS_LOONGSON_2F = 27
+    let UC_CPU_MIPS_MIPS64DSPR2 = 28
+
     // MIPS registers
 
     let UC_MIPS_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Ppc.fs b/bindings/dotnet/UnicornManaged/Const/Ppc.fs
index 2e6c91aa..cfa5be62 100644
--- a/bindings/dotnet/UnicornManaged/Const/Ppc.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Ppc.fs
@@ -7,6 +7,307 @@ open System
 [<AutoOpen>]
 module Ppc =
 
+    let UC_CPU_PPC_401A1 = 0
+    let UC_CPU_PPC_401B2 = 1
+    let UC_CPU_PPC_401C2 = 2
+    let UC_CPU_PPC_401D2 = 3
+    let UC_CPU_PPC_401E2 = 4
+    let UC_CPU_PPC_401F2 = 5
+    let UC_CPU_PPC_401G2 = 6
+    let UC_CPU_PPC_COBRA = 7
+    let UC_CPU_PPC_403GA = 8
+    let UC_CPU_PPC_403GB = 9
+    let UC_CPU_PPC_403GC = 10
+    let UC_CPU_PPC_403GCX = 11
+    let UC_CPU_PPC_405D2 = 12
+    let UC_CPU_PPC_405D4 = 13
+    let UC_CPU_PPC_405CRA = 14
+    let UC_CPU_PPC_405CRB = 15
+    let UC_CPU_PPC_405CRC = 16
+    let UC_CPU_PPC_405EP = 17
+    let UC_CPU_PPC_405EZ = 18
+    let UC_CPU_PPC_405GPA = 19
+    let UC_CPU_PPC_405GPB = 20
+    let UC_CPU_PPC_405GPC = 21
+    let UC_CPU_PPC_405GPD = 22
+    let UC_CPU_PPC_405GPR = 23
+    let UC_CPU_PPC_405LP = 24
+    let UC_CPU_PPC_NPE405H = 25
+    let UC_CPU_PPC_NPE405H2 = 26
+    let UC_CPU_PPC_NPE405L = 27
+    let UC_CPU_PPC_NPE4GS3 = 28
+    let UC_CPU_PPC_STB03 = 29
+    let UC_CPU_PPC_STB04 = 30
+    let UC_CPU_PPC_STB25 = 31
+    let UC_CPU_PPC_X2VP4 = 32
+    let UC_CPU_PPC_440_XILINX = 33
+    let UC_CPU_PPC_440EPA = 34
+    let UC_CPU_PPC_440EPB = 35
+    let UC_CPU_PPC_440GPB = 36
+    let UC_CPU_PPC_440GPC = 37
+    let UC_CPU_PPC_440GRX = 38
+    let UC_CPU_PPC_440GXA = 39
+    let UC_CPU_PPC_440GXB = 40
+    let UC_CPU_PPC_440GXC = 41
+    let UC_CPU_PPC_440GXF = 42
+    let UC_CPU_PPC_440SP = 43
+    let UC_CPU_PPC_440SP2 = 44
+    let UC_CPU_PPC_440SPE = 45
+    let UC_CPU_PPC_460EXB = 46
+    let UC_CPU_PPC_MPC5XX = 47
+    let UC_CPU_PPC_MPC8XX = 48
+    let UC_CPU_PPC_G2 = 49
+    let UC_CPU_PPC_G2H4 = 50
+    let UC_CPU_PPC_G2GP = 51
+    let UC_CPU_PPC_G2LS = 52
+    let UC_CPU_PPC_MPC603 = 53
+    let UC_CPU_PPC_G2_HIP3 = 54
+    let UC_CPU_PPC_G2_HIP4 = 55
+    let UC_CPU_PPC_G2LE = 56
+    let UC_CPU_PPC_G2LEGP = 57
+    let UC_CPU_PPC_G2LELS = 58
+    let UC_CPU_PPC_G2LEGP1 = 59
+    let UC_CPU_PPC_G2LEGP3 = 60
+    let UC_CPU_PPC_E200Z5 = 61
+    let UC_CPU_PPC_E200Z6 = 62
+    let UC_CPU_PPC_E300C1 = 63
+    let UC_CPU_PPC_E300C2 = 64
+    let UC_CPU_PPC_E300C3 = 65
+    let UC_CPU_PPC_E300C4 = 66
+    let UC_CPU_PPC_E500V1_V10 = 67
+    let UC_CPU_PPC_E500V1_V20 = 68
+    let UC_CPU_PPC_E500V2_V10 = 69
+    let UC_CPU_PPC_E500V2_V11 = 70
+    let UC_CPU_PPC_E500V2_V20 = 71
+    let UC_CPU_PPC_E500V2_V21 = 72
+    let UC_CPU_PPC_E500V2_V22 = 73
+    let UC_CPU_PPC_E500V2_V30 = 74
+    let UC_CPU_PPC_E500MC = 75
+    let UC_CPU_PPC_E5500 = 76
+    let UC_CPU_PPC_E6500 = 77
+    let UC_CPU_PPC_E600 = 78
+    let UC_CPU_PPC_601_V0 = 79
+    let UC_CPU_PPC_601_V1 = 80
+    let UC_CPU_PPC_601_V2 = 81
+    let UC_CPU_PPC_602 = 82
+    let UC_CPU_PPC_603 = 83
+    let UC_CPU_PPC_603E_V11 = 84
+    let UC_CPU_PPC_603E_V12 = 85
+    let UC_CPU_PPC_603E_V13 = 86
+    let UC_CPU_PPC_603E_V14 = 87
+    let UC_CPU_PPC_603E_V22 = 88
+    let UC_CPU_PPC_603E_V3 = 89
+    let UC_CPU_PPC_603E_V4 = 90
+    let UC_CPU_PPC_603E_V41 = 91
+    let UC_CPU_PPC_603E7T = 92
+    let UC_CPU_PPC_603E7V = 93
+    let UC_CPU_PPC_603E7V1 = 94
+    let UC_CPU_PPC_603E7V2 = 95
+    let UC_CPU_PPC_603E7 = 96
+    let UC_CPU_PPC_603P = 97
+    let UC_CPU_PPC_604 = 98
+    let UC_CPU_PPC_604E_V10 = 99
+    let UC_CPU_PPC_604E_V22 = 100
+    let UC_CPU_PPC_604E_V24 = 101
+    let UC_CPU_PPC_604R = 102
+    let UC_CPU_PPC_7X0_V10 = 103
+    let UC_CPU_PPC_7X0_V20 = 104
+    let UC_CPU_PPC_7X0_V21 = 105
+    let UC_CPU_PPC_7X0_V22 = 106
+    let UC_CPU_PPC_7X0_V30 = 107
+    let UC_CPU_PPC_7X0_V31 = 108
+    let UC_CPU_PPC_740E = 109
+    let UC_CPU_PPC_750E = 110
+    let UC_CPU_PPC_7X0P = 111
+    let UC_CPU_PPC_750CL_V10 = 112
+    let UC_CPU_PPC_750CL_V20 = 113
+    let UC_CPU_PPC_750CX_V10 = 114
+    let UC_CPU_PPC_750CX_V20 = 115
+    let UC_CPU_PPC_750CX_V21 = 116
+    let UC_CPU_PPC_750CX_V22 = 117
+    let UC_CPU_PPC_750CXE_V21 = 118
+    let UC_CPU_PPC_750CXE_V22 = 119
+    let UC_CPU_PPC_750CXE_V23 = 120
+    let UC_CPU_PPC_750CXE_V24 = 121
+    let UC_CPU_PPC_750CXE_V24B = 122
+    let UC_CPU_PPC_750CXE_V30 = 123
+    let UC_CPU_PPC_750CXE_V31 = 124
+    let UC_CPU_PPC_750CXE_V31B = 125
+    let UC_CPU_PPC_750CXR = 126
+    let UC_CPU_PPC_750FL = 127
+    let UC_CPU_PPC_750FX_V10 = 128
+    let UC_CPU_PPC_750FX_V20 = 129
+    let UC_CPU_PPC_750FX_V21 = 130
+    let UC_CPU_PPC_750FX_V22 = 131
+    let UC_CPU_PPC_750FX_V23 = 132
+    let UC_CPU_PPC_750GL = 133
+    let UC_CPU_PPC_750GX_V10 = 134
+    let UC_CPU_PPC_750GX_V11 = 135
+    let UC_CPU_PPC_750GX_V12 = 136
+    let UC_CPU_PPC_750L_V20 = 137
+    let UC_CPU_PPC_750L_V21 = 138
+    let UC_CPU_PPC_750L_V22 = 139
+    let UC_CPU_PPC_750L_V30 = 140
+    let UC_CPU_PPC_750L_V32 = 141
+    let UC_CPU_PPC_7X5_V10 = 142
+    let UC_CPU_PPC_7X5_V11 = 143
+    let UC_CPU_PPC_7X5_V20 = 144
+    let UC_CPU_PPC_7X5_V21 = 145
+    let UC_CPU_PPC_7X5_V22 = 146
+    let UC_CPU_PPC_7X5_V23 = 147
+    let UC_CPU_PPC_7X5_V24 = 148
+    let UC_CPU_PPC_7X5_V25 = 149
+    let UC_CPU_PPC_7X5_V26 = 150
+    let UC_CPU_PPC_7X5_V27 = 151
+    let UC_CPU_PPC_7X5_V28 = 152
+    let UC_CPU_PPC_7400_V10 = 153
+    let UC_CPU_PPC_7400_V11 = 154
+    let UC_CPU_PPC_7400_V20 = 155
+    let UC_CPU_PPC_7400_V21 = 156
+    let UC_CPU_PPC_7400_V22 = 157
+    let UC_CPU_PPC_7400_V26 = 158
+    let UC_CPU_PPC_7400_V27 = 159
+    let UC_CPU_PPC_7400_V28 = 160
+    let UC_CPU_PPC_7400_V29 = 161
+    let UC_CPU_PPC_7410_V10 = 162
+    let UC_CPU_PPC_7410_V11 = 163
+    let UC_CPU_PPC_7410_V12 = 164
+    let UC_CPU_PPC_7410_V13 = 165
+    let UC_CPU_PPC_7410_V14 = 166
+    let UC_CPU_PPC_7448_V10 = 167
+    let UC_CPU_PPC_7448_V11 = 168
+    let UC_CPU_PPC_7448_V20 = 169
+    let UC_CPU_PPC_7448_V21 = 170
+    let UC_CPU_PPC_7450_V10 = 171
+    let UC_CPU_PPC_7450_V11 = 172
+    let UC_CPU_PPC_7450_V12 = 173
+    let UC_CPU_PPC_7450_V20 = 174
+    let UC_CPU_PPC_7450_V21 = 175
+    let UC_CPU_PPC_74X1_V23 = 176
+    let UC_CPU_PPC_74X1_V210 = 177
+    let UC_CPU_PPC_74X5_V10 = 178
+    let UC_CPU_PPC_74X5_V21 = 179
+    let UC_CPU_PPC_74X5_V32 = 180
+    let UC_CPU_PPC_74X5_V33 = 181
+    let UC_CPU_PPC_74X5_V34 = 182
+    let UC_CPU_PPC_74X7_V10 = 183
+    let UC_CPU_PPC_74X7_V11 = 184
+    let UC_CPU_PPC_74X7_V12 = 185
+    let UC_CPU_PPC_74X7A_V10 = 186
+    let UC_CPU_PPC_74X7A_V11 = 187
+    let UC_CPU_PPC_74X7A_V12 = 188
+    let UC_CPU_PPC_IOP480 = 1
+    let UC_CPU_PPC_X2VP20 = 42
+    let UC_CPU_PPC_440GRA = 35
+    let UC_CPU_PPC_440EPX = 38
+    let UC_CPU_PPC_MPC5200_V10 = 59
+    let UC_CPU_PPC_MPC5200_V11 = 59
+    let UC_CPU_PPC_MPC5200_V12 = 59
+    let UC_CPU_PPC_MPC5200B_V20 = 59
+    let UC_CPU_PPC_MPC5200B_V21 = 59
+    let UC_CPU_PPC_MPC834X = 63
+    let UC_CPU_PPC_MPC837X = 66
+    let UC_CPU_PPC_E500 = 73
+    let UC_CPU_PPC_MPC8533_V10 = 72
+    let UC_CPU_PPC_MPC8533_V11 = 73
+    let UC_CPU_PPC_MPC8533E_V10 = 72
+    let UC_CPU_PPC_MPC8533E_V11 = 73
+    let UC_CPU_PPC_MPC8540_V10 = 67
+    let UC_CPU_PPC_MPC8540_V20 = 68
+    let UC_CPU_PPC_MPC8540_V21 = 68
+    let UC_CPU_PPC_MPC8541_V10 = 68
+    let UC_CPU_PPC_MPC8541_V11 = 68
+    let UC_CPU_PPC_MPC8541E_V10 = 68
+    let UC_CPU_PPC_MPC8541E_V11 = 68
+    let UC_CPU_PPC_MPC8543_V10 = 69
+    let UC_CPU_PPC_MPC8543_V11 = 70
+    let UC_CPU_PPC_MPC8543_V20 = 71
+    let UC_CPU_PPC_MPC8543_V21 = 72
+    let UC_CPU_PPC_MPC8543E_V10 = 69
+    let UC_CPU_PPC_MPC8543E_V11 = 70
+    let UC_CPU_PPC_MPC8543E_V20 = 71
+    let UC_CPU_PPC_MPC8543E_V21 = 72
+    let UC_CPU_PPC_MPC8544_V10 = 72
+    let UC_CPU_PPC_MPC8544_V11 = 73
+    let UC_CPU_PPC_MPC8544E_V11 = 73
+    let UC_CPU_PPC_MPC8544E_V10 = 72
+    let UC_CPU_PPC_MPC8545_V10 = 69
+    let UC_CPU_PPC_MPC8545_V20 = 71
+    let UC_CPU_PPC_MPC8545_V21 = 72
+    let UC_CPU_PPC_MPC8545E_V10 = 69
+    let UC_CPU_PPC_MPC8545E_V20 = 71
+    let UC_CPU_PPC_MPC8545E_V21 = 72
+    let UC_CPU_PPC_MPC8547E_V10 = 69
+    let UC_CPU_PPC_MPC8547E_V20 = 71
+    let UC_CPU_PPC_MPC8547E_V21 = 72
+    let UC_CPU_PPC_MPC8548_V10 = 69
+    let UC_CPU_PPC_MPC8548_V11 = 70
+    let UC_CPU_PPC_MPC8548_V20 = 71
+    let UC_CPU_PPC_MPC8548_V21 = 72
+    let UC_CPU_PPC_MPC8548E_V10 = 69
+    let UC_CPU_PPC_MPC8548E_V11 = 70
+    let UC_CPU_PPC_MPC8548E_V20 = 71
+    let UC_CPU_PPC_MPC8548E_V21 = 72
+    let UC_CPU_PPC_MPC8555_V10 = 69
+    let UC_CPU_PPC_MPC8555_V11 = 70
+    let UC_CPU_PPC_MPC8555E_V10 = 69
+    let UC_CPU_PPC_MPC8555E_V11 = 70
+    let UC_CPU_PPC_MPC8560_V10 = 69
+    let UC_CPU_PPC_MPC8560_V20 = 71
+    let UC_CPU_PPC_MPC8560_V21 = 72
+    let UC_CPU_PPC_MPC8567 = 73
+    let UC_CPU_PPC_MPC8567E = 73
+    let UC_CPU_PPC_MPC8568 = 73
+    let UC_CPU_PPC_MPC8568E = 73
+    let UC_CPU_PPC_MPC8572 = 74
+    let UC_CPU_PPC_MPC8572E = 74
+    let UC_CPU_PPC_MPC8610 = 78
+    let UC_CPU_PPC_MPC8641 = 78
+    let UC_CPU_PPC_MPC8641D = 78
+
+    let UC_CPU_PPC64_620 = 0
+    let UC_CPU_PPC64_630 = 1
+    let UC_CPU_PPC64_631 = 2
+    let UC_CPU_PPC64_POWER4 = 3
+    let UC_CPU_PPC64_POWER4P = 4
+    let UC_CPU_PPC64_POWER5 = 5
+    let UC_CPU_PPC64_POWER5P_V21 = 6
+    let UC_CPU_PPC64_POWER6 = 7
+    let UC_CPU_PPC64_POWER_SERVER_MASK = 8
+    let UC_CPU_PPC64_POWER7_BASE = 9
+    let UC_CPU_PPC64_POWER7_V23 = 10
+    let UC_CPU_PPC64_POWER7P_BASE = 11
+    let UC_CPU_PPC64_POWER7P_V21 = 12
+    let UC_CPU_PPC64_POWER8E_BASE = 13
+    let UC_CPU_PPC64_POWER8E_V21 = 14
+    let UC_CPU_PPC64_POWER8_BASE = 15
+    let UC_CPU_PPC64_POWER8_V20 = 16
+    let UC_CPU_PPC64_POWER8NVL_BASE = 17
+    let UC_CPU_PPC64_POWER8NVL_V10 = 18
+    let UC_CPU_PPC64_POWER9_BASE = 19
+    let UC_CPU_PPC64_POWER9_DD1 = 20
+    let UC_CPU_PPC64_POWER9_DD20 = 21
+    let UC_CPU_PPC64_POWER10_BASE = 22
+    let UC_CPU_PPC64_POWER10_DD1 = 23
+    let UC_CPU_PPC64_970_V22 = 24
+    let UC_CPU_PPC64_970FX_V10 = 25
+    let UC_CPU_PPC64_970FX_V20 = 26
+    let UC_CPU_PPC64_970FX_V21 = 27
+    let UC_CPU_PPC64_970FX_V30 = 28
+    let UC_CPU_PPC64_970FX_V31 = 29
+    let UC_CPU_PPC64_970MP_V10 = 30
+    let UC_CPU_PPC64_970MP_V11 = 31
+    let UC_CPU_PPC64_CELL_V10 = 32
+    let UC_CPU_PPC64_CELL_V20 = 33
+    let UC_CPU_PPC64_CELL_V30 = 34
+    let UC_CPU_PPC64_CELL_V31 = 35
+    let UC_CPU_PPC64_RS64 = 36
+    let UC_CPU_PPC64_RS64II = 37
+    let UC_CPU_PPC64_RS64III = 38
+    let UC_CPU_PPC64_RS64IV = 39
+    let UC_CPU_PPC64_CELL_V32 = 35
+    let UC_CPU_PPC64_CELL = 35
+
     // PPC registers
 
     let UC_PPC_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Riscv.fs b/bindings/dotnet/UnicornManaged/Const/Riscv.fs
index 5fd11e95..ca5881f1 100644
--- a/bindings/dotnet/UnicornManaged/Const/Riscv.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Riscv.fs
@@ -7,6 +7,16 @@ open System
 [<AutoOpen>]
 module Riscv =
 
+    let UC_CPU_RISCV32_ANY = 0
+    let UC_CPU_RISCV32_BASE32 = 1
+    let UC_CPU_RISCV32_SIFIVE_E31 = 2
+    let UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+    let UC_CPU_RISCV64_ANY = 0
+    let UC_CPU_RISCV64_BASE64 = 1
+    let UC_CPU_RISCV64_SIFIVE_E51 = 2
+    let UC_CPU_RISCV64_SIFIVE_U54 = 3
+
     // RISCV registers
 
     let UC_RISCV_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/Sparc.fs b/bindings/dotnet/UnicornManaged/Const/Sparc.fs
index 9a91e1a7..c6c15dd6 100644
--- a/bindings/dotnet/UnicornManaged/Const/Sparc.fs
+++ b/bindings/dotnet/UnicornManaged/Const/Sparc.fs
@@ -7,6 +7,38 @@ open System
 [<AutoOpen>]
 module Sparc =
 
+    let UC_CPU_SPARC_FUJITSU_MB86904 = 0
+    let UC_CPU_SPARC_FUJITSU_MB86907 = 1
+    let UC_CPU_SPARC_TI_MICROSPARC_I = 2
+    let UC_CPU_SPARC_TI_MICROSPARC_II = 3
+    let UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+    let UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+    let UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+    let UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+    let UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+    let UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+    let UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+    let UC_CPU_SPARC_LEON2 = 11
+    let UC_CPU_SPARC_LEON3 = 12
+
+    let UC_CPU_SPARC64_FUJITSU = 0
+    let UC_CPU_SPARC64_FUJITSU_III = 1
+    let UC_CPU_SPARC64_FUJITSU_IV = 2
+    let UC_CPU_SPARC64_FUJITSU_V = 3
+    let UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+    let UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+    let UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+    let UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+    let UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
     // SPARC registers
 
     let UC_SPARC_REG_INVALID = 0
diff --git a/bindings/dotnet/UnicornManaged/Const/X86.fs b/bindings/dotnet/UnicornManaged/Const/X86.fs
index fd5ddba6..11c7217b 100644
--- a/bindings/dotnet/UnicornManaged/Const/X86.fs
+++ b/bindings/dotnet/UnicornManaged/Const/X86.fs
@@ -7,6 +7,45 @@ open System
 [<AutoOpen>]
 module X86 =
 
+    let UC_CPU_X86_QEMU64 = 0
+    let UC_CPU_X86_PHENOM = 1
+    let UC_CPU_X86_CORE2DUO = 2
+    let UC_CPU_X86_KVM64 = 3
+    let UC_CPU_X86_QEMU32 = 4
+    let UC_CPU_X86_KVM32 = 5
+    let UC_CPU_X86_COREDUO = 6
+    let UC_CPU_X86_486 = 7
+    let UC_CPU_X86_PENTIUM = 8
+    let UC_CPU_X86_PENTIUM2 = 9
+    let UC_CPU_X86_PENTIUM3 = 10
+    let UC_CPU_X86_ATHLON = 11
+    let UC_CPU_X86_N270 = 12
+    let UC_CPU_X86_CONROE = 13
+    let UC_CPU_X86_PENRYN = 14
+    let UC_CPU_X86_NEHALEM = 15
+    let UC_CPU_X86_WESTMERE = 16
+    let UC_CPU_X86_SANDYBRIDGE = 17
+    let UC_CPU_X86_IVYBRIDGE = 18
+    let UC_CPU_X86_HASWELL = 19
+    let UC_CPU_X86_BROADWELL = 20
+    let UC_CPU_X86_SKYLAKE_CLIENT = 21
+    let UC_CPU_X86_SKYLAKE_SERVER = 22
+    let UC_CPU_X86_CASCADELAKE_SERVER = 23
+    let UC_CPU_X86_COOPERLAKE = 24
+    let UC_CPU_X86_ICELAKE_CLIENT = 25
+    let UC_CPU_X86_ICELAKE_SERVER = 26
+    let UC_CPU_X86_DENVERTON = 27
+    let UC_CPU_X86_SNOWRIDGE = 28
+    let UC_CPU_X86_KNIGHTSMILL = 29
+    let UC_CPU_X86_OPTERON_G1 = 30
+    let UC_CPU_X86_OPTERON_G2 = 31
+    let UC_CPU_X86_OPTERON_G3 = 32
+    let UC_CPU_X86_OPTERON_G4 = 33
+    let UC_CPU_X86_OPTERON_G5 = 34
+    let UC_CPU_X86_EPYC = 35
+    let UC_CPU_X86_DHYANA = 36
+    let UC_CPU_X86_EPYC_ROME = 37
+
     // X86 registers
 
     let UC_X86_REG_INVALID = 0
diff --git a/bindings/go/unicorn/arm64_const.go b/bindings/go/unicorn/arm64_const.go
index fb8dc906..d2bfd18a 100644
--- a/bindings/go/unicorn/arm64_const.go
+++ b/bindings/go/unicorn/arm64_const.go
@@ -2,6 +2,11 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.go]
 const (
 
+	CPU_AARCH64_A57 = 0
+	CPU_AARCH64_A53 = 1
+	CPU_AARCH64_A72 = 2
+	CPU_AARCH64_MAX = 3
+
 // ARM64 registers
 
 	ARM64_REG_INVALID = 0
diff --git a/bindings/go/unicorn/arm_const.go b/bindings/go/unicorn/arm_const.go
index eab0e336..007c9cad 100644
--- a/bindings/go/unicorn/arm_const.go
+++ b/bindings/go/unicorn/arm_const.go
@@ -2,6 +2,40 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.go]
 const (
 
+	CPU_ARM_926 = 0
+	CPU_ARM_946 = 1
+	CPU_ARM_1026 = 2
+	CPU_ARM_1136_R2 = 3
+	CPU_ARM_1136 = 4
+	CPU_ARM_1176 = 5
+	CPU_ARM_11MPCORE = 6
+	CPU_ARM_CORTEX_M0 = 7
+	CPU_ARM_CORTEX_M3 = 8
+	CPU_ARM_CORTEX_M4 = 9
+	CPU_ARM_CORTEX_M7 = 10
+	CPU_ARM_CORTEX_M33 = 11
+	CPU_ARM_CORTEX_R5 = 12
+	CPU_ARM_CORTEX_R5F = 13
+	CPU_ARM_CORTEX_A8 = 14
+	CPU_ARM_CORTEX_A9 = 15
+	CPU_ARM_CORTEX_A7 = 16
+	CPU_ARM_CORTEX_A15 = 17
+	CPU_ARM_TI925T = 18
+	CPU_ARM_SA1100 = 19
+	CPU_ARM_SA1110 = 20
+	CPU_ARM_PXA250 = 21
+	CPU_ARM_PXA255 = 22
+	CPU_ARM_PXA260 = 23
+	CPU_ARM_PXA261 = 24
+	CPU_ARM_PXA262 = 25
+	CPU_ARM_PXA270A0 = 26
+	CPU_ARM_PXA270A1 = 27
+	CPU_ARM_PXA270B0 = 28
+	CPU_ARM_PXA270B1 = 29
+	CPU_ARM_PXA270C0 = 30
+	CPU_ARM_PXA270C5 = 31
+	CPU_ARM_MAX = 32
+
 // ARM registers
 
 	ARM_REG_INVALID = 0
diff --git a/bindings/go/unicorn/m68k_const.go b/bindings/go/unicorn/m68k_const.go
index 36ba914a..efa02e03 100644
--- a/bindings/go/unicorn/m68k_const.go
+++ b/bindings/go/unicorn/m68k_const.go
@@ -2,6 +2,16 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.go]
 const (
 
+	CPU_M5206_CPU = 0
+	CPU_M68000_CPU = 1
+	CPU_M68020_CPU = 2
+	CPU_M68030_CPU = 3
+	CPU_M68040_CPU = 4
+	CPU_M68060_CPU = 5
+	CPU_M5208_CPU = 6
+	CPU_CFV4E_CPU = 7
+	CPU_ANY_CPU = 8
+
 // M68K registers
 
 	M68K_REG_INVALID = 0
diff --git a/bindings/go/unicorn/mips_const.go b/bindings/go/unicorn/mips_const.go
index 20a33756..e45291b5 100644
--- a/bindings/go/unicorn/mips_const.go
+++ b/bindings/go/unicorn/mips_const.go
@@ -2,6 +2,36 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.go]
 const (
 
+	CPU_MIPS_4KC = 0
+	CPU_MIPS_4KM = 1
+	CPU_MIPS_4KECR1 = 2
+	CPU_MIPS_4KEMR1 = 3
+	CPU_MIPS_4KEC = 4
+	CPU_MIPS_4KEM = 5
+	CPU_MIPS_24KC = 6
+	CPU_MIPS_24KEC = 7
+	CPU_MIPS_24KF = 8
+	CPU_MIPS_34KF = 9
+	CPU_MIPS_74KF = 10
+	CPU_MIPS_M14K = 11
+	CPU_MIPS_M14KC = 12
+	CPU_MIPS_P5600 = 13
+	CPU_MIPS_MIPS32R6_GENERIC = 14
+	CPU_MIPS_I7200 = 15
+	CPU_MIPS_R4000 = 16
+	CPU_MIPS_VR5432 = 17
+	CPU_MIPS_5KC = 18
+	CPU_MIPS_5KF = 19
+	CPU_MIPS_20KC = 20
+	CPU_MIPS_MIPS64R2_GENERIC = 21
+	CPU_MIPS_5KEC = 22
+	CPU_MIPS_5KEF = 23
+	CPU_MIPS_I6400 = 24
+	CPU_MIPS_I6500 = 25
+	CPU_MIPS_LOONGSON_2E = 26
+	CPU_MIPS_LOONGSON_2F = 27
+	CPU_MIPS_MIPS64DSPR2 = 28
+
 // MIPS registers
 
 	MIPS_REG_INVALID = 0
diff --git a/bindings/go/unicorn/ppc_const.go b/bindings/go/unicorn/ppc_const.go
index f0180eeb..03eba18e 100644
--- a/bindings/go/unicorn/ppc_const.go
+++ b/bindings/go/unicorn/ppc_const.go
@@ -2,6 +2,307 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.go]
 const (
 
+	CPU_PPC_401A1 = 0
+	CPU_PPC_401B2 = 1
+	CPU_PPC_401C2 = 2
+	CPU_PPC_401D2 = 3
+	CPU_PPC_401E2 = 4
+	CPU_PPC_401F2 = 5
+	CPU_PPC_401G2 = 6
+	CPU_PPC_COBRA = 7
+	CPU_PPC_403GA = 8
+	CPU_PPC_403GB = 9
+	CPU_PPC_403GC = 10
+	CPU_PPC_403GCX = 11
+	CPU_PPC_405D2 = 12
+	CPU_PPC_405D4 = 13
+	CPU_PPC_405CRA = 14
+	CPU_PPC_405CRB = 15
+	CPU_PPC_405CRC = 16
+	CPU_PPC_405EP = 17
+	CPU_PPC_405EZ = 18
+	CPU_PPC_405GPA = 19
+	CPU_PPC_405GPB = 20
+	CPU_PPC_405GPC = 21
+	CPU_PPC_405GPD = 22
+	CPU_PPC_405GPR = 23
+	CPU_PPC_405LP = 24
+	CPU_PPC_NPE405H = 25
+	CPU_PPC_NPE405H2 = 26
+	CPU_PPC_NPE405L = 27
+	CPU_PPC_NPE4GS3 = 28
+	CPU_PPC_STB03 = 29
+	CPU_PPC_STB04 = 30
+	CPU_PPC_STB25 = 31
+	CPU_PPC_X2VP4 = 32
+	CPU_PPC_440_XILINX = 33
+	CPU_PPC_440EPA = 34
+	CPU_PPC_440EPB = 35
+	CPU_PPC_440GPB = 36
+	CPU_PPC_440GPC = 37
+	CPU_PPC_440GRX = 38
+	CPU_PPC_440GXA = 39
+	CPU_PPC_440GXB = 40
+	CPU_PPC_440GXC = 41
+	CPU_PPC_440GXF = 42
+	CPU_PPC_440SP = 43
+	CPU_PPC_440SP2 = 44
+	CPU_PPC_440SPE = 45
+	CPU_PPC_460EXB = 46
+	CPU_PPC_MPC5XX = 47
+	CPU_PPC_MPC8XX = 48
+	CPU_PPC_G2 = 49
+	CPU_PPC_G2H4 = 50
+	CPU_PPC_G2GP = 51
+	CPU_PPC_G2LS = 52
+	CPU_PPC_MPC603 = 53
+	CPU_PPC_G2_HIP3 = 54
+	CPU_PPC_G2_HIP4 = 55
+	CPU_PPC_G2LE = 56
+	CPU_PPC_G2LEGP = 57
+	CPU_PPC_G2LELS = 58
+	CPU_PPC_G2LEGP1 = 59
+	CPU_PPC_G2LEGP3 = 60
+	CPU_PPC_E200Z5 = 61
+	CPU_PPC_E200Z6 = 62
+	CPU_PPC_E300C1 = 63
+	CPU_PPC_E300C2 = 64
+	CPU_PPC_E300C3 = 65
+	CPU_PPC_E300C4 = 66
+	CPU_PPC_E500V1_V10 = 67
+	CPU_PPC_E500V1_V20 = 68
+	CPU_PPC_E500V2_V10 = 69
+	CPU_PPC_E500V2_V11 = 70
+	CPU_PPC_E500V2_V20 = 71
+	CPU_PPC_E500V2_V21 = 72
+	CPU_PPC_E500V2_V22 = 73
+	CPU_PPC_E500V2_V30 = 74
+	CPU_PPC_E500MC = 75
+	CPU_PPC_E5500 = 76
+	CPU_PPC_E6500 = 77
+	CPU_PPC_E600 = 78
+	CPU_PPC_601_V0 = 79
+	CPU_PPC_601_V1 = 80
+	CPU_PPC_601_V2 = 81
+	CPU_PPC_602 = 82
+	CPU_PPC_603 = 83
+	CPU_PPC_603E_V11 = 84
+	CPU_PPC_603E_V12 = 85
+	CPU_PPC_603E_V13 = 86
+	CPU_PPC_603E_V14 = 87
+	CPU_PPC_603E_V22 = 88
+	CPU_PPC_603E_V3 = 89
+	CPU_PPC_603E_V4 = 90
+	CPU_PPC_603E_V41 = 91
+	CPU_PPC_603E7T = 92
+	CPU_PPC_603E7V = 93
+	CPU_PPC_603E7V1 = 94
+	CPU_PPC_603E7V2 = 95
+	CPU_PPC_603E7 = 96
+	CPU_PPC_603P = 97
+	CPU_PPC_604 = 98
+	CPU_PPC_604E_V10 = 99
+	CPU_PPC_604E_V22 = 100
+	CPU_PPC_604E_V24 = 101
+	CPU_PPC_604R = 102
+	CPU_PPC_7X0_V10 = 103
+	CPU_PPC_7X0_V20 = 104
+	CPU_PPC_7X0_V21 = 105
+	CPU_PPC_7X0_V22 = 106
+	CPU_PPC_7X0_V30 = 107
+	CPU_PPC_7X0_V31 = 108
+	CPU_PPC_740E = 109
+	CPU_PPC_750E = 110
+	CPU_PPC_7X0P = 111
+	CPU_PPC_750CL_V10 = 112
+	CPU_PPC_750CL_V20 = 113
+	CPU_PPC_750CX_V10 = 114
+	CPU_PPC_750CX_V20 = 115
+	CPU_PPC_750CX_V21 = 116
+	CPU_PPC_750CX_V22 = 117
+	CPU_PPC_750CXE_V21 = 118
+	CPU_PPC_750CXE_V22 = 119
+	CPU_PPC_750CXE_V23 = 120
+	CPU_PPC_750CXE_V24 = 121
+	CPU_PPC_750CXE_V24B = 122
+	CPU_PPC_750CXE_V30 = 123
+	CPU_PPC_750CXE_V31 = 124
+	CPU_PPC_750CXE_V31B = 125
+	CPU_PPC_750CXR = 126
+	CPU_PPC_750FL = 127
+	CPU_PPC_750FX_V10 = 128
+	CPU_PPC_750FX_V20 = 129
+	CPU_PPC_750FX_V21 = 130
+	CPU_PPC_750FX_V22 = 131
+	CPU_PPC_750FX_V23 = 132
+	CPU_PPC_750GL = 133
+	CPU_PPC_750GX_V10 = 134
+	CPU_PPC_750GX_V11 = 135
+	CPU_PPC_750GX_V12 = 136
+	CPU_PPC_750L_V20 = 137
+	CPU_PPC_750L_V21 = 138
+	CPU_PPC_750L_V22 = 139
+	CPU_PPC_750L_V30 = 140
+	CPU_PPC_750L_V32 = 141
+	CPU_PPC_7X5_V10 = 142
+	CPU_PPC_7X5_V11 = 143
+	CPU_PPC_7X5_V20 = 144
+	CPU_PPC_7X5_V21 = 145
+	CPU_PPC_7X5_V22 = 146
+	CPU_PPC_7X5_V23 = 147
+	CPU_PPC_7X5_V24 = 148
+	CPU_PPC_7X5_V25 = 149
+	CPU_PPC_7X5_V26 = 150
+	CPU_PPC_7X5_V27 = 151
+	CPU_PPC_7X5_V28 = 152
+	CPU_PPC_7400_V10 = 153
+	CPU_PPC_7400_V11 = 154
+	CPU_PPC_7400_V20 = 155
+	CPU_PPC_7400_V21 = 156
+	CPU_PPC_7400_V22 = 157
+	CPU_PPC_7400_V26 = 158
+	CPU_PPC_7400_V27 = 159
+	CPU_PPC_7400_V28 = 160
+	CPU_PPC_7400_V29 = 161
+	CPU_PPC_7410_V10 = 162
+	CPU_PPC_7410_V11 = 163
+	CPU_PPC_7410_V12 = 164
+	CPU_PPC_7410_V13 = 165
+	CPU_PPC_7410_V14 = 166
+	CPU_PPC_7448_V10 = 167
+	CPU_PPC_7448_V11 = 168
+	CPU_PPC_7448_V20 = 169
+	CPU_PPC_7448_V21 = 170
+	CPU_PPC_7450_V10 = 171
+	CPU_PPC_7450_V11 = 172
+	CPU_PPC_7450_V12 = 173
+	CPU_PPC_7450_V20 = 174
+	CPU_PPC_7450_V21 = 175
+	CPU_PPC_74X1_V23 = 176
+	CPU_PPC_74X1_V210 = 177
+	CPU_PPC_74X5_V10 = 178
+	CPU_PPC_74X5_V21 = 179
+	CPU_PPC_74X5_V32 = 180
+	CPU_PPC_74X5_V33 = 181
+	CPU_PPC_74X5_V34 = 182
+	CPU_PPC_74X7_V10 = 183
+	CPU_PPC_74X7_V11 = 184
+	CPU_PPC_74X7_V12 = 185
+	CPU_PPC_74X7A_V10 = 186
+	CPU_PPC_74X7A_V11 = 187
+	CPU_PPC_74X7A_V12 = 188
+	CPU_PPC_IOP480 = 1
+	CPU_PPC_X2VP20 = 42
+	CPU_PPC_440GRA = 35
+	CPU_PPC_440EPX = 38
+	CPU_PPC_MPC5200_V10 = 59
+	CPU_PPC_MPC5200_V11 = 59
+	CPU_PPC_MPC5200_V12 = 59
+	CPU_PPC_MPC5200B_V20 = 59
+	CPU_PPC_MPC5200B_V21 = 59
+	CPU_PPC_MPC834X = 63
+	CPU_PPC_MPC837X = 66
+	CPU_PPC_E500 = 73
+	CPU_PPC_MPC8533_V10 = 72
+	CPU_PPC_MPC8533_V11 = 73
+	CPU_PPC_MPC8533E_V10 = 72
+	CPU_PPC_MPC8533E_V11 = 73
+	CPU_PPC_MPC8540_V10 = 67
+	CPU_PPC_MPC8540_V20 = 68
+	CPU_PPC_MPC8540_V21 = 68
+	CPU_PPC_MPC8541_V10 = 68
+	CPU_PPC_MPC8541_V11 = 68
+	CPU_PPC_MPC8541E_V10 = 68
+	CPU_PPC_MPC8541E_V11 = 68
+	CPU_PPC_MPC8543_V10 = 69
+	CPU_PPC_MPC8543_V11 = 70
+	CPU_PPC_MPC8543_V20 = 71
+	CPU_PPC_MPC8543_V21 = 72
+	CPU_PPC_MPC8543E_V10 = 69
+	CPU_PPC_MPC8543E_V11 = 70
+	CPU_PPC_MPC8543E_V20 = 71
+	CPU_PPC_MPC8543E_V21 = 72
+	CPU_PPC_MPC8544_V10 = 72
+	CPU_PPC_MPC8544_V11 = 73
+	CPU_PPC_MPC8544E_V11 = 73
+	CPU_PPC_MPC8544E_V10 = 72
+	CPU_PPC_MPC8545_V10 = 69
+	CPU_PPC_MPC8545_V20 = 71
+	CPU_PPC_MPC8545_V21 = 72
+	CPU_PPC_MPC8545E_V10 = 69
+	CPU_PPC_MPC8545E_V20 = 71
+	CPU_PPC_MPC8545E_V21 = 72
+	CPU_PPC_MPC8547E_V10 = 69
+	CPU_PPC_MPC8547E_V20 = 71
+	CPU_PPC_MPC8547E_V21 = 72
+	CPU_PPC_MPC8548_V10 = 69
+	CPU_PPC_MPC8548_V11 = 70
+	CPU_PPC_MPC8548_V20 = 71
+	CPU_PPC_MPC8548_V21 = 72
+	CPU_PPC_MPC8548E_V10 = 69
+	CPU_PPC_MPC8548E_V11 = 70
+	CPU_PPC_MPC8548E_V20 = 71
+	CPU_PPC_MPC8548E_V21 = 72
+	CPU_PPC_MPC8555_V10 = 69
+	CPU_PPC_MPC8555_V11 = 70
+	CPU_PPC_MPC8555E_V10 = 69
+	CPU_PPC_MPC8555E_V11 = 70
+	CPU_PPC_MPC8560_V10 = 69
+	CPU_PPC_MPC8560_V20 = 71
+	CPU_PPC_MPC8560_V21 = 72
+	CPU_PPC_MPC8567 = 73
+	CPU_PPC_MPC8567E = 73
+	CPU_PPC_MPC8568 = 73
+	CPU_PPC_MPC8568E = 73
+	CPU_PPC_MPC8572 = 74
+	CPU_PPC_MPC8572E = 74
+	CPU_PPC_MPC8610 = 78
+	CPU_PPC_MPC8641 = 78
+	CPU_PPC_MPC8641D = 78
+
+	CPU_PPC64_620 = 0
+	CPU_PPC64_630 = 1
+	CPU_PPC64_631 = 2
+	CPU_PPC64_POWER4 = 3
+	CPU_PPC64_POWER4P = 4
+	CPU_PPC64_POWER5 = 5
+	CPU_PPC64_POWER5P_V21 = 6
+	CPU_PPC64_POWER6 = 7
+	CPU_PPC64_POWER_SERVER_MASK = 8
+	CPU_PPC64_POWER7_BASE = 9
+	CPU_PPC64_POWER7_V23 = 10
+	CPU_PPC64_POWER7P_BASE = 11
+	CPU_PPC64_POWER7P_V21 = 12
+	CPU_PPC64_POWER8E_BASE = 13
+	CPU_PPC64_POWER8E_V21 = 14
+	CPU_PPC64_POWER8_BASE = 15
+	CPU_PPC64_POWER8_V20 = 16
+	CPU_PPC64_POWER8NVL_BASE = 17
+	CPU_PPC64_POWER8NVL_V10 = 18
+	CPU_PPC64_POWER9_BASE = 19
+	CPU_PPC64_POWER9_DD1 = 20
+	CPU_PPC64_POWER9_DD20 = 21
+	CPU_PPC64_POWER10_BASE = 22
+	CPU_PPC64_POWER10_DD1 = 23
+	CPU_PPC64_970_V22 = 24
+	CPU_PPC64_970FX_V10 = 25
+	CPU_PPC64_970FX_V20 = 26
+	CPU_PPC64_970FX_V21 = 27
+	CPU_PPC64_970FX_V30 = 28
+	CPU_PPC64_970FX_V31 = 29
+	CPU_PPC64_970MP_V10 = 30
+	CPU_PPC64_970MP_V11 = 31
+	CPU_PPC64_CELL_V10 = 32
+	CPU_PPC64_CELL_V20 = 33
+	CPU_PPC64_CELL_V30 = 34
+	CPU_PPC64_CELL_V31 = 35
+	CPU_PPC64_RS64 = 36
+	CPU_PPC64_RS64II = 37
+	CPU_PPC64_RS64III = 38
+	CPU_PPC64_RS64IV = 39
+	CPU_PPC64_CELL_V32 = 35
+	CPU_PPC64_CELL = 35
+
 // PPC registers
 
 	PPC_REG_INVALID = 0
diff --git a/bindings/go/unicorn/riscv_const.go b/bindings/go/unicorn/riscv_const.go
index 506a9f90..4295dcc6 100644
--- a/bindings/go/unicorn/riscv_const.go
+++ b/bindings/go/unicorn/riscv_const.go
@@ -2,6 +2,16 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.go]
 const (
 
+	CPU_RISCV32_ANY = 0
+	CPU_RISCV32_BASE32 = 1
+	CPU_RISCV32_SIFIVE_E31 = 2
+	CPU_RISCV32_SIFIVE_U34 = 3
+
+	CPU_RISCV64_ANY = 0
+	CPU_RISCV64_BASE64 = 1
+	CPU_RISCV64_SIFIVE_E51 = 2
+	CPU_RISCV64_SIFIVE_U54 = 3
+
 // RISCV registers
 
 	RISCV_REG_INVALID = 0
diff --git a/bindings/go/unicorn/sparc_const.go b/bindings/go/unicorn/sparc_const.go
index afd94f45..02bea244 100644
--- a/bindings/go/unicorn/sparc_const.go
+++ b/bindings/go/unicorn/sparc_const.go
@@ -2,6 +2,38 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.go]
 const (
 
+	CPU_SPARC_FUJITSU_MB86904 = 0
+	CPU_SPARC_FUJITSU_MB86907 = 1
+	CPU_SPARC_TI_MICROSPARC_I = 2
+	CPU_SPARC_TI_MICROSPARC_II = 3
+	CPU_SPARC_TI_MICROSPARC_IIEP = 4
+	CPU_SPARC_TI_SUPERSPARC_40 = 5
+	CPU_SPARC_TI_SUPERSPARC_50 = 6
+	CPU_SPARC_TI_SUPERSPARC_51 = 7
+	CPU_SPARC_TI_SUPERSPARC_60 = 8
+	CPU_SPARC_TI_SUPERSPARC_61 = 9
+	CPU_SPARC_TI_SUPERSPARC_II = 10
+	CPU_SPARC_LEON2 = 11
+	CPU_SPARC_LEON3 = 12
+
+	CPU_SPARC64_FUJITSU = 0
+	CPU_SPARC64_FUJITSU_III = 1
+	CPU_SPARC64_FUJITSU_IV = 2
+	CPU_SPARC64_FUJITSU_V = 3
+	CPU_SPARC64_TI_ULTRASPARC_I = 4
+	CPU_SPARC64_TI_ULTRASPARC_II = 5
+	CPU_SPARC64_TI_ULTRASPARC_III = 6
+	CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+	CPU_SPARC64_SUN_ULTRASPARC_III = 8
+	CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+	CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+	CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+	CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+	CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+	CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+	CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+	CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 // SPARC registers
 
 	SPARC_REG_INVALID = 0
diff --git a/bindings/go/unicorn/unicorn_const.go b/bindings/go/unicorn/unicorn_const.go
index 6196fde5..883453da 100644
--- a/bindings/go/unicorn/unicorn_const.go
+++ b/bindings/go/unicorn/unicorn_const.go
@@ -107,6 +107,22 @@ const (
 	QUERY_ARCH = 3
 	QUERY_TIMEOUT = 4
 
+	CTL_IO_NONE = 0
+	CTL_IO_WRITE = 1
+	CTL_IO_READ = 2
+	CTL_IO_READ_WRITE = 3
+
+	CTL_UC_MODE = 0
+	CTL_UC_PAGE_SIZE = 1
+	CTL_UC_ARCH = 2
+	CTL_UC_TIMEOUT = 3
+	CTL_UC_EXITS_CNT = 4
+	CTL_UC_EXITS = 5
+	CTL_CPU_MODEL = 6
+	CTL_TB_EDGE = 7
+	CTL_TB_REQUEST_CACHE = 8
+	CTL_TB_REMOVE_CACHE = 9
+
 	PROT_NONE = 0
 	PROT_READ = 1
 	PROT_WRITE = 2
diff --git a/bindings/go/unicorn/x86_const.go b/bindings/go/unicorn/x86_const.go
index 2a5015bf..c8c45848 100644
--- a/bindings/go/unicorn/x86_const.go
+++ b/bindings/go/unicorn/x86_const.go
@@ -2,6 +2,45 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.go]
 const (
 
+	CPU_X86_QEMU64 = 0
+	CPU_X86_PHENOM = 1
+	CPU_X86_CORE2DUO = 2
+	CPU_X86_KVM64 = 3
+	CPU_X86_QEMU32 = 4
+	CPU_X86_KVM32 = 5
+	CPU_X86_COREDUO = 6
+	CPU_X86_486 = 7
+	CPU_X86_PENTIUM = 8
+	CPU_X86_PENTIUM2 = 9
+	CPU_X86_PENTIUM3 = 10
+	CPU_X86_ATHLON = 11
+	CPU_X86_N270 = 12
+	CPU_X86_CONROE = 13
+	CPU_X86_PENRYN = 14
+	CPU_X86_NEHALEM = 15
+	CPU_X86_WESTMERE = 16
+	CPU_X86_SANDYBRIDGE = 17
+	CPU_X86_IVYBRIDGE = 18
+	CPU_X86_HASWELL = 19
+	CPU_X86_BROADWELL = 20
+	CPU_X86_SKYLAKE_CLIENT = 21
+	CPU_X86_SKYLAKE_SERVER = 22
+	CPU_X86_CASCADELAKE_SERVER = 23
+	CPU_X86_COOPERLAKE = 24
+	CPU_X86_ICELAKE_CLIENT = 25
+	CPU_X86_ICELAKE_SERVER = 26
+	CPU_X86_DENVERTON = 27
+	CPU_X86_SNOWRIDGE = 28
+	CPU_X86_KNIGHTSMILL = 29
+	CPU_X86_OPTERON_G1 = 30
+	CPU_X86_OPTERON_G2 = 31
+	CPU_X86_OPTERON_G3 = 32
+	CPU_X86_OPTERON_G4 = 33
+	CPU_X86_OPTERON_G5 = 34
+	CPU_X86_EPYC = 35
+	CPU_X86_DHYANA = 36
+	CPU_X86_EPYC_ROME = 37
+
 // X86 registers
 
 	X86_REG_INVALID = 0
diff --git a/bindings/java/unicorn/Arm64Const.java b/bindings/java/unicorn/Arm64Const.java
index dc70de85..93cb6975 100644
--- a/bindings/java/unicorn/Arm64Const.java
+++ b/bindings/java/unicorn/Arm64Const.java
@@ -4,6 +4,11 @@ package unicorn;
 
 public interface Arm64Const {
 
+   public static final int UC_CPU_AARCH64_A57 = 0;
+   public static final int UC_CPU_AARCH64_A53 = 1;
+   public static final int UC_CPU_AARCH64_A72 = 2;
+   public static final int UC_CPU_AARCH64_MAX = 3;
+
 // ARM64 registers
 
    public static final int UC_ARM64_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/ArmConst.java b/bindings/java/unicorn/ArmConst.java
index 4508430a..4f68cf51 100644
--- a/bindings/java/unicorn/ArmConst.java
+++ b/bindings/java/unicorn/ArmConst.java
@@ -4,6 +4,40 @@ package unicorn;
 
 public interface ArmConst {
 
+   public static final int UC_CPU_ARM_926 = 0;
+   public static final int UC_CPU_ARM_946 = 1;
+   public static final int UC_CPU_ARM_1026 = 2;
+   public static final int UC_CPU_ARM_1136_R2 = 3;
+   public static final int UC_CPU_ARM_1136 = 4;
+   public static final int UC_CPU_ARM_1176 = 5;
+   public static final int UC_CPU_ARM_11MPCORE = 6;
+   public static final int UC_CPU_ARM_CORTEX_M0 = 7;
+   public static final int UC_CPU_ARM_CORTEX_M3 = 8;
+   public static final int UC_CPU_ARM_CORTEX_M4 = 9;
+   public static final int UC_CPU_ARM_CORTEX_M7 = 10;
+   public static final int UC_CPU_ARM_CORTEX_M33 = 11;
+   public static final int UC_CPU_ARM_CORTEX_R5 = 12;
+   public static final int UC_CPU_ARM_CORTEX_R5F = 13;
+   public static final int UC_CPU_ARM_CORTEX_A8 = 14;
+   public static final int UC_CPU_ARM_CORTEX_A9 = 15;
+   public static final int UC_CPU_ARM_CORTEX_A7 = 16;
+   public static final int UC_CPU_ARM_CORTEX_A15 = 17;
+   public static final int UC_CPU_ARM_TI925T = 18;
+   public static final int UC_CPU_ARM_SA1100 = 19;
+   public static final int UC_CPU_ARM_SA1110 = 20;
+   public static final int UC_CPU_ARM_PXA250 = 21;
+   public static final int UC_CPU_ARM_PXA255 = 22;
+   public static final int UC_CPU_ARM_PXA260 = 23;
+   public static final int UC_CPU_ARM_PXA261 = 24;
+   public static final int UC_CPU_ARM_PXA262 = 25;
+   public static final int UC_CPU_ARM_PXA270A0 = 26;
+   public static final int UC_CPU_ARM_PXA270A1 = 27;
+   public static final int UC_CPU_ARM_PXA270B0 = 28;
+   public static final int UC_CPU_ARM_PXA270B1 = 29;
+   public static final int UC_CPU_ARM_PXA270C0 = 30;
+   public static final int UC_CPU_ARM_PXA270C5 = 31;
+   public static final int UC_CPU_ARM_MAX = 32;
+
 // ARM registers
 
    public static final int UC_ARM_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/M68kConst.java b/bindings/java/unicorn/M68kConst.java
index 4f0574d8..fa7d2d66 100644
--- a/bindings/java/unicorn/M68kConst.java
+++ b/bindings/java/unicorn/M68kConst.java
@@ -4,6 +4,16 @@ package unicorn;
 
 public interface M68kConst {
 
+   public static final int UC_CPU_M5206_CPU = 0;
+   public static final int UC_CPU_M68000_CPU = 1;
+   public static final int UC_CPU_M68020_CPU = 2;
+   public static final int UC_CPU_M68030_CPU = 3;
+   public static final int UC_CPU_M68040_CPU = 4;
+   public static final int UC_CPU_M68060_CPU = 5;
+   public static final int UC_CPU_M5208_CPU = 6;
+   public static final int UC_CPU_CFV4E_CPU = 7;
+   public static final int UC_CPU_ANY_CPU = 8;
+
 // M68K registers
 
    public static final int UC_M68K_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/MipsConst.java b/bindings/java/unicorn/MipsConst.java
index bace395c..43c53ac0 100644
--- a/bindings/java/unicorn/MipsConst.java
+++ b/bindings/java/unicorn/MipsConst.java
@@ -4,6 +4,36 @@ package unicorn;
 
 public interface MipsConst {
 
+   public static final int UC_CPU_MIPS_4KC = 0;
+   public static final int UC_CPU_MIPS_4KM = 1;
+   public static final int UC_CPU_MIPS_4KECR1 = 2;
+   public static final int UC_CPU_MIPS_4KEMR1 = 3;
+   public static final int UC_CPU_MIPS_4KEC = 4;
+   public static final int UC_CPU_MIPS_4KEM = 5;
+   public static final int UC_CPU_MIPS_24KC = 6;
+   public static final int UC_CPU_MIPS_24KEC = 7;
+   public static final int UC_CPU_MIPS_24KF = 8;
+   public static final int UC_CPU_MIPS_34KF = 9;
+   public static final int UC_CPU_MIPS_74KF = 10;
+   public static final int UC_CPU_MIPS_M14K = 11;
+   public static final int UC_CPU_MIPS_M14KC = 12;
+   public static final int UC_CPU_MIPS_P5600 = 13;
+   public static final int UC_CPU_MIPS_MIPS32R6_GENERIC = 14;
+   public static final int UC_CPU_MIPS_I7200 = 15;
+   public static final int UC_CPU_MIPS_R4000 = 16;
+   public static final int UC_CPU_MIPS_VR5432 = 17;
+   public static final int UC_CPU_MIPS_5KC = 18;
+   public static final int UC_CPU_MIPS_5KF = 19;
+   public static final int UC_CPU_MIPS_20KC = 20;
+   public static final int UC_CPU_MIPS_MIPS64R2_GENERIC = 21;
+   public static final int UC_CPU_MIPS_5KEC = 22;
+   public static final int UC_CPU_MIPS_5KEF = 23;
+   public static final int UC_CPU_MIPS_I6400 = 24;
+   public static final int UC_CPU_MIPS_I6500 = 25;
+   public static final int UC_CPU_MIPS_LOONGSON_2E = 26;
+   public static final int UC_CPU_MIPS_LOONGSON_2F = 27;
+   public static final int UC_CPU_MIPS_MIPS64DSPR2 = 28;
+
 // MIPS registers
 
    public static final int UC_MIPS_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/PpcConst.java b/bindings/java/unicorn/PpcConst.java
index 86597be6..09cada99 100644
--- a/bindings/java/unicorn/PpcConst.java
+++ b/bindings/java/unicorn/PpcConst.java
@@ -4,6 +4,307 @@ package unicorn;
 
 public interface PpcConst {
 
+   public static final int UC_CPU_PPC_401A1 = 0;
+   public static final int UC_CPU_PPC_401B2 = 1;
+   public static final int UC_CPU_PPC_401C2 = 2;
+   public static final int UC_CPU_PPC_401D2 = 3;
+   public static final int UC_CPU_PPC_401E2 = 4;
+   public static final int UC_CPU_PPC_401F2 = 5;
+   public static final int UC_CPU_PPC_401G2 = 6;
+   public static final int UC_CPU_PPC_COBRA = 7;
+   public static final int UC_CPU_PPC_403GA = 8;
+   public static final int UC_CPU_PPC_403GB = 9;
+   public static final int UC_CPU_PPC_403GC = 10;
+   public static final int UC_CPU_PPC_403GCX = 11;
+   public static final int UC_CPU_PPC_405D2 = 12;
+   public static final int UC_CPU_PPC_405D4 = 13;
+   public static final int UC_CPU_PPC_405CRA = 14;
+   public static final int UC_CPU_PPC_405CRB = 15;
+   public static final int UC_CPU_PPC_405CRC = 16;
+   public static final int UC_CPU_PPC_405EP = 17;
+   public static final int UC_CPU_PPC_405EZ = 18;
+   public static final int UC_CPU_PPC_405GPA = 19;
+   public static final int UC_CPU_PPC_405GPB = 20;
+   public static final int UC_CPU_PPC_405GPC = 21;
+   public static final int UC_CPU_PPC_405GPD = 22;
+   public static final int UC_CPU_PPC_405GPR = 23;
+   public static final int UC_CPU_PPC_405LP = 24;
+   public static final int UC_CPU_PPC_NPE405H = 25;
+   public static final int UC_CPU_PPC_NPE405H2 = 26;
+   public static final int UC_CPU_PPC_NPE405L = 27;
+   public static final int UC_CPU_PPC_NPE4GS3 = 28;
+   public static final int UC_CPU_PPC_STB03 = 29;
+   public static final int UC_CPU_PPC_STB04 = 30;
+   public static final int UC_CPU_PPC_STB25 = 31;
+   public static final int UC_CPU_PPC_X2VP4 = 32;
+   public static final int UC_CPU_PPC_440_XILINX = 33;
+   public static final int UC_CPU_PPC_440EPA = 34;
+   public static final int UC_CPU_PPC_440EPB = 35;
+   public static final int UC_CPU_PPC_440GPB = 36;
+   public static final int UC_CPU_PPC_440GPC = 37;
+   public static final int UC_CPU_PPC_440GRX = 38;
+   public static final int UC_CPU_PPC_440GXA = 39;
+   public static final int UC_CPU_PPC_440GXB = 40;
+   public static final int UC_CPU_PPC_440GXC = 41;
+   public static final int UC_CPU_PPC_440GXF = 42;
+   public static final int UC_CPU_PPC_440SP = 43;
+   public static final int UC_CPU_PPC_440SP2 = 44;
+   public static final int UC_CPU_PPC_440SPE = 45;
+   public static final int UC_CPU_PPC_460EXB = 46;
+   public static final int UC_CPU_PPC_MPC5XX = 47;
+   public static final int UC_CPU_PPC_MPC8XX = 48;
+   public static final int UC_CPU_PPC_G2 = 49;
+   public static final int UC_CPU_PPC_G2H4 = 50;
+   public static final int UC_CPU_PPC_G2GP = 51;
+   public static final int UC_CPU_PPC_G2LS = 52;
+   public static final int UC_CPU_PPC_MPC603 = 53;
+   public static final int UC_CPU_PPC_G2_HIP3 = 54;
+   public static final int UC_CPU_PPC_G2_HIP4 = 55;
+   public static final int UC_CPU_PPC_G2LE = 56;
+   public static final int UC_CPU_PPC_G2LEGP = 57;
+   public static final int UC_CPU_PPC_G2LELS = 58;
+   public static final int UC_CPU_PPC_G2LEGP1 = 59;
+   public static final int UC_CPU_PPC_G2LEGP3 = 60;
+   public static final int UC_CPU_PPC_E200Z5 = 61;
+   public static final int UC_CPU_PPC_E200Z6 = 62;
+   public static final int UC_CPU_PPC_E300C1 = 63;
+   public static final int UC_CPU_PPC_E300C2 = 64;
+   public static final int UC_CPU_PPC_E300C3 = 65;
+   public static final int UC_CPU_PPC_E300C4 = 66;
+   public static final int UC_CPU_PPC_E500V1_V10 = 67;
+   public static final int UC_CPU_PPC_E500V1_V20 = 68;
+   public static final int UC_CPU_PPC_E500V2_V10 = 69;
+   public static final int UC_CPU_PPC_E500V2_V11 = 70;
+   public static final int UC_CPU_PPC_E500V2_V20 = 71;
+   public static final int UC_CPU_PPC_E500V2_V21 = 72;
+   public static final int UC_CPU_PPC_E500V2_V22 = 73;
+   public static final int UC_CPU_PPC_E500V2_V30 = 74;
+   public static final int UC_CPU_PPC_E500MC = 75;
+   public static final int UC_CPU_PPC_E5500 = 76;
+   public static final int UC_CPU_PPC_E6500 = 77;
+   public static final int UC_CPU_PPC_E600 = 78;
+   public static final int UC_CPU_PPC_601_V0 = 79;
+   public static final int UC_CPU_PPC_601_V1 = 80;
+   public static final int UC_CPU_PPC_601_V2 = 81;
+   public static final int UC_CPU_PPC_602 = 82;
+   public static final int UC_CPU_PPC_603 = 83;
+   public static final int UC_CPU_PPC_603E_V11 = 84;
+   public static final int UC_CPU_PPC_603E_V12 = 85;
+   public static final int UC_CPU_PPC_603E_V13 = 86;
+   public static final int UC_CPU_PPC_603E_V14 = 87;
+   public static final int UC_CPU_PPC_603E_V22 = 88;
+   public static final int UC_CPU_PPC_603E_V3 = 89;
+   public static final int UC_CPU_PPC_603E_V4 = 90;
+   public static final int UC_CPU_PPC_603E_V41 = 91;
+   public static final int UC_CPU_PPC_603E7T = 92;
+   public static final int UC_CPU_PPC_603E7V = 93;
+   public static final int UC_CPU_PPC_603E7V1 = 94;
+   public static final int UC_CPU_PPC_603E7V2 = 95;
+   public static final int UC_CPU_PPC_603E7 = 96;
+   public static final int UC_CPU_PPC_603P = 97;
+   public static final int UC_CPU_PPC_604 = 98;
+   public static final int UC_CPU_PPC_604E_V10 = 99;
+   public static final int UC_CPU_PPC_604E_V22 = 100;
+   public static final int UC_CPU_PPC_604E_V24 = 101;
+   public static final int UC_CPU_PPC_604R = 102;
+   public static final int UC_CPU_PPC_7X0_V10 = 103;
+   public static final int UC_CPU_PPC_7X0_V20 = 104;
+   public static final int UC_CPU_PPC_7X0_V21 = 105;
+   public static final int UC_CPU_PPC_7X0_V22 = 106;
+   public static final int UC_CPU_PPC_7X0_V30 = 107;
+   public static final int UC_CPU_PPC_7X0_V31 = 108;
+   public static final int UC_CPU_PPC_740E = 109;
+   public static final int UC_CPU_PPC_750E = 110;
+   public static final int UC_CPU_PPC_7X0P = 111;
+   public static final int UC_CPU_PPC_750CL_V10 = 112;
+   public static final int UC_CPU_PPC_750CL_V20 = 113;
+   public static final int UC_CPU_PPC_750CX_V10 = 114;
+   public static final int UC_CPU_PPC_750CX_V20 = 115;
+   public static final int UC_CPU_PPC_750CX_V21 = 116;
+   public static final int UC_CPU_PPC_750CX_V22 = 117;
+   public static final int UC_CPU_PPC_750CXE_V21 = 118;
+   public static final int UC_CPU_PPC_750CXE_V22 = 119;
+   public static final int UC_CPU_PPC_750CXE_V23 = 120;
+   public static final int UC_CPU_PPC_750CXE_V24 = 121;
+   public static final int UC_CPU_PPC_750CXE_V24B = 122;
+   public static final int UC_CPU_PPC_750CXE_V30 = 123;
+   public static final int UC_CPU_PPC_750CXE_V31 = 124;
+   public static final int UC_CPU_PPC_750CXE_V31B = 125;
+   public static final int UC_CPU_PPC_750CXR = 126;
+   public static final int UC_CPU_PPC_750FL = 127;
+   public static final int UC_CPU_PPC_750FX_V10 = 128;
+   public static final int UC_CPU_PPC_750FX_V20 = 129;
+   public static final int UC_CPU_PPC_750FX_V21 = 130;
+   public static final int UC_CPU_PPC_750FX_V22 = 131;
+   public static final int UC_CPU_PPC_750FX_V23 = 132;
+   public static final int UC_CPU_PPC_750GL = 133;
+   public static final int UC_CPU_PPC_750GX_V10 = 134;
+   public static final int UC_CPU_PPC_750GX_V11 = 135;
+   public static final int UC_CPU_PPC_750GX_V12 = 136;
+   public static final int UC_CPU_PPC_750L_V20 = 137;
+   public static final int UC_CPU_PPC_750L_V21 = 138;
+   public static final int UC_CPU_PPC_750L_V22 = 139;
+   public static final int UC_CPU_PPC_750L_V30 = 140;
+   public static final int UC_CPU_PPC_750L_V32 = 141;
+   public static final int UC_CPU_PPC_7X5_V10 = 142;
+   public static final int UC_CPU_PPC_7X5_V11 = 143;
+   public static final int UC_CPU_PPC_7X5_V20 = 144;
+   public static final int UC_CPU_PPC_7X5_V21 = 145;
+   public static final int UC_CPU_PPC_7X5_V22 = 146;
+   public static final int UC_CPU_PPC_7X5_V23 = 147;
+   public static final int UC_CPU_PPC_7X5_V24 = 148;
+   public static final int UC_CPU_PPC_7X5_V25 = 149;
+   public static final int UC_CPU_PPC_7X5_V26 = 150;
+   public static final int UC_CPU_PPC_7X5_V27 = 151;
+   public static final int UC_CPU_PPC_7X5_V28 = 152;
+   public static final int UC_CPU_PPC_7400_V10 = 153;
+   public static final int UC_CPU_PPC_7400_V11 = 154;
+   public static final int UC_CPU_PPC_7400_V20 = 155;
+   public static final int UC_CPU_PPC_7400_V21 = 156;
+   public static final int UC_CPU_PPC_7400_V22 = 157;
+   public static final int UC_CPU_PPC_7400_V26 = 158;
+   public static final int UC_CPU_PPC_7400_V27 = 159;
+   public static final int UC_CPU_PPC_7400_V28 = 160;
+   public static final int UC_CPU_PPC_7400_V29 = 161;
+   public static final int UC_CPU_PPC_7410_V10 = 162;
+   public static final int UC_CPU_PPC_7410_V11 = 163;
+   public static final int UC_CPU_PPC_7410_V12 = 164;
+   public static final int UC_CPU_PPC_7410_V13 = 165;
+   public static final int UC_CPU_PPC_7410_V14 = 166;
+   public static final int UC_CPU_PPC_7448_V10 = 167;
+   public static final int UC_CPU_PPC_7448_V11 = 168;
+   public static final int UC_CPU_PPC_7448_V20 = 169;
+   public static final int UC_CPU_PPC_7448_V21 = 170;
+   public static final int UC_CPU_PPC_7450_V10 = 171;
+   public static final int UC_CPU_PPC_7450_V11 = 172;
+   public static final int UC_CPU_PPC_7450_V12 = 173;
+   public static final int UC_CPU_PPC_7450_V20 = 174;
+   public static final int UC_CPU_PPC_7450_V21 = 175;
+   public static final int UC_CPU_PPC_74X1_V23 = 176;
+   public static final int UC_CPU_PPC_74X1_V210 = 177;
+   public static final int UC_CPU_PPC_74X5_V10 = 178;
+   public static final int UC_CPU_PPC_74X5_V21 = 179;
+   public static final int UC_CPU_PPC_74X5_V32 = 180;
+   public static final int UC_CPU_PPC_74X5_V33 = 181;
+   public static final int UC_CPU_PPC_74X5_V34 = 182;
+   public static final int UC_CPU_PPC_74X7_V10 = 183;
+   public static final int UC_CPU_PPC_74X7_V11 = 184;
+   public static final int UC_CPU_PPC_74X7_V12 = 185;
+   public static final int UC_CPU_PPC_74X7A_V10 = 186;
+   public static final int UC_CPU_PPC_74X7A_V11 = 187;
+   public static final int UC_CPU_PPC_74X7A_V12 = 188;
+   public static final int UC_CPU_PPC_IOP480 = 1;
+   public static final int UC_CPU_PPC_X2VP20 = 42;
+   public static final int UC_CPU_PPC_440GRA = 35;
+   public static final int UC_CPU_PPC_440EPX = 38;
+   public static final int UC_CPU_PPC_MPC5200_V10 = 59;
+   public static final int UC_CPU_PPC_MPC5200_V11 = 59;
+   public static final int UC_CPU_PPC_MPC5200_V12 = 59;
+   public static final int UC_CPU_PPC_MPC5200B_V20 = 59;
+   public static final int UC_CPU_PPC_MPC5200B_V21 = 59;
+   public static final int UC_CPU_PPC_MPC834X = 63;
+   public static final int UC_CPU_PPC_MPC837X = 66;
+   public static final int UC_CPU_PPC_E500 = 73;
+   public static final int UC_CPU_PPC_MPC8533_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8533_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8533E_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8533E_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8540_V10 = 67;
+   public static final int UC_CPU_PPC_MPC8540_V20 = 68;
+   public static final int UC_CPU_PPC_MPC8540_V21 = 68;
+   public static final int UC_CPU_PPC_MPC8541_V10 = 68;
+   public static final int UC_CPU_PPC_MPC8541_V11 = 68;
+   public static final int UC_CPU_PPC_MPC8541E_V10 = 68;
+   public static final int UC_CPU_PPC_MPC8541E_V11 = 68;
+   public static final int UC_CPU_PPC_MPC8543_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8543_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8543_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8543_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8543E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8543E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8543E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8543E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8544_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8544_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8544E_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8544E_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8545_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8545_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8545_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8545E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8545E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8545E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8547E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8547E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8547E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8548_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8548_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8548_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8548_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8548E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8548E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8548E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8548E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8555_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8555_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8555E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8555E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8560_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8560_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8560_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8567 = 73;
+   public static final int UC_CPU_PPC_MPC8567E = 73;
+   public static final int UC_CPU_PPC_MPC8568 = 73;
+   public static final int UC_CPU_PPC_MPC8568E = 73;
+   public static final int UC_CPU_PPC_MPC8572 = 74;
+   public static final int UC_CPU_PPC_MPC8572E = 74;
+   public static final int UC_CPU_PPC_MPC8610 = 78;
+   public static final int UC_CPU_PPC_MPC8641 = 78;
+   public static final int UC_CPU_PPC_MPC8641D = 78;
+
+   public static final int UC_CPU_PPC64_620 = 0;
+   public static final int UC_CPU_PPC64_630 = 1;
+   public static final int UC_CPU_PPC64_631 = 2;
+   public static final int UC_CPU_PPC64_POWER4 = 3;
+   public static final int UC_CPU_PPC64_POWER4P = 4;
+   public static final int UC_CPU_PPC64_POWER5 = 5;
+   public static final int UC_CPU_PPC64_POWER5P_V21 = 6;
+   public static final int UC_CPU_PPC64_POWER6 = 7;
+   public static final int UC_CPU_PPC64_POWER_SERVER_MASK = 8;
+   public static final int UC_CPU_PPC64_POWER7_BASE = 9;
+   public static final int UC_CPU_PPC64_POWER7_V23 = 10;
+   public static final int UC_CPU_PPC64_POWER7P_BASE = 11;
+   public static final int UC_CPU_PPC64_POWER7P_V21 = 12;
+   public static final int UC_CPU_PPC64_POWER8E_BASE = 13;
+   public static final int UC_CPU_PPC64_POWER8E_V21 = 14;
+   public static final int UC_CPU_PPC64_POWER8_BASE = 15;
+   public static final int UC_CPU_PPC64_POWER8_V20 = 16;
+   public static final int UC_CPU_PPC64_POWER8NVL_BASE = 17;
+   public static final int UC_CPU_PPC64_POWER8NVL_V10 = 18;
+   public static final int UC_CPU_PPC64_POWER9_BASE = 19;
+   public static final int UC_CPU_PPC64_POWER9_DD1 = 20;
+   public static final int UC_CPU_PPC64_POWER9_DD20 = 21;
+   public static final int UC_CPU_PPC64_POWER10_BASE = 22;
+   public static final int UC_CPU_PPC64_POWER10_DD1 = 23;
+   public static final int UC_CPU_PPC64_970_V22 = 24;
+   public static final int UC_CPU_PPC64_970FX_V10 = 25;
+   public static final int UC_CPU_PPC64_970FX_V20 = 26;
+   public static final int UC_CPU_PPC64_970FX_V21 = 27;
+   public static final int UC_CPU_PPC64_970FX_V30 = 28;
+   public static final int UC_CPU_PPC64_970FX_V31 = 29;
+   public static final int UC_CPU_PPC64_970MP_V10 = 30;
+   public static final int UC_CPU_PPC64_970MP_V11 = 31;
+   public static final int UC_CPU_PPC64_CELL_V10 = 32;
+   public static final int UC_CPU_PPC64_CELL_V20 = 33;
+   public static final int UC_CPU_PPC64_CELL_V30 = 34;
+   public static final int UC_CPU_PPC64_CELL_V31 = 35;
+   public static final int UC_CPU_PPC64_RS64 = 36;
+   public static final int UC_CPU_PPC64_RS64II = 37;
+   public static final int UC_CPU_PPC64_RS64III = 38;
+   public static final int UC_CPU_PPC64_RS64IV = 39;
+   public static final int UC_CPU_PPC64_CELL_V32 = 35;
+   public static final int UC_CPU_PPC64_CELL = 35;
+
 // PPC registers
 
    public static final int UC_PPC_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/RiscvConst.java b/bindings/java/unicorn/RiscvConst.java
index ca375f1a..d835296c 100644
--- a/bindings/java/unicorn/RiscvConst.java
+++ b/bindings/java/unicorn/RiscvConst.java
@@ -4,6 +4,16 @@ package unicorn;
 
 public interface RiscvConst {
 
+   public static final int UC_CPU_RISCV32_ANY = 0;
+   public static final int UC_CPU_RISCV32_BASE32 = 1;
+   public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
+   public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
+
+   public static final int UC_CPU_RISCV64_ANY = 0;
+   public static final int UC_CPU_RISCV64_BASE64 = 1;
+   public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
+   public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
+
 // RISCV registers
 
    public static final int UC_RISCV_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/SparcConst.java b/bindings/java/unicorn/SparcConst.java
index de0dc184..27b3b618 100644
--- a/bindings/java/unicorn/SparcConst.java
+++ b/bindings/java/unicorn/SparcConst.java
@@ -4,6 +4,38 @@ package unicorn;
 
 public interface SparcConst {
 
+   public static final int UC_CPU_SPARC_FUJITSU_MB86904 = 0;
+   public static final int UC_CPU_SPARC_FUJITSU_MB86907 = 1;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_I = 2;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_II = 3;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_40 = 5;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_50 = 6;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_51 = 7;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_60 = 8;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_61 = 9;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_II = 10;
+   public static final int UC_CPU_SPARC_LEON2 = 11;
+   public static final int UC_CPU_SPARC_LEON3 = 12;
+
+   public static final int UC_CPU_SPARC64_FUJITSU = 0;
+   public static final int UC_CPU_SPARC64_FUJITSU_III = 1;
+   public static final int UC_CPU_SPARC64_FUJITSU_IV = 2;
+   public static final int UC_CPU_SPARC64_FUJITSU_V = 3;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_I = 4;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_II = 5;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_III = 6;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15;
+   public static final int UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16;
+
 // SPARC registers
 
    public static final int UC_SPARC_REG_INVALID = 0;
diff --git a/bindings/java/unicorn/UnicornConst.java b/bindings/java/unicorn/UnicornConst.java
index f4396003..0c519d65 100644
--- a/bindings/java/unicorn/UnicornConst.java
+++ b/bindings/java/unicorn/UnicornConst.java
@@ -109,6 +109,22 @@ public interface UnicornConst {
    public static final int UC_QUERY_ARCH = 3;
    public static final int UC_QUERY_TIMEOUT = 4;
 
+   public static final int UC_CTL_IO_NONE = 0;
+   public static final int UC_CTL_IO_WRITE = 1;
+   public static final int UC_CTL_IO_READ = 2;
+   public static final int UC_CTL_IO_READ_WRITE = 3;
+
+   public static final int UC_CTL_UC_MODE = 0;
+   public static final int UC_CTL_UC_PAGE_SIZE = 1;
+   public static final int UC_CTL_UC_ARCH = 2;
+   public static final int UC_CTL_UC_TIMEOUT = 3;
+   public static final int UC_CTL_UC_EXITS_CNT = 4;
+   public static final int UC_CTL_UC_EXITS = 5;
+   public static final int UC_CTL_CPU_MODEL = 6;
+   public static final int UC_CTL_TB_EDGE = 7;
+   public static final int UC_CTL_TB_REQUEST_CACHE = 8;
+   public static final int UC_CTL_TB_REMOVE_CACHE = 9;
+
    public static final int UC_PROT_NONE = 0;
    public static final int UC_PROT_READ = 1;
    public static final int UC_PROT_WRITE = 2;
diff --git a/bindings/java/unicorn/X86Const.java b/bindings/java/unicorn/X86Const.java
index a097b525..a12e55bc 100644
--- a/bindings/java/unicorn/X86Const.java
+++ b/bindings/java/unicorn/X86Const.java
@@ -4,6 +4,45 @@ package unicorn;
 
 public interface X86Const {
 
+   public static final int UC_CPU_X86_QEMU64 = 0;
+   public static final int UC_CPU_X86_PHENOM = 1;
+   public static final int UC_CPU_X86_CORE2DUO = 2;
+   public static final int UC_CPU_X86_KVM64 = 3;
+   public static final int UC_CPU_X86_QEMU32 = 4;
+   public static final int UC_CPU_X86_KVM32 = 5;
+   public static final int UC_CPU_X86_COREDUO = 6;
+   public static final int UC_CPU_X86_486 = 7;
+   public static final int UC_CPU_X86_PENTIUM = 8;
+   public static final int UC_CPU_X86_PENTIUM2 = 9;
+   public static final int UC_CPU_X86_PENTIUM3 = 10;
+   public static final int UC_CPU_X86_ATHLON = 11;
+   public static final int UC_CPU_X86_N270 = 12;
+   public static final int UC_CPU_X86_CONROE = 13;
+   public static final int UC_CPU_X86_PENRYN = 14;
+   public static final int UC_CPU_X86_NEHALEM = 15;
+   public static final int UC_CPU_X86_WESTMERE = 16;
+   public static final int UC_CPU_X86_SANDYBRIDGE = 17;
+   public static final int UC_CPU_X86_IVYBRIDGE = 18;
+   public static final int UC_CPU_X86_HASWELL = 19;
+   public static final int UC_CPU_X86_BROADWELL = 20;
+   public static final int UC_CPU_X86_SKYLAKE_CLIENT = 21;
+   public static final int UC_CPU_X86_SKYLAKE_SERVER = 22;
+   public static final int UC_CPU_X86_CASCADELAKE_SERVER = 23;
+   public static final int UC_CPU_X86_COOPERLAKE = 24;
+   public static final int UC_CPU_X86_ICELAKE_CLIENT = 25;
+   public static final int UC_CPU_X86_ICELAKE_SERVER = 26;
+   public static final int UC_CPU_X86_DENVERTON = 27;
+   public static final int UC_CPU_X86_SNOWRIDGE = 28;
+   public static final int UC_CPU_X86_KNIGHTSMILL = 29;
+   public static final int UC_CPU_X86_OPTERON_G1 = 30;
+   public static final int UC_CPU_X86_OPTERON_G2 = 31;
+   public static final int UC_CPU_X86_OPTERON_G3 = 32;
+   public static final int UC_CPU_X86_OPTERON_G4 = 33;
+   public static final int UC_CPU_X86_OPTERON_G5 = 34;
+   public static final int UC_CPU_X86_EPYC = 35;
+   public static final int UC_CPU_X86_DHYANA = 36;
+   public static final int UC_CPU_X86_EPYC_ROME = 37;
+
 // X86 registers
 
    public static final int UC_X86_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/Arm64Const.pas b/bindings/pascal/unicorn/Arm64Const.pas
index d348039a..416ec2f7 100644
--- a/bindings/pascal/unicorn/Arm64Const.pas
+++ b/bindings/pascal/unicorn/Arm64Const.pas
@@ -5,6 +5,11 @@ unit Arm64Const;
 interface
 
 const
+  UC_CPU_AARCH64_A57 = 0;
+  UC_CPU_AARCH64_A53 = 1;
+  UC_CPU_AARCH64_A72 = 2;
+  UC_CPU_AARCH64_MAX = 3;
+
 // ARM64 registers
 
   UC_ARM64_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/ArmConst.pas b/bindings/pascal/unicorn/ArmConst.pas
index b70b8326..1a85d9f3 100644
--- a/bindings/pascal/unicorn/ArmConst.pas
+++ b/bindings/pascal/unicorn/ArmConst.pas
@@ -5,6 +5,40 @@ unit ArmConst;
 interface
 
 const
+  UC_CPU_ARM_926 = 0;
+  UC_CPU_ARM_946 = 1;
+  UC_CPU_ARM_1026 = 2;
+  UC_CPU_ARM_1136_R2 = 3;
+  UC_CPU_ARM_1136 = 4;
+  UC_CPU_ARM_1176 = 5;
+  UC_CPU_ARM_11MPCORE = 6;
+  UC_CPU_ARM_CORTEX_M0 = 7;
+  UC_CPU_ARM_CORTEX_M3 = 8;
+  UC_CPU_ARM_CORTEX_M4 = 9;
+  UC_CPU_ARM_CORTEX_M7 = 10;
+  UC_CPU_ARM_CORTEX_M33 = 11;
+  UC_CPU_ARM_CORTEX_R5 = 12;
+  UC_CPU_ARM_CORTEX_R5F = 13;
+  UC_CPU_ARM_CORTEX_A8 = 14;
+  UC_CPU_ARM_CORTEX_A9 = 15;
+  UC_CPU_ARM_CORTEX_A7 = 16;
+  UC_CPU_ARM_CORTEX_A15 = 17;
+  UC_CPU_ARM_TI925T = 18;
+  UC_CPU_ARM_SA1100 = 19;
+  UC_CPU_ARM_SA1110 = 20;
+  UC_CPU_ARM_PXA250 = 21;
+  UC_CPU_ARM_PXA255 = 22;
+  UC_CPU_ARM_PXA260 = 23;
+  UC_CPU_ARM_PXA261 = 24;
+  UC_CPU_ARM_PXA262 = 25;
+  UC_CPU_ARM_PXA270A0 = 26;
+  UC_CPU_ARM_PXA270A1 = 27;
+  UC_CPU_ARM_PXA270B0 = 28;
+  UC_CPU_ARM_PXA270B1 = 29;
+  UC_CPU_ARM_PXA270C0 = 30;
+  UC_CPU_ARM_PXA270C5 = 31;
+  UC_CPU_ARM_MAX = 32;
+
 // ARM registers
 
   UC_ARM_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/M68kConst.pas b/bindings/pascal/unicorn/M68kConst.pas
index be78f78a..0db7ee82 100644
--- a/bindings/pascal/unicorn/M68kConst.pas
+++ b/bindings/pascal/unicorn/M68kConst.pas
@@ -5,6 +5,16 @@ unit M68kConst;
 interface
 
 const
+  UC_CPU_M5206_CPU = 0;
+  UC_CPU_M68000_CPU = 1;
+  UC_CPU_M68020_CPU = 2;
+  UC_CPU_M68030_CPU = 3;
+  UC_CPU_M68040_CPU = 4;
+  UC_CPU_M68060_CPU = 5;
+  UC_CPU_M5208_CPU = 6;
+  UC_CPU_CFV4E_CPU = 7;
+  UC_CPU_ANY_CPU = 8;
+
 // M68K registers
 
   UC_M68K_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/MipsConst.pas b/bindings/pascal/unicorn/MipsConst.pas
index 90f22248..3b1df5f0 100644
--- a/bindings/pascal/unicorn/MipsConst.pas
+++ b/bindings/pascal/unicorn/MipsConst.pas
@@ -5,6 +5,36 @@ unit MipsConst;
 interface
 
 const
+  UC_CPU_MIPS_4KC = 0;
+  UC_CPU_MIPS_4KM = 1;
+  UC_CPU_MIPS_4KECR1 = 2;
+  UC_CPU_MIPS_4KEMR1 = 3;
+  UC_CPU_MIPS_4KEC = 4;
+  UC_CPU_MIPS_4KEM = 5;
+  UC_CPU_MIPS_24KC = 6;
+  UC_CPU_MIPS_24KEC = 7;
+  UC_CPU_MIPS_24KF = 8;
+  UC_CPU_MIPS_34KF = 9;
+  UC_CPU_MIPS_74KF = 10;
+  UC_CPU_MIPS_M14K = 11;
+  UC_CPU_MIPS_M14KC = 12;
+  UC_CPU_MIPS_P5600 = 13;
+  UC_CPU_MIPS_MIPS32R6_GENERIC = 14;
+  UC_CPU_MIPS_I7200 = 15;
+  UC_CPU_MIPS_R4000 = 16;
+  UC_CPU_MIPS_VR5432 = 17;
+  UC_CPU_MIPS_5KC = 18;
+  UC_CPU_MIPS_5KF = 19;
+  UC_CPU_MIPS_20KC = 20;
+  UC_CPU_MIPS_MIPS64R2_GENERIC = 21;
+  UC_CPU_MIPS_5KEC = 22;
+  UC_CPU_MIPS_5KEF = 23;
+  UC_CPU_MIPS_I6400 = 24;
+  UC_CPU_MIPS_I6500 = 25;
+  UC_CPU_MIPS_LOONGSON_2E = 26;
+  UC_CPU_MIPS_LOONGSON_2F = 27;
+  UC_CPU_MIPS_MIPS64DSPR2 = 28;
+
 // MIPS registers
 
   UC_MIPS_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/PpcConst.pas b/bindings/pascal/unicorn/PpcConst.pas
index 2c6633db..9158c4e3 100644
--- a/bindings/pascal/unicorn/PpcConst.pas
+++ b/bindings/pascal/unicorn/PpcConst.pas
@@ -5,6 +5,307 @@ unit PpcConst;
 interface
 
 const
+  UC_CPU_PPC_401A1 = 0;
+  UC_CPU_PPC_401B2 = 1;
+  UC_CPU_PPC_401C2 = 2;
+  UC_CPU_PPC_401D2 = 3;
+  UC_CPU_PPC_401E2 = 4;
+  UC_CPU_PPC_401F2 = 5;
+  UC_CPU_PPC_401G2 = 6;
+  UC_CPU_PPC_COBRA = 7;
+  UC_CPU_PPC_403GA = 8;
+  UC_CPU_PPC_403GB = 9;
+  UC_CPU_PPC_403GC = 10;
+  UC_CPU_PPC_403GCX = 11;
+  UC_CPU_PPC_405D2 = 12;
+  UC_CPU_PPC_405D4 = 13;
+  UC_CPU_PPC_405CRA = 14;
+  UC_CPU_PPC_405CRB = 15;
+  UC_CPU_PPC_405CRC = 16;
+  UC_CPU_PPC_405EP = 17;
+  UC_CPU_PPC_405EZ = 18;
+  UC_CPU_PPC_405GPA = 19;
+  UC_CPU_PPC_405GPB = 20;
+  UC_CPU_PPC_405GPC = 21;
+  UC_CPU_PPC_405GPD = 22;
+  UC_CPU_PPC_405GPR = 23;
+  UC_CPU_PPC_405LP = 24;
+  UC_CPU_PPC_NPE405H = 25;
+  UC_CPU_PPC_NPE405H2 = 26;
+  UC_CPU_PPC_NPE405L = 27;
+  UC_CPU_PPC_NPE4GS3 = 28;
+  UC_CPU_PPC_STB03 = 29;
+  UC_CPU_PPC_STB04 = 30;
+  UC_CPU_PPC_STB25 = 31;
+  UC_CPU_PPC_X2VP4 = 32;
+  UC_CPU_PPC_440_XILINX = 33;
+  UC_CPU_PPC_440EPA = 34;
+  UC_CPU_PPC_440EPB = 35;
+  UC_CPU_PPC_440GPB = 36;
+  UC_CPU_PPC_440GPC = 37;
+  UC_CPU_PPC_440GRX = 38;
+  UC_CPU_PPC_440GXA = 39;
+  UC_CPU_PPC_440GXB = 40;
+  UC_CPU_PPC_440GXC = 41;
+  UC_CPU_PPC_440GXF = 42;
+  UC_CPU_PPC_440SP = 43;
+  UC_CPU_PPC_440SP2 = 44;
+  UC_CPU_PPC_440SPE = 45;
+  UC_CPU_PPC_460EXB = 46;
+  UC_CPU_PPC_MPC5XX = 47;
+  UC_CPU_PPC_MPC8XX = 48;
+  UC_CPU_PPC_G2 = 49;
+  UC_CPU_PPC_G2H4 = 50;
+  UC_CPU_PPC_G2GP = 51;
+  UC_CPU_PPC_G2LS = 52;
+  UC_CPU_PPC_MPC603 = 53;
+  UC_CPU_PPC_G2_HIP3 = 54;
+  UC_CPU_PPC_G2_HIP4 = 55;
+  UC_CPU_PPC_G2LE = 56;
+  UC_CPU_PPC_G2LEGP = 57;
+  UC_CPU_PPC_G2LELS = 58;
+  UC_CPU_PPC_G2LEGP1 = 59;
+  UC_CPU_PPC_G2LEGP3 = 60;
+  UC_CPU_PPC_E200Z5 = 61;
+  UC_CPU_PPC_E200Z6 = 62;
+  UC_CPU_PPC_E300C1 = 63;
+  UC_CPU_PPC_E300C2 = 64;
+  UC_CPU_PPC_E300C3 = 65;
+  UC_CPU_PPC_E300C4 = 66;
+  UC_CPU_PPC_E500V1_V10 = 67;
+  UC_CPU_PPC_E500V1_V20 = 68;
+  UC_CPU_PPC_E500V2_V10 = 69;
+  UC_CPU_PPC_E500V2_V11 = 70;
+  UC_CPU_PPC_E500V2_V20 = 71;
+  UC_CPU_PPC_E500V2_V21 = 72;
+  UC_CPU_PPC_E500V2_V22 = 73;
+  UC_CPU_PPC_E500V2_V30 = 74;
+  UC_CPU_PPC_E500MC = 75;
+  UC_CPU_PPC_E5500 = 76;
+  UC_CPU_PPC_E6500 = 77;
+  UC_CPU_PPC_E600 = 78;
+  UC_CPU_PPC_601_V0 = 79;
+  UC_CPU_PPC_601_V1 = 80;
+  UC_CPU_PPC_601_V2 = 81;
+  UC_CPU_PPC_602 = 82;
+  UC_CPU_PPC_603 = 83;
+  UC_CPU_PPC_603E_V11 = 84;
+  UC_CPU_PPC_603E_V12 = 85;
+  UC_CPU_PPC_603E_V13 = 86;
+  UC_CPU_PPC_603E_V14 = 87;
+  UC_CPU_PPC_603E_V22 = 88;
+  UC_CPU_PPC_603E_V3 = 89;
+  UC_CPU_PPC_603E_V4 = 90;
+  UC_CPU_PPC_603E_V41 = 91;
+  UC_CPU_PPC_603E7T = 92;
+  UC_CPU_PPC_603E7V = 93;
+  UC_CPU_PPC_603E7V1 = 94;
+  UC_CPU_PPC_603E7V2 = 95;
+  UC_CPU_PPC_603E7 = 96;
+  UC_CPU_PPC_603P = 97;
+  UC_CPU_PPC_604 = 98;
+  UC_CPU_PPC_604E_V10 = 99;
+  UC_CPU_PPC_604E_V22 = 100;
+  UC_CPU_PPC_604E_V24 = 101;
+  UC_CPU_PPC_604R = 102;
+  UC_CPU_PPC_7X0_V10 = 103;
+  UC_CPU_PPC_7X0_V20 = 104;
+  UC_CPU_PPC_7X0_V21 = 105;
+  UC_CPU_PPC_7X0_V22 = 106;
+  UC_CPU_PPC_7X0_V30 = 107;
+  UC_CPU_PPC_7X0_V31 = 108;
+  UC_CPU_PPC_740E = 109;
+  UC_CPU_PPC_750E = 110;
+  UC_CPU_PPC_7X0P = 111;
+  UC_CPU_PPC_750CL_V10 = 112;
+  UC_CPU_PPC_750CL_V20 = 113;
+  UC_CPU_PPC_750CX_V10 = 114;
+  UC_CPU_PPC_750CX_V20 = 115;
+  UC_CPU_PPC_750CX_V21 = 116;
+  UC_CPU_PPC_750CX_V22 = 117;
+  UC_CPU_PPC_750CXE_V21 = 118;
+  UC_CPU_PPC_750CXE_V22 = 119;
+  UC_CPU_PPC_750CXE_V23 = 120;
+  UC_CPU_PPC_750CXE_V24 = 121;
+  UC_CPU_PPC_750CXE_V24B = 122;
+  UC_CPU_PPC_750CXE_V30 = 123;
+  UC_CPU_PPC_750CXE_V31 = 124;
+  UC_CPU_PPC_750CXE_V31B = 125;
+  UC_CPU_PPC_750CXR = 126;
+  UC_CPU_PPC_750FL = 127;
+  UC_CPU_PPC_750FX_V10 = 128;
+  UC_CPU_PPC_750FX_V20 = 129;
+  UC_CPU_PPC_750FX_V21 = 130;
+  UC_CPU_PPC_750FX_V22 = 131;
+  UC_CPU_PPC_750FX_V23 = 132;
+  UC_CPU_PPC_750GL = 133;
+  UC_CPU_PPC_750GX_V10 = 134;
+  UC_CPU_PPC_750GX_V11 = 135;
+  UC_CPU_PPC_750GX_V12 = 136;
+  UC_CPU_PPC_750L_V20 = 137;
+  UC_CPU_PPC_750L_V21 = 138;
+  UC_CPU_PPC_750L_V22 = 139;
+  UC_CPU_PPC_750L_V30 = 140;
+  UC_CPU_PPC_750L_V32 = 141;
+  UC_CPU_PPC_7X5_V10 = 142;
+  UC_CPU_PPC_7X5_V11 = 143;
+  UC_CPU_PPC_7X5_V20 = 144;
+  UC_CPU_PPC_7X5_V21 = 145;
+  UC_CPU_PPC_7X5_V22 = 146;
+  UC_CPU_PPC_7X5_V23 = 147;
+  UC_CPU_PPC_7X5_V24 = 148;
+  UC_CPU_PPC_7X5_V25 = 149;
+  UC_CPU_PPC_7X5_V26 = 150;
+  UC_CPU_PPC_7X5_V27 = 151;
+  UC_CPU_PPC_7X5_V28 = 152;
+  UC_CPU_PPC_7400_V10 = 153;
+  UC_CPU_PPC_7400_V11 = 154;
+  UC_CPU_PPC_7400_V20 = 155;
+  UC_CPU_PPC_7400_V21 = 156;
+  UC_CPU_PPC_7400_V22 = 157;
+  UC_CPU_PPC_7400_V26 = 158;
+  UC_CPU_PPC_7400_V27 = 159;
+  UC_CPU_PPC_7400_V28 = 160;
+  UC_CPU_PPC_7400_V29 = 161;
+  UC_CPU_PPC_7410_V10 = 162;
+  UC_CPU_PPC_7410_V11 = 163;
+  UC_CPU_PPC_7410_V12 = 164;
+  UC_CPU_PPC_7410_V13 = 165;
+  UC_CPU_PPC_7410_V14 = 166;
+  UC_CPU_PPC_7448_V10 = 167;
+  UC_CPU_PPC_7448_V11 = 168;
+  UC_CPU_PPC_7448_V20 = 169;
+  UC_CPU_PPC_7448_V21 = 170;
+  UC_CPU_PPC_7450_V10 = 171;
+  UC_CPU_PPC_7450_V11 = 172;
+  UC_CPU_PPC_7450_V12 = 173;
+  UC_CPU_PPC_7450_V20 = 174;
+  UC_CPU_PPC_7450_V21 = 175;
+  UC_CPU_PPC_74X1_V23 = 176;
+  UC_CPU_PPC_74X1_V210 = 177;
+  UC_CPU_PPC_74X5_V10 = 178;
+  UC_CPU_PPC_74X5_V21 = 179;
+  UC_CPU_PPC_74X5_V32 = 180;
+  UC_CPU_PPC_74X5_V33 = 181;
+  UC_CPU_PPC_74X5_V34 = 182;
+  UC_CPU_PPC_74X7_V10 = 183;
+  UC_CPU_PPC_74X7_V11 = 184;
+  UC_CPU_PPC_74X7_V12 = 185;
+  UC_CPU_PPC_74X7A_V10 = 186;
+  UC_CPU_PPC_74X7A_V11 = 187;
+  UC_CPU_PPC_74X7A_V12 = 188;
+  UC_CPU_PPC_IOP480 = 1;
+  UC_CPU_PPC_X2VP20 = 42;
+  UC_CPU_PPC_440GRA = 35;
+  UC_CPU_PPC_440EPX = 38;
+  UC_CPU_PPC_MPC5200_V10 = 59;
+  UC_CPU_PPC_MPC5200_V11 = 59;
+  UC_CPU_PPC_MPC5200_V12 = 59;
+  UC_CPU_PPC_MPC5200B_V20 = 59;
+  UC_CPU_PPC_MPC5200B_V21 = 59;
+  UC_CPU_PPC_MPC834X = 63;
+  UC_CPU_PPC_MPC837X = 66;
+  UC_CPU_PPC_E500 = 73;
+  UC_CPU_PPC_MPC8533_V10 = 72;
+  UC_CPU_PPC_MPC8533_V11 = 73;
+  UC_CPU_PPC_MPC8533E_V10 = 72;
+  UC_CPU_PPC_MPC8533E_V11 = 73;
+  UC_CPU_PPC_MPC8540_V10 = 67;
+  UC_CPU_PPC_MPC8540_V20 = 68;
+  UC_CPU_PPC_MPC8540_V21 = 68;
+  UC_CPU_PPC_MPC8541_V10 = 68;
+  UC_CPU_PPC_MPC8541_V11 = 68;
+  UC_CPU_PPC_MPC8541E_V10 = 68;
+  UC_CPU_PPC_MPC8541E_V11 = 68;
+  UC_CPU_PPC_MPC8543_V10 = 69;
+  UC_CPU_PPC_MPC8543_V11 = 70;
+  UC_CPU_PPC_MPC8543_V20 = 71;
+  UC_CPU_PPC_MPC8543_V21 = 72;
+  UC_CPU_PPC_MPC8543E_V10 = 69;
+  UC_CPU_PPC_MPC8543E_V11 = 70;
+  UC_CPU_PPC_MPC8543E_V20 = 71;
+  UC_CPU_PPC_MPC8543E_V21 = 72;
+  UC_CPU_PPC_MPC8544_V10 = 72;
+  UC_CPU_PPC_MPC8544_V11 = 73;
+  UC_CPU_PPC_MPC8544E_V11 = 73;
+  UC_CPU_PPC_MPC8544E_V10 = 72;
+  UC_CPU_PPC_MPC8545_V10 = 69;
+  UC_CPU_PPC_MPC8545_V20 = 71;
+  UC_CPU_PPC_MPC8545_V21 = 72;
+  UC_CPU_PPC_MPC8545E_V10 = 69;
+  UC_CPU_PPC_MPC8545E_V20 = 71;
+  UC_CPU_PPC_MPC8545E_V21 = 72;
+  UC_CPU_PPC_MPC8547E_V10 = 69;
+  UC_CPU_PPC_MPC8547E_V20 = 71;
+  UC_CPU_PPC_MPC8547E_V21 = 72;
+  UC_CPU_PPC_MPC8548_V10 = 69;
+  UC_CPU_PPC_MPC8548_V11 = 70;
+  UC_CPU_PPC_MPC8548_V20 = 71;
+  UC_CPU_PPC_MPC8548_V21 = 72;
+  UC_CPU_PPC_MPC8548E_V10 = 69;
+  UC_CPU_PPC_MPC8548E_V11 = 70;
+  UC_CPU_PPC_MPC8548E_V20 = 71;
+  UC_CPU_PPC_MPC8548E_V21 = 72;
+  UC_CPU_PPC_MPC8555_V10 = 69;
+  UC_CPU_PPC_MPC8555_V11 = 70;
+  UC_CPU_PPC_MPC8555E_V10 = 69;
+  UC_CPU_PPC_MPC8555E_V11 = 70;
+  UC_CPU_PPC_MPC8560_V10 = 69;
+  UC_CPU_PPC_MPC8560_V20 = 71;
+  UC_CPU_PPC_MPC8560_V21 = 72;
+  UC_CPU_PPC_MPC8567 = 73;
+  UC_CPU_PPC_MPC8567E = 73;
+  UC_CPU_PPC_MPC8568 = 73;
+  UC_CPU_PPC_MPC8568E = 73;
+  UC_CPU_PPC_MPC8572 = 74;
+  UC_CPU_PPC_MPC8572E = 74;
+  UC_CPU_PPC_MPC8610 = 78;
+  UC_CPU_PPC_MPC8641 = 78;
+  UC_CPU_PPC_MPC8641D = 78;
+
+  UC_CPU_PPC64_620 = 0;
+  UC_CPU_PPC64_630 = 1;
+  UC_CPU_PPC64_631 = 2;
+  UC_CPU_PPC64_POWER4 = 3;
+  UC_CPU_PPC64_POWER4P = 4;
+  UC_CPU_PPC64_POWER5 = 5;
+  UC_CPU_PPC64_POWER5P_V21 = 6;
+  UC_CPU_PPC64_POWER6 = 7;
+  UC_CPU_PPC64_POWER_SERVER_MASK = 8;
+  UC_CPU_PPC64_POWER7_BASE = 9;
+  UC_CPU_PPC64_POWER7_V23 = 10;
+  UC_CPU_PPC64_POWER7P_BASE = 11;
+  UC_CPU_PPC64_POWER7P_V21 = 12;
+  UC_CPU_PPC64_POWER8E_BASE = 13;
+  UC_CPU_PPC64_POWER8E_V21 = 14;
+  UC_CPU_PPC64_POWER8_BASE = 15;
+  UC_CPU_PPC64_POWER8_V20 = 16;
+  UC_CPU_PPC64_POWER8NVL_BASE = 17;
+  UC_CPU_PPC64_POWER8NVL_V10 = 18;
+  UC_CPU_PPC64_POWER9_BASE = 19;
+  UC_CPU_PPC64_POWER9_DD1 = 20;
+  UC_CPU_PPC64_POWER9_DD20 = 21;
+  UC_CPU_PPC64_POWER10_BASE = 22;
+  UC_CPU_PPC64_POWER10_DD1 = 23;
+  UC_CPU_PPC64_970_V22 = 24;
+  UC_CPU_PPC64_970FX_V10 = 25;
+  UC_CPU_PPC64_970FX_V20 = 26;
+  UC_CPU_PPC64_970FX_V21 = 27;
+  UC_CPU_PPC64_970FX_V30 = 28;
+  UC_CPU_PPC64_970FX_V31 = 29;
+  UC_CPU_PPC64_970MP_V10 = 30;
+  UC_CPU_PPC64_970MP_V11 = 31;
+  UC_CPU_PPC64_CELL_V10 = 32;
+  UC_CPU_PPC64_CELL_V20 = 33;
+  UC_CPU_PPC64_CELL_V30 = 34;
+  UC_CPU_PPC64_CELL_V31 = 35;
+  UC_CPU_PPC64_RS64 = 36;
+  UC_CPU_PPC64_RS64II = 37;
+  UC_CPU_PPC64_RS64III = 38;
+  UC_CPU_PPC64_RS64IV = 39;
+  UC_CPU_PPC64_CELL_V32 = 35;
+  UC_CPU_PPC64_CELL = 35;
+
 // PPC registers
 
   UC_PPC_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/RiscvConst.pas b/bindings/pascal/unicorn/RiscvConst.pas
index 7aaa9b74..98a30ce5 100644
--- a/bindings/pascal/unicorn/RiscvConst.pas
+++ b/bindings/pascal/unicorn/RiscvConst.pas
@@ -5,6 +5,16 @@ unit RiscvConst;
 interface
 
 const
+  UC_CPU_RISCV32_ANY = 0;
+  UC_CPU_RISCV32_BASE32 = 1;
+  UC_CPU_RISCV32_SIFIVE_E31 = 2;
+  UC_CPU_RISCV32_SIFIVE_U34 = 3;
+
+  UC_CPU_RISCV64_ANY = 0;
+  UC_CPU_RISCV64_BASE64 = 1;
+  UC_CPU_RISCV64_SIFIVE_E51 = 2;
+  UC_CPU_RISCV64_SIFIVE_U54 = 3;
+
 // RISCV registers
 
   UC_RISCV_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/SparcConst.pas b/bindings/pascal/unicorn/SparcConst.pas
index 32ed3013..9e77d3bb 100644
--- a/bindings/pascal/unicorn/SparcConst.pas
+++ b/bindings/pascal/unicorn/SparcConst.pas
@@ -5,6 +5,38 @@ unit SparcConst;
 interface
 
 const
+  UC_CPU_SPARC_FUJITSU_MB86904 = 0;
+  UC_CPU_SPARC_FUJITSU_MB86907 = 1;
+  UC_CPU_SPARC_TI_MICROSPARC_I = 2;
+  UC_CPU_SPARC_TI_MICROSPARC_II = 3;
+  UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4;
+  UC_CPU_SPARC_TI_SUPERSPARC_40 = 5;
+  UC_CPU_SPARC_TI_SUPERSPARC_50 = 6;
+  UC_CPU_SPARC_TI_SUPERSPARC_51 = 7;
+  UC_CPU_SPARC_TI_SUPERSPARC_60 = 8;
+  UC_CPU_SPARC_TI_SUPERSPARC_61 = 9;
+  UC_CPU_SPARC_TI_SUPERSPARC_II = 10;
+  UC_CPU_SPARC_LEON2 = 11;
+  UC_CPU_SPARC_LEON3 = 12;
+
+  UC_CPU_SPARC64_FUJITSU = 0;
+  UC_CPU_SPARC64_FUJITSU_III = 1;
+  UC_CPU_SPARC64_FUJITSU_IV = 2;
+  UC_CPU_SPARC64_FUJITSU_V = 3;
+  UC_CPU_SPARC64_TI_ULTRASPARC_I = 4;
+  UC_CPU_SPARC64_TI_ULTRASPARC_II = 5;
+  UC_CPU_SPARC64_TI_ULTRASPARC_III = 6;
+  UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15;
+  UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16;
+
 // SPARC registers
 
   UC_SPARC_REG_INVALID = 0;
diff --git a/bindings/pascal/unicorn/UnicornConst.pas b/bindings/pascal/unicorn/UnicornConst.pas
index 29303b89..6884687b 100644
--- a/bindings/pascal/unicorn/UnicornConst.pas
+++ b/bindings/pascal/unicorn/UnicornConst.pas
@@ -110,6 +110,22 @@ const  UC_API_MAJOR = 2;
   UC_QUERY_ARCH = 3;
   UC_QUERY_TIMEOUT = 4;
 
+  UC_CTL_IO_NONE = 0;
+  UC_CTL_IO_WRITE = 1;
+  UC_CTL_IO_READ = 2;
+  UC_CTL_IO_READ_WRITE = 3;
+
+  UC_CTL_UC_MODE = 0;
+  UC_CTL_UC_PAGE_SIZE = 1;
+  UC_CTL_UC_ARCH = 2;
+  UC_CTL_UC_TIMEOUT = 3;
+  UC_CTL_UC_EXITS_CNT = 4;
+  UC_CTL_UC_EXITS = 5;
+  UC_CTL_CPU_MODEL = 6;
+  UC_CTL_TB_EDGE = 7;
+  UC_CTL_TB_REQUEST_CACHE = 8;
+  UC_CTL_TB_REMOVE_CACHE = 9;
+
   UC_PROT_NONE = 0;
   UC_PROT_READ = 1;
   UC_PROT_WRITE = 2;
diff --git a/bindings/pascal/unicorn/X86Const.pas b/bindings/pascal/unicorn/X86Const.pas
index 9f05a6f6..446f7602 100644
--- a/bindings/pascal/unicorn/X86Const.pas
+++ b/bindings/pascal/unicorn/X86Const.pas
@@ -5,6 +5,45 @@ unit X86Const;
 interface
 
 const
+  UC_CPU_X86_QEMU64 = 0;
+  UC_CPU_X86_PHENOM = 1;
+  UC_CPU_X86_CORE2DUO = 2;
+  UC_CPU_X86_KVM64 = 3;
+  UC_CPU_X86_QEMU32 = 4;
+  UC_CPU_X86_KVM32 = 5;
+  UC_CPU_X86_COREDUO = 6;
+  UC_CPU_X86_486 = 7;
+  UC_CPU_X86_PENTIUM = 8;
+  UC_CPU_X86_PENTIUM2 = 9;
+  UC_CPU_X86_PENTIUM3 = 10;
+  UC_CPU_X86_ATHLON = 11;
+  UC_CPU_X86_N270 = 12;
+  UC_CPU_X86_CONROE = 13;
+  UC_CPU_X86_PENRYN = 14;
+  UC_CPU_X86_NEHALEM = 15;
+  UC_CPU_X86_WESTMERE = 16;
+  UC_CPU_X86_SANDYBRIDGE = 17;
+  UC_CPU_X86_IVYBRIDGE = 18;
+  UC_CPU_X86_HASWELL = 19;
+  UC_CPU_X86_BROADWELL = 20;
+  UC_CPU_X86_SKYLAKE_CLIENT = 21;
+  UC_CPU_X86_SKYLAKE_SERVER = 22;
+  UC_CPU_X86_CASCADELAKE_SERVER = 23;
+  UC_CPU_X86_COOPERLAKE = 24;
+  UC_CPU_X86_ICELAKE_CLIENT = 25;
+  UC_CPU_X86_ICELAKE_SERVER = 26;
+  UC_CPU_X86_DENVERTON = 27;
+  UC_CPU_X86_SNOWRIDGE = 28;
+  UC_CPU_X86_KNIGHTSMILL = 29;
+  UC_CPU_X86_OPTERON_G1 = 30;
+  UC_CPU_X86_OPTERON_G2 = 31;
+  UC_CPU_X86_OPTERON_G3 = 32;
+  UC_CPU_X86_OPTERON_G4 = 33;
+  UC_CPU_X86_OPTERON_G5 = 34;
+  UC_CPU_X86_EPYC = 35;
+  UC_CPU_X86_DHYANA = 36;
+  UC_CPU_X86_EPYC_ROME = 37;
+
 // X86 registers
 
   UC_X86_REG_INVALID = 0;
diff --git a/bindings/python/unicorn/arm64_const.py b/bindings/python/unicorn/arm64_const.py
index ae8e77eb..867aba49 100644
--- a/bindings/python/unicorn/arm64_const.py
+++ b/bindings/python/unicorn/arm64_const.py
@@ -1,5 +1,10 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
 
+UC_CPU_AARCH64_A57 = 0
+UC_CPU_AARCH64_A53 = 1
+UC_CPU_AARCH64_A72 = 2
+UC_CPU_AARCH64_MAX = 3
+
 # ARM64 registers
 
 UC_ARM64_REG_INVALID = 0
diff --git a/bindings/python/unicorn/arm_const.py b/bindings/python/unicorn/arm_const.py
index 8526f2b9..af8fb5ab 100644
--- a/bindings/python/unicorn/arm_const.py
+++ b/bindings/python/unicorn/arm_const.py
@@ -1,5 +1,39 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
 
+UC_CPU_ARM_926 = 0
+UC_CPU_ARM_946 = 1
+UC_CPU_ARM_1026 = 2
+UC_CPU_ARM_1136_R2 = 3
+UC_CPU_ARM_1136 = 4
+UC_CPU_ARM_1176 = 5
+UC_CPU_ARM_11MPCORE = 6
+UC_CPU_ARM_CORTEX_M0 = 7
+UC_CPU_ARM_CORTEX_M3 = 8
+UC_CPU_ARM_CORTEX_M4 = 9
+UC_CPU_ARM_CORTEX_M7 = 10
+UC_CPU_ARM_CORTEX_M33 = 11
+UC_CPU_ARM_CORTEX_R5 = 12
+UC_CPU_ARM_CORTEX_R5F = 13
+UC_CPU_ARM_CORTEX_A8 = 14
+UC_CPU_ARM_CORTEX_A9 = 15
+UC_CPU_ARM_CORTEX_A7 = 16
+UC_CPU_ARM_CORTEX_A15 = 17
+UC_CPU_ARM_TI925T = 18
+UC_CPU_ARM_SA1100 = 19
+UC_CPU_ARM_SA1110 = 20
+UC_CPU_ARM_PXA250 = 21
+UC_CPU_ARM_PXA255 = 22
+UC_CPU_ARM_PXA260 = 23
+UC_CPU_ARM_PXA261 = 24
+UC_CPU_ARM_PXA262 = 25
+UC_CPU_ARM_PXA270A0 = 26
+UC_CPU_ARM_PXA270A1 = 27
+UC_CPU_ARM_PXA270B0 = 28
+UC_CPU_ARM_PXA270B1 = 29
+UC_CPU_ARM_PXA270C0 = 30
+UC_CPU_ARM_PXA270C5 = 31
+UC_CPU_ARM_MAX = 32
+
 # ARM registers
 
 UC_ARM_REG_INVALID = 0
diff --git a/bindings/python/unicorn/m68k_const.py b/bindings/python/unicorn/m68k_const.py
index 37b00b99..f585b225 100644
--- a/bindings/python/unicorn/m68k_const.py
+++ b/bindings/python/unicorn/m68k_const.py
@@ -1,5 +1,15 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
 
+UC_CPU_M5206_CPU = 0
+UC_CPU_M68000_CPU = 1
+UC_CPU_M68020_CPU = 2
+UC_CPU_M68030_CPU = 3
+UC_CPU_M68040_CPU = 4
+UC_CPU_M68060_CPU = 5
+UC_CPU_M5208_CPU = 6
+UC_CPU_CFV4E_CPU = 7
+UC_CPU_ANY_CPU = 8
+
 # M68K registers
 
 UC_M68K_REG_INVALID = 0
diff --git a/bindings/python/unicorn/mips_const.py b/bindings/python/unicorn/mips_const.py
index a8370ae4..43b0e49f 100644
--- a/bindings/python/unicorn/mips_const.py
+++ b/bindings/python/unicorn/mips_const.py
@@ -1,5 +1,35 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
 
+UC_CPU_MIPS_4KC = 0
+UC_CPU_MIPS_4KM = 1
+UC_CPU_MIPS_4KECR1 = 2
+UC_CPU_MIPS_4KEMR1 = 3
+UC_CPU_MIPS_4KEC = 4
+UC_CPU_MIPS_4KEM = 5
+UC_CPU_MIPS_24KC = 6
+UC_CPU_MIPS_24KEC = 7
+UC_CPU_MIPS_24KF = 8
+UC_CPU_MIPS_34KF = 9
+UC_CPU_MIPS_74KF = 10
+UC_CPU_MIPS_M14K = 11
+UC_CPU_MIPS_M14KC = 12
+UC_CPU_MIPS_P5600 = 13
+UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+UC_CPU_MIPS_I7200 = 15
+UC_CPU_MIPS_R4000 = 16
+UC_CPU_MIPS_VR5432 = 17
+UC_CPU_MIPS_5KC = 18
+UC_CPU_MIPS_5KF = 19
+UC_CPU_MIPS_20KC = 20
+UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+UC_CPU_MIPS_5KEC = 22
+UC_CPU_MIPS_5KEF = 23
+UC_CPU_MIPS_I6400 = 24
+UC_CPU_MIPS_I6500 = 25
+UC_CPU_MIPS_LOONGSON_2E = 26
+UC_CPU_MIPS_LOONGSON_2F = 27
+UC_CPU_MIPS_MIPS64DSPR2 = 28
+
 # MIPS registers
 
 UC_MIPS_REG_INVALID = 0
diff --git a/bindings/python/unicorn/ppc_const.py b/bindings/python/unicorn/ppc_const.py
index 18162dac..1d4813cb 100644
--- a/bindings/python/unicorn/ppc_const.py
+++ b/bindings/python/unicorn/ppc_const.py
@@ -1,5 +1,306 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py]
 
+UC_CPU_PPC_401A1 = 0
+UC_CPU_PPC_401B2 = 1
+UC_CPU_PPC_401C2 = 2
+UC_CPU_PPC_401D2 = 3
+UC_CPU_PPC_401E2 = 4
+UC_CPU_PPC_401F2 = 5
+UC_CPU_PPC_401G2 = 6
+UC_CPU_PPC_COBRA = 7
+UC_CPU_PPC_403GA = 8
+UC_CPU_PPC_403GB = 9
+UC_CPU_PPC_403GC = 10
+UC_CPU_PPC_403GCX = 11
+UC_CPU_PPC_405D2 = 12
+UC_CPU_PPC_405D4 = 13
+UC_CPU_PPC_405CRA = 14
+UC_CPU_PPC_405CRB = 15
+UC_CPU_PPC_405CRC = 16
+UC_CPU_PPC_405EP = 17
+UC_CPU_PPC_405EZ = 18
+UC_CPU_PPC_405GPA = 19
+UC_CPU_PPC_405GPB = 20
+UC_CPU_PPC_405GPC = 21
+UC_CPU_PPC_405GPD = 22
+UC_CPU_PPC_405GPR = 23
+UC_CPU_PPC_405LP = 24
+UC_CPU_PPC_NPE405H = 25
+UC_CPU_PPC_NPE405H2 = 26
+UC_CPU_PPC_NPE405L = 27
+UC_CPU_PPC_NPE4GS3 = 28
+UC_CPU_PPC_STB03 = 29
+UC_CPU_PPC_STB04 = 30
+UC_CPU_PPC_STB25 = 31
+UC_CPU_PPC_X2VP4 = 32
+UC_CPU_PPC_440_XILINX = 33
+UC_CPU_PPC_440EPA = 34
+UC_CPU_PPC_440EPB = 35
+UC_CPU_PPC_440GPB = 36
+UC_CPU_PPC_440GPC = 37
+UC_CPU_PPC_440GRX = 38
+UC_CPU_PPC_440GXA = 39
+UC_CPU_PPC_440GXB = 40
+UC_CPU_PPC_440GXC = 41
+UC_CPU_PPC_440GXF = 42
+UC_CPU_PPC_440SP = 43
+UC_CPU_PPC_440SP2 = 44
+UC_CPU_PPC_440SPE = 45
+UC_CPU_PPC_460EXB = 46
+UC_CPU_PPC_MPC5XX = 47
+UC_CPU_PPC_MPC8XX = 48
+UC_CPU_PPC_G2 = 49
+UC_CPU_PPC_G2H4 = 50
+UC_CPU_PPC_G2GP = 51
+UC_CPU_PPC_G2LS = 52
+UC_CPU_PPC_MPC603 = 53
+UC_CPU_PPC_G2_HIP3 = 54
+UC_CPU_PPC_G2_HIP4 = 55
+UC_CPU_PPC_G2LE = 56
+UC_CPU_PPC_G2LEGP = 57
+UC_CPU_PPC_G2LELS = 58
+UC_CPU_PPC_G2LEGP1 = 59
+UC_CPU_PPC_G2LEGP3 = 60
+UC_CPU_PPC_E200Z5 = 61
+UC_CPU_PPC_E200Z6 = 62
+UC_CPU_PPC_E300C1 = 63
+UC_CPU_PPC_E300C2 = 64
+UC_CPU_PPC_E300C3 = 65
+UC_CPU_PPC_E300C4 = 66
+UC_CPU_PPC_E500V1_V10 = 67
+UC_CPU_PPC_E500V1_V20 = 68
+UC_CPU_PPC_E500V2_V10 = 69
+UC_CPU_PPC_E500V2_V11 = 70
+UC_CPU_PPC_E500V2_V20 = 71
+UC_CPU_PPC_E500V2_V21 = 72
+UC_CPU_PPC_E500V2_V22 = 73
+UC_CPU_PPC_E500V2_V30 = 74
+UC_CPU_PPC_E500MC = 75
+UC_CPU_PPC_E5500 = 76
+UC_CPU_PPC_E6500 = 77
+UC_CPU_PPC_E600 = 78
+UC_CPU_PPC_601_V0 = 79
+UC_CPU_PPC_601_V1 = 80
+UC_CPU_PPC_601_V2 = 81
+UC_CPU_PPC_602 = 82
+UC_CPU_PPC_603 = 83
+UC_CPU_PPC_603E_V11 = 84
+UC_CPU_PPC_603E_V12 = 85
+UC_CPU_PPC_603E_V13 = 86
+UC_CPU_PPC_603E_V14 = 87
+UC_CPU_PPC_603E_V22 = 88
+UC_CPU_PPC_603E_V3 = 89
+UC_CPU_PPC_603E_V4 = 90
+UC_CPU_PPC_603E_V41 = 91
+UC_CPU_PPC_603E7T = 92
+UC_CPU_PPC_603E7V = 93
+UC_CPU_PPC_603E7V1 = 94
+UC_CPU_PPC_603E7V2 = 95
+UC_CPU_PPC_603E7 = 96
+UC_CPU_PPC_603P = 97
+UC_CPU_PPC_604 = 98
+UC_CPU_PPC_604E_V10 = 99
+UC_CPU_PPC_604E_V22 = 100
+UC_CPU_PPC_604E_V24 = 101
+UC_CPU_PPC_604R = 102
+UC_CPU_PPC_7X0_V10 = 103
+UC_CPU_PPC_7X0_V20 = 104
+UC_CPU_PPC_7X0_V21 = 105
+UC_CPU_PPC_7X0_V22 = 106
+UC_CPU_PPC_7X0_V30 = 107
+UC_CPU_PPC_7X0_V31 = 108
+UC_CPU_PPC_740E = 109
+UC_CPU_PPC_750E = 110
+UC_CPU_PPC_7X0P = 111
+UC_CPU_PPC_750CL_V10 = 112
+UC_CPU_PPC_750CL_V20 = 113
+UC_CPU_PPC_750CX_V10 = 114
+UC_CPU_PPC_750CX_V20 = 115
+UC_CPU_PPC_750CX_V21 = 116
+UC_CPU_PPC_750CX_V22 = 117
+UC_CPU_PPC_750CXE_V21 = 118
+UC_CPU_PPC_750CXE_V22 = 119
+UC_CPU_PPC_750CXE_V23 = 120
+UC_CPU_PPC_750CXE_V24 = 121
+UC_CPU_PPC_750CXE_V24B = 122
+UC_CPU_PPC_750CXE_V30 = 123
+UC_CPU_PPC_750CXE_V31 = 124
+UC_CPU_PPC_750CXE_V31B = 125
+UC_CPU_PPC_750CXR = 126
+UC_CPU_PPC_750FL = 127
+UC_CPU_PPC_750FX_V10 = 128
+UC_CPU_PPC_750FX_V20 = 129
+UC_CPU_PPC_750FX_V21 = 130
+UC_CPU_PPC_750FX_V22 = 131
+UC_CPU_PPC_750FX_V23 = 132
+UC_CPU_PPC_750GL = 133
+UC_CPU_PPC_750GX_V10 = 134
+UC_CPU_PPC_750GX_V11 = 135
+UC_CPU_PPC_750GX_V12 = 136
+UC_CPU_PPC_750L_V20 = 137
+UC_CPU_PPC_750L_V21 = 138
+UC_CPU_PPC_750L_V22 = 139
+UC_CPU_PPC_750L_V30 = 140
+UC_CPU_PPC_750L_V32 = 141
+UC_CPU_PPC_7X5_V10 = 142
+UC_CPU_PPC_7X5_V11 = 143
+UC_CPU_PPC_7X5_V20 = 144
+UC_CPU_PPC_7X5_V21 = 145
+UC_CPU_PPC_7X5_V22 = 146
+UC_CPU_PPC_7X5_V23 = 147
+UC_CPU_PPC_7X5_V24 = 148
+UC_CPU_PPC_7X5_V25 = 149
+UC_CPU_PPC_7X5_V26 = 150
+UC_CPU_PPC_7X5_V27 = 151
+UC_CPU_PPC_7X5_V28 = 152
+UC_CPU_PPC_7400_V10 = 153
+UC_CPU_PPC_7400_V11 = 154
+UC_CPU_PPC_7400_V20 = 155
+UC_CPU_PPC_7400_V21 = 156
+UC_CPU_PPC_7400_V22 = 157
+UC_CPU_PPC_7400_V26 = 158
+UC_CPU_PPC_7400_V27 = 159
+UC_CPU_PPC_7400_V28 = 160
+UC_CPU_PPC_7400_V29 = 161
+UC_CPU_PPC_7410_V10 = 162
+UC_CPU_PPC_7410_V11 = 163
+UC_CPU_PPC_7410_V12 = 164
+UC_CPU_PPC_7410_V13 = 165
+UC_CPU_PPC_7410_V14 = 166
+UC_CPU_PPC_7448_V10 = 167
+UC_CPU_PPC_7448_V11 = 168
+UC_CPU_PPC_7448_V20 = 169
+UC_CPU_PPC_7448_V21 = 170
+UC_CPU_PPC_7450_V10 = 171
+UC_CPU_PPC_7450_V11 = 172
+UC_CPU_PPC_7450_V12 = 173
+UC_CPU_PPC_7450_V20 = 174
+UC_CPU_PPC_7450_V21 = 175
+UC_CPU_PPC_74X1_V23 = 176
+UC_CPU_PPC_74X1_V210 = 177
+UC_CPU_PPC_74X5_V10 = 178
+UC_CPU_PPC_74X5_V21 = 179
+UC_CPU_PPC_74X5_V32 = 180
+UC_CPU_PPC_74X5_V33 = 181
+UC_CPU_PPC_74X5_V34 = 182
+UC_CPU_PPC_74X7_V10 = 183
+UC_CPU_PPC_74X7_V11 = 184
+UC_CPU_PPC_74X7_V12 = 185
+UC_CPU_PPC_74X7A_V10 = 186
+UC_CPU_PPC_74X7A_V11 = 187
+UC_CPU_PPC_74X7A_V12 = 188
+UC_CPU_PPC_IOP480 = 1
+UC_CPU_PPC_X2VP20 = 42
+UC_CPU_PPC_440GRA = 35
+UC_CPU_PPC_440EPX = 38
+UC_CPU_PPC_MPC5200_V10 = 59
+UC_CPU_PPC_MPC5200_V11 = 59
+UC_CPU_PPC_MPC5200_V12 = 59
+UC_CPU_PPC_MPC5200B_V20 = 59
+UC_CPU_PPC_MPC5200B_V21 = 59
+UC_CPU_PPC_MPC834X = 63
+UC_CPU_PPC_MPC837X = 66
+UC_CPU_PPC_E500 = 73
+UC_CPU_PPC_MPC8533_V10 = 72
+UC_CPU_PPC_MPC8533_V11 = 73
+UC_CPU_PPC_MPC8533E_V10 = 72
+UC_CPU_PPC_MPC8533E_V11 = 73
+UC_CPU_PPC_MPC8540_V10 = 67
+UC_CPU_PPC_MPC8540_V20 = 68
+UC_CPU_PPC_MPC8540_V21 = 68
+UC_CPU_PPC_MPC8541_V10 = 68
+UC_CPU_PPC_MPC8541_V11 = 68
+UC_CPU_PPC_MPC8541E_V10 = 68
+UC_CPU_PPC_MPC8541E_V11 = 68
+UC_CPU_PPC_MPC8543_V10 = 69
+UC_CPU_PPC_MPC8543_V11 = 70
+UC_CPU_PPC_MPC8543_V20 = 71
+UC_CPU_PPC_MPC8543_V21 = 72
+UC_CPU_PPC_MPC8543E_V10 = 69
+UC_CPU_PPC_MPC8543E_V11 = 70
+UC_CPU_PPC_MPC8543E_V20 = 71
+UC_CPU_PPC_MPC8543E_V21 = 72
+UC_CPU_PPC_MPC8544_V10 = 72
+UC_CPU_PPC_MPC8544_V11 = 73
+UC_CPU_PPC_MPC8544E_V11 = 73
+UC_CPU_PPC_MPC8544E_V10 = 72
+UC_CPU_PPC_MPC8545_V10 = 69
+UC_CPU_PPC_MPC8545_V20 = 71
+UC_CPU_PPC_MPC8545_V21 = 72
+UC_CPU_PPC_MPC8545E_V10 = 69
+UC_CPU_PPC_MPC8545E_V20 = 71
+UC_CPU_PPC_MPC8545E_V21 = 72
+UC_CPU_PPC_MPC8547E_V10 = 69
+UC_CPU_PPC_MPC8547E_V20 = 71
+UC_CPU_PPC_MPC8547E_V21 = 72
+UC_CPU_PPC_MPC8548_V10 = 69
+UC_CPU_PPC_MPC8548_V11 = 70
+UC_CPU_PPC_MPC8548_V20 = 71
+UC_CPU_PPC_MPC8548_V21 = 72
+UC_CPU_PPC_MPC8548E_V10 = 69
+UC_CPU_PPC_MPC8548E_V11 = 70
+UC_CPU_PPC_MPC8548E_V20 = 71
+UC_CPU_PPC_MPC8548E_V21 = 72
+UC_CPU_PPC_MPC8555_V10 = 69
+UC_CPU_PPC_MPC8555_V11 = 70
+UC_CPU_PPC_MPC8555E_V10 = 69
+UC_CPU_PPC_MPC8555E_V11 = 70
+UC_CPU_PPC_MPC8560_V10 = 69
+UC_CPU_PPC_MPC8560_V20 = 71
+UC_CPU_PPC_MPC8560_V21 = 72
+UC_CPU_PPC_MPC8567 = 73
+UC_CPU_PPC_MPC8567E = 73
+UC_CPU_PPC_MPC8568 = 73
+UC_CPU_PPC_MPC8568E = 73
+UC_CPU_PPC_MPC8572 = 74
+UC_CPU_PPC_MPC8572E = 74
+UC_CPU_PPC_MPC8610 = 78
+UC_CPU_PPC_MPC8641 = 78
+UC_CPU_PPC_MPC8641D = 78
+
+UC_CPU_PPC64_620 = 0
+UC_CPU_PPC64_630 = 1
+UC_CPU_PPC64_631 = 2
+UC_CPU_PPC64_POWER4 = 3
+UC_CPU_PPC64_POWER4P = 4
+UC_CPU_PPC64_POWER5 = 5
+UC_CPU_PPC64_POWER5P_V21 = 6
+UC_CPU_PPC64_POWER6 = 7
+UC_CPU_PPC64_POWER_SERVER_MASK = 8
+UC_CPU_PPC64_POWER7_BASE = 9
+UC_CPU_PPC64_POWER7_V23 = 10
+UC_CPU_PPC64_POWER7P_BASE = 11
+UC_CPU_PPC64_POWER7P_V21 = 12
+UC_CPU_PPC64_POWER8E_BASE = 13
+UC_CPU_PPC64_POWER8E_V21 = 14
+UC_CPU_PPC64_POWER8_BASE = 15
+UC_CPU_PPC64_POWER8_V20 = 16
+UC_CPU_PPC64_POWER8NVL_BASE = 17
+UC_CPU_PPC64_POWER8NVL_V10 = 18
+UC_CPU_PPC64_POWER9_BASE = 19
+UC_CPU_PPC64_POWER9_DD1 = 20
+UC_CPU_PPC64_POWER9_DD20 = 21
+UC_CPU_PPC64_POWER10_BASE = 22
+UC_CPU_PPC64_POWER10_DD1 = 23
+UC_CPU_PPC64_970_V22 = 24
+UC_CPU_PPC64_970FX_V10 = 25
+UC_CPU_PPC64_970FX_V20 = 26
+UC_CPU_PPC64_970FX_V21 = 27
+UC_CPU_PPC64_970FX_V30 = 28
+UC_CPU_PPC64_970FX_V31 = 29
+UC_CPU_PPC64_970MP_V10 = 30
+UC_CPU_PPC64_970MP_V11 = 31
+UC_CPU_PPC64_CELL_V10 = 32
+UC_CPU_PPC64_CELL_V20 = 33
+UC_CPU_PPC64_CELL_V30 = 34
+UC_CPU_PPC64_CELL_V31 = 35
+UC_CPU_PPC64_RS64 = 36
+UC_CPU_PPC64_RS64II = 37
+UC_CPU_PPC64_RS64III = 38
+UC_CPU_PPC64_RS64IV = 39
+UC_CPU_PPC64_CELL_V32 = 35
+UC_CPU_PPC64_CELL = 35
+
 # PPC registers
 
 UC_PPC_REG_INVALID = 0
diff --git a/bindings/python/unicorn/riscv_const.py b/bindings/python/unicorn/riscv_const.py
index e4adbcd7..91463afb 100644
--- a/bindings/python/unicorn/riscv_const.py
+++ b/bindings/python/unicorn/riscv_const.py
@@ -1,5 +1,15 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
 
+UC_CPU_RISCV32_ANY = 0
+UC_CPU_RISCV32_BASE32 = 1
+UC_CPU_RISCV32_SIFIVE_E31 = 2
+UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+UC_CPU_RISCV64_ANY = 0
+UC_CPU_RISCV64_BASE64 = 1
+UC_CPU_RISCV64_SIFIVE_E51 = 2
+UC_CPU_RISCV64_SIFIVE_U54 = 3
+
 # RISCV registers
 
 UC_RISCV_REG_INVALID = 0
diff --git a/bindings/python/unicorn/sparc_const.py b/bindings/python/unicorn/sparc_const.py
index 7bd326d0..a15599f0 100644
--- a/bindings/python/unicorn/sparc_const.py
+++ b/bindings/python/unicorn/sparc_const.py
@@ -1,5 +1,37 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
 
+UC_CPU_SPARC_FUJITSU_MB86904 = 0
+UC_CPU_SPARC_FUJITSU_MB86907 = 1
+UC_CPU_SPARC_TI_MICROSPARC_I = 2
+UC_CPU_SPARC_TI_MICROSPARC_II = 3
+UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+UC_CPU_SPARC_LEON2 = 11
+UC_CPU_SPARC_LEON3 = 12
+
+UC_CPU_SPARC64_FUJITSU = 0
+UC_CPU_SPARC64_FUJITSU_III = 1
+UC_CPU_SPARC64_FUJITSU_IV = 2
+UC_CPU_SPARC64_FUJITSU_V = 3
+UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 # SPARC registers
 
 UC_SPARC_REG_INVALID = 0
diff --git a/bindings/python/unicorn/unicorn_const.py b/bindings/python/unicorn/unicorn_const.py
index a517572a..10a7ae51 100644
--- a/bindings/python/unicorn/unicorn_const.py
+++ b/bindings/python/unicorn/unicorn_const.py
@@ -105,6 +105,22 @@ UC_QUERY_PAGE_SIZE = 2
 UC_QUERY_ARCH = 3
 UC_QUERY_TIMEOUT = 4
 
+UC_CTL_IO_NONE = 0
+UC_CTL_IO_WRITE = 1
+UC_CTL_IO_READ = 2
+UC_CTL_IO_READ_WRITE = 3
+
+UC_CTL_UC_MODE = 0
+UC_CTL_UC_PAGE_SIZE = 1
+UC_CTL_UC_ARCH = 2
+UC_CTL_UC_TIMEOUT = 3
+UC_CTL_UC_EXITS_CNT = 4
+UC_CTL_UC_EXITS = 5
+UC_CTL_CPU_MODEL = 6
+UC_CTL_TB_EDGE = 7
+UC_CTL_TB_REQUEST_CACHE = 8
+UC_CTL_TB_REMOVE_CACHE = 9
+
 UC_PROT_NONE = 0
 UC_PROT_READ = 1
 UC_PROT_WRITE = 2
diff --git a/bindings/python/unicorn/x86_const.py b/bindings/python/unicorn/x86_const.py
index 35803fe7..46454371 100644
--- a/bindings/python/unicorn/x86_const.py
+++ b/bindings/python/unicorn/x86_const.py
@@ -1,5 +1,44 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
 
+UC_CPU_X86_QEMU64 = 0
+UC_CPU_X86_PHENOM = 1
+UC_CPU_X86_CORE2DUO = 2
+UC_CPU_X86_KVM64 = 3
+UC_CPU_X86_QEMU32 = 4
+UC_CPU_X86_KVM32 = 5
+UC_CPU_X86_COREDUO = 6
+UC_CPU_X86_486 = 7
+UC_CPU_X86_PENTIUM = 8
+UC_CPU_X86_PENTIUM2 = 9
+UC_CPU_X86_PENTIUM3 = 10
+UC_CPU_X86_ATHLON = 11
+UC_CPU_X86_N270 = 12
+UC_CPU_X86_CONROE = 13
+UC_CPU_X86_PENRYN = 14
+UC_CPU_X86_NEHALEM = 15
+UC_CPU_X86_WESTMERE = 16
+UC_CPU_X86_SANDYBRIDGE = 17
+UC_CPU_X86_IVYBRIDGE = 18
+UC_CPU_X86_HASWELL = 19
+UC_CPU_X86_BROADWELL = 20
+UC_CPU_X86_SKYLAKE_CLIENT = 21
+UC_CPU_X86_SKYLAKE_SERVER = 22
+UC_CPU_X86_CASCADELAKE_SERVER = 23
+UC_CPU_X86_COOPERLAKE = 24
+UC_CPU_X86_ICELAKE_CLIENT = 25
+UC_CPU_X86_ICELAKE_SERVER = 26
+UC_CPU_X86_DENVERTON = 27
+UC_CPU_X86_SNOWRIDGE = 28
+UC_CPU_X86_KNIGHTSMILL = 29
+UC_CPU_X86_OPTERON_G1 = 30
+UC_CPU_X86_OPTERON_G2 = 31
+UC_CPU_X86_OPTERON_G3 = 32
+UC_CPU_X86_OPTERON_G4 = 33
+UC_CPU_X86_OPTERON_G5 = 34
+UC_CPU_X86_EPYC = 35
+UC_CPU_X86_DHYANA = 36
+UC_CPU_X86_EPYC_ROME = 37
+
 # X86 registers
 
 UC_X86_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb
index 4c98dd0f..ce051599 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb
@@ -2,6 +2,11 @@
 
 module UnicornEngine
 
+	UC_CPU_AARCH64_A57 = 0
+	UC_CPU_AARCH64_A53 = 1
+	UC_CPU_AARCH64_A72 = 2
+	UC_CPU_AARCH64_MAX = 3
+
 # ARM64 registers
 
 	UC_ARM64_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb
index 1d908787..66ad11bf 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb
@@ -2,6 +2,40 @@
 
 module UnicornEngine
 
+	UC_CPU_ARM_926 = 0
+	UC_CPU_ARM_946 = 1
+	UC_CPU_ARM_1026 = 2
+	UC_CPU_ARM_1136_R2 = 3
+	UC_CPU_ARM_1136 = 4
+	UC_CPU_ARM_1176 = 5
+	UC_CPU_ARM_11MPCORE = 6
+	UC_CPU_ARM_CORTEX_M0 = 7
+	UC_CPU_ARM_CORTEX_M3 = 8
+	UC_CPU_ARM_CORTEX_M4 = 9
+	UC_CPU_ARM_CORTEX_M7 = 10
+	UC_CPU_ARM_CORTEX_M33 = 11
+	UC_CPU_ARM_CORTEX_R5 = 12
+	UC_CPU_ARM_CORTEX_R5F = 13
+	UC_CPU_ARM_CORTEX_A8 = 14
+	UC_CPU_ARM_CORTEX_A9 = 15
+	UC_CPU_ARM_CORTEX_A7 = 16
+	UC_CPU_ARM_CORTEX_A15 = 17
+	UC_CPU_ARM_TI925T = 18
+	UC_CPU_ARM_SA1100 = 19
+	UC_CPU_ARM_SA1110 = 20
+	UC_CPU_ARM_PXA250 = 21
+	UC_CPU_ARM_PXA255 = 22
+	UC_CPU_ARM_PXA260 = 23
+	UC_CPU_ARM_PXA261 = 24
+	UC_CPU_ARM_PXA262 = 25
+	UC_CPU_ARM_PXA270A0 = 26
+	UC_CPU_ARM_PXA270A1 = 27
+	UC_CPU_ARM_PXA270B0 = 28
+	UC_CPU_ARM_PXA270B1 = 29
+	UC_CPU_ARM_PXA270C0 = 30
+	UC_CPU_ARM_PXA270C5 = 31
+	UC_CPU_ARM_MAX = 32
+
 # ARM registers
 
 	UC_ARM_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb
index dc641535..4a473674 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb
@@ -2,6 +2,16 @@
 
 module UnicornEngine
 
+	UC_CPU_M5206_CPU = 0
+	UC_CPU_M68000_CPU = 1
+	UC_CPU_M68020_CPU = 2
+	UC_CPU_M68030_CPU = 3
+	UC_CPU_M68040_CPU = 4
+	UC_CPU_M68060_CPU = 5
+	UC_CPU_M5208_CPU = 6
+	UC_CPU_CFV4E_CPU = 7
+	UC_CPU_ANY_CPU = 8
+
 # M68K registers
 
 	UC_M68K_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
index f9fe86bd..13920c06 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb
@@ -2,6 +2,36 @@
 
 module UnicornEngine
 
+	UC_CPU_MIPS_4KC = 0
+	UC_CPU_MIPS_4KM = 1
+	UC_CPU_MIPS_4KECR1 = 2
+	UC_CPU_MIPS_4KEMR1 = 3
+	UC_CPU_MIPS_4KEC = 4
+	UC_CPU_MIPS_4KEM = 5
+	UC_CPU_MIPS_24KC = 6
+	UC_CPU_MIPS_24KEC = 7
+	UC_CPU_MIPS_24KF = 8
+	UC_CPU_MIPS_34KF = 9
+	UC_CPU_MIPS_74KF = 10
+	UC_CPU_MIPS_M14K = 11
+	UC_CPU_MIPS_M14KC = 12
+	UC_CPU_MIPS_P5600 = 13
+	UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+	UC_CPU_MIPS_I7200 = 15
+	UC_CPU_MIPS_R4000 = 16
+	UC_CPU_MIPS_VR5432 = 17
+	UC_CPU_MIPS_5KC = 18
+	UC_CPU_MIPS_5KF = 19
+	UC_CPU_MIPS_20KC = 20
+	UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+	UC_CPU_MIPS_5KEC = 22
+	UC_CPU_MIPS_5KEF = 23
+	UC_CPU_MIPS_I6400 = 24
+	UC_CPU_MIPS_I6500 = 25
+	UC_CPU_MIPS_LOONGSON_2E = 26
+	UC_CPU_MIPS_LOONGSON_2F = 27
+	UC_CPU_MIPS_MIPS64DSPR2 = 28
+
 # MIPS registers
 
 	UC_MIPS_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb
index e8f33330..94748d5c 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb
@@ -2,6 +2,307 @@
 
 module UnicornEngine
 
+	UC_CPU_PPC_401A1 = 0
+	UC_CPU_PPC_401B2 = 1
+	UC_CPU_PPC_401C2 = 2
+	UC_CPU_PPC_401D2 = 3
+	UC_CPU_PPC_401E2 = 4
+	UC_CPU_PPC_401F2 = 5
+	UC_CPU_PPC_401G2 = 6
+	UC_CPU_PPC_COBRA = 7
+	UC_CPU_PPC_403GA = 8
+	UC_CPU_PPC_403GB = 9
+	UC_CPU_PPC_403GC = 10
+	UC_CPU_PPC_403GCX = 11
+	UC_CPU_PPC_405D2 = 12
+	UC_CPU_PPC_405D4 = 13
+	UC_CPU_PPC_405CRA = 14
+	UC_CPU_PPC_405CRB = 15
+	UC_CPU_PPC_405CRC = 16
+	UC_CPU_PPC_405EP = 17
+	UC_CPU_PPC_405EZ = 18
+	UC_CPU_PPC_405GPA = 19
+	UC_CPU_PPC_405GPB = 20
+	UC_CPU_PPC_405GPC = 21
+	UC_CPU_PPC_405GPD = 22
+	UC_CPU_PPC_405GPR = 23
+	UC_CPU_PPC_405LP = 24
+	UC_CPU_PPC_NPE405H = 25
+	UC_CPU_PPC_NPE405H2 = 26
+	UC_CPU_PPC_NPE405L = 27
+	UC_CPU_PPC_NPE4GS3 = 28
+	UC_CPU_PPC_STB03 = 29
+	UC_CPU_PPC_STB04 = 30
+	UC_CPU_PPC_STB25 = 31
+	UC_CPU_PPC_X2VP4 = 32
+	UC_CPU_PPC_440_XILINX = 33
+	UC_CPU_PPC_440EPA = 34
+	UC_CPU_PPC_440EPB = 35
+	UC_CPU_PPC_440GPB = 36
+	UC_CPU_PPC_440GPC = 37
+	UC_CPU_PPC_440GRX = 38
+	UC_CPU_PPC_440GXA = 39
+	UC_CPU_PPC_440GXB = 40
+	UC_CPU_PPC_440GXC = 41
+	UC_CPU_PPC_440GXF = 42
+	UC_CPU_PPC_440SP = 43
+	UC_CPU_PPC_440SP2 = 44
+	UC_CPU_PPC_440SPE = 45
+	UC_CPU_PPC_460EXB = 46
+	UC_CPU_PPC_MPC5XX = 47
+	UC_CPU_PPC_MPC8XX = 48
+	UC_CPU_PPC_G2 = 49
+	UC_CPU_PPC_G2H4 = 50
+	UC_CPU_PPC_G2GP = 51
+	UC_CPU_PPC_G2LS = 52
+	UC_CPU_PPC_MPC603 = 53
+	UC_CPU_PPC_G2_HIP3 = 54
+	UC_CPU_PPC_G2_HIP4 = 55
+	UC_CPU_PPC_G2LE = 56
+	UC_CPU_PPC_G2LEGP = 57
+	UC_CPU_PPC_G2LELS = 58
+	UC_CPU_PPC_G2LEGP1 = 59
+	UC_CPU_PPC_G2LEGP3 = 60
+	UC_CPU_PPC_E200Z5 = 61
+	UC_CPU_PPC_E200Z6 = 62
+	UC_CPU_PPC_E300C1 = 63
+	UC_CPU_PPC_E300C2 = 64
+	UC_CPU_PPC_E300C3 = 65
+	UC_CPU_PPC_E300C4 = 66
+	UC_CPU_PPC_E500V1_V10 = 67
+	UC_CPU_PPC_E500V1_V20 = 68
+	UC_CPU_PPC_E500V2_V10 = 69
+	UC_CPU_PPC_E500V2_V11 = 70
+	UC_CPU_PPC_E500V2_V20 = 71
+	UC_CPU_PPC_E500V2_V21 = 72
+	UC_CPU_PPC_E500V2_V22 = 73
+	UC_CPU_PPC_E500V2_V30 = 74
+	UC_CPU_PPC_E500MC = 75
+	UC_CPU_PPC_E5500 = 76
+	UC_CPU_PPC_E6500 = 77
+	UC_CPU_PPC_E600 = 78
+	UC_CPU_PPC_601_V0 = 79
+	UC_CPU_PPC_601_V1 = 80
+	UC_CPU_PPC_601_V2 = 81
+	UC_CPU_PPC_602 = 82
+	UC_CPU_PPC_603 = 83
+	UC_CPU_PPC_603E_V11 = 84
+	UC_CPU_PPC_603E_V12 = 85
+	UC_CPU_PPC_603E_V13 = 86
+	UC_CPU_PPC_603E_V14 = 87
+	UC_CPU_PPC_603E_V22 = 88
+	UC_CPU_PPC_603E_V3 = 89
+	UC_CPU_PPC_603E_V4 = 90
+	UC_CPU_PPC_603E_V41 = 91
+	UC_CPU_PPC_603E7T = 92
+	UC_CPU_PPC_603E7V = 93
+	UC_CPU_PPC_603E7V1 = 94
+	UC_CPU_PPC_603E7V2 = 95
+	UC_CPU_PPC_603E7 = 96
+	UC_CPU_PPC_603P = 97
+	UC_CPU_PPC_604 = 98
+	UC_CPU_PPC_604E_V10 = 99
+	UC_CPU_PPC_604E_V22 = 100
+	UC_CPU_PPC_604E_V24 = 101
+	UC_CPU_PPC_604R = 102
+	UC_CPU_PPC_7X0_V10 = 103
+	UC_CPU_PPC_7X0_V20 = 104
+	UC_CPU_PPC_7X0_V21 = 105
+	UC_CPU_PPC_7X0_V22 = 106
+	UC_CPU_PPC_7X0_V30 = 107
+	UC_CPU_PPC_7X0_V31 = 108
+	UC_CPU_PPC_740E = 109
+	UC_CPU_PPC_750E = 110
+	UC_CPU_PPC_7X0P = 111
+	UC_CPU_PPC_750CL_V10 = 112
+	UC_CPU_PPC_750CL_V20 = 113
+	UC_CPU_PPC_750CX_V10 = 114
+	UC_CPU_PPC_750CX_V20 = 115
+	UC_CPU_PPC_750CX_V21 = 116
+	UC_CPU_PPC_750CX_V22 = 117
+	UC_CPU_PPC_750CXE_V21 = 118
+	UC_CPU_PPC_750CXE_V22 = 119
+	UC_CPU_PPC_750CXE_V23 = 120
+	UC_CPU_PPC_750CXE_V24 = 121
+	UC_CPU_PPC_750CXE_V24B = 122
+	UC_CPU_PPC_750CXE_V30 = 123
+	UC_CPU_PPC_750CXE_V31 = 124
+	UC_CPU_PPC_750CXE_V31B = 125
+	UC_CPU_PPC_750CXR = 126
+	UC_CPU_PPC_750FL = 127
+	UC_CPU_PPC_750FX_V10 = 128
+	UC_CPU_PPC_750FX_V20 = 129
+	UC_CPU_PPC_750FX_V21 = 130
+	UC_CPU_PPC_750FX_V22 = 131
+	UC_CPU_PPC_750FX_V23 = 132
+	UC_CPU_PPC_750GL = 133
+	UC_CPU_PPC_750GX_V10 = 134
+	UC_CPU_PPC_750GX_V11 = 135
+	UC_CPU_PPC_750GX_V12 = 136
+	UC_CPU_PPC_750L_V20 = 137
+	UC_CPU_PPC_750L_V21 = 138
+	UC_CPU_PPC_750L_V22 = 139
+	UC_CPU_PPC_750L_V30 = 140
+	UC_CPU_PPC_750L_V32 = 141
+	UC_CPU_PPC_7X5_V10 = 142
+	UC_CPU_PPC_7X5_V11 = 143
+	UC_CPU_PPC_7X5_V20 = 144
+	UC_CPU_PPC_7X5_V21 = 145
+	UC_CPU_PPC_7X5_V22 = 146
+	UC_CPU_PPC_7X5_V23 = 147
+	UC_CPU_PPC_7X5_V24 = 148
+	UC_CPU_PPC_7X5_V25 = 149
+	UC_CPU_PPC_7X5_V26 = 150
+	UC_CPU_PPC_7X5_V27 = 151
+	UC_CPU_PPC_7X5_V28 = 152
+	UC_CPU_PPC_7400_V10 = 153
+	UC_CPU_PPC_7400_V11 = 154
+	UC_CPU_PPC_7400_V20 = 155
+	UC_CPU_PPC_7400_V21 = 156
+	UC_CPU_PPC_7400_V22 = 157
+	UC_CPU_PPC_7400_V26 = 158
+	UC_CPU_PPC_7400_V27 = 159
+	UC_CPU_PPC_7400_V28 = 160
+	UC_CPU_PPC_7400_V29 = 161
+	UC_CPU_PPC_7410_V10 = 162
+	UC_CPU_PPC_7410_V11 = 163
+	UC_CPU_PPC_7410_V12 = 164
+	UC_CPU_PPC_7410_V13 = 165
+	UC_CPU_PPC_7410_V14 = 166
+	UC_CPU_PPC_7448_V10 = 167
+	UC_CPU_PPC_7448_V11 = 168
+	UC_CPU_PPC_7448_V20 = 169
+	UC_CPU_PPC_7448_V21 = 170
+	UC_CPU_PPC_7450_V10 = 171
+	UC_CPU_PPC_7450_V11 = 172
+	UC_CPU_PPC_7450_V12 = 173
+	UC_CPU_PPC_7450_V20 = 174
+	UC_CPU_PPC_7450_V21 = 175
+	UC_CPU_PPC_74X1_V23 = 176
+	UC_CPU_PPC_74X1_V210 = 177
+	UC_CPU_PPC_74X5_V10 = 178
+	UC_CPU_PPC_74X5_V21 = 179
+	UC_CPU_PPC_74X5_V32 = 180
+	UC_CPU_PPC_74X5_V33 = 181
+	UC_CPU_PPC_74X5_V34 = 182
+	UC_CPU_PPC_74X7_V10 = 183
+	UC_CPU_PPC_74X7_V11 = 184
+	UC_CPU_PPC_74X7_V12 = 185
+	UC_CPU_PPC_74X7A_V10 = 186
+	UC_CPU_PPC_74X7A_V11 = 187
+	UC_CPU_PPC_74X7A_V12 = 188
+	UC_CPU_PPC_IOP480 = 1
+	UC_CPU_PPC_X2VP20 = 42
+	UC_CPU_PPC_440GRA = 35
+	UC_CPU_PPC_440EPX = 38
+	UC_CPU_PPC_MPC5200_V10 = 59
+	UC_CPU_PPC_MPC5200_V11 = 59
+	UC_CPU_PPC_MPC5200_V12 = 59
+	UC_CPU_PPC_MPC5200B_V20 = 59
+	UC_CPU_PPC_MPC5200B_V21 = 59
+	UC_CPU_PPC_MPC834X = 63
+	UC_CPU_PPC_MPC837X = 66
+	UC_CPU_PPC_E500 = 73
+	UC_CPU_PPC_MPC8533_V10 = 72
+	UC_CPU_PPC_MPC8533_V11 = 73
+	UC_CPU_PPC_MPC8533E_V10 = 72
+	UC_CPU_PPC_MPC8533E_V11 = 73
+	UC_CPU_PPC_MPC8540_V10 = 67
+	UC_CPU_PPC_MPC8540_V20 = 68
+	UC_CPU_PPC_MPC8540_V21 = 68
+	UC_CPU_PPC_MPC8541_V10 = 68
+	UC_CPU_PPC_MPC8541_V11 = 68
+	UC_CPU_PPC_MPC8541E_V10 = 68
+	UC_CPU_PPC_MPC8541E_V11 = 68
+	UC_CPU_PPC_MPC8543_V10 = 69
+	UC_CPU_PPC_MPC8543_V11 = 70
+	UC_CPU_PPC_MPC8543_V20 = 71
+	UC_CPU_PPC_MPC8543_V21 = 72
+	UC_CPU_PPC_MPC8543E_V10 = 69
+	UC_CPU_PPC_MPC8543E_V11 = 70
+	UC_CPU_PPC_MPC8543E_V20 = 71
+	UC_CPU_PPC_MPC8543E_V21 = 72
+	UC_CPU_PPC_MPC8544_V10 = 72
+	UC_CPU_PPC_MPC8544_V11 = 73
+	UC_CPU_PPC_MPC8544E_V11 = 73
+	UC_CPU_PPC_MPC8544E_V10 = 72
+	UC_CPU_PPC_MPC8545_V10 = 69
+	UC_CPU_PPC_MPC8545_V20 = 71
+	UC_CPU_PPC_MPC8545_V21 = 72
+	UC_CPU_PPC_MPC8545E_V10 = 69
+	UC_CPU_PPC_MPC8545E_V20 = 71
+	UC_CPU_PPC_MPC8545E_V21 = 72
+	UC_CPU_PPC_MPC8547E_V10 = 69
+	UC_CPU_PPC_MPC8547E_V20 = 71
+	UC_CPU_PPC_MPC8547E_V21 = 72
+	UC_CPU_PPC_MPC8548_V10 = 69
+	UC_CPU_PPC_MPC8548_V11 = 70
+	UC_CPU_PPC_MPC8548_V20 = 71
+	UC_CPU_PPC_MPC8548_V21 = 72
+	UC_CPU_PPC_MPC8548E_V10 = 69
+	UC_CPU_PPC_MPC8548E_V11 = 70
+	UC_CPU_PPC_MPC8548E_V20 = 71
+	UC_CPU_PPC_MPC8548E_V21 = 72
+	UC_CPU_PPC_MPC8555_V10 = 69
+	UC_CPU_PPC_MPC8555_V11 = 70
+	UC_CPU_PPC_MPC8555E_V10 = 69
+	UC_CPU_PPC_MPC8555E_V11 = 70
+	UC_CPU_PPC_MPC8560_V10 = 69
+	UC_CPU_PPC_MPC8560_V20 = 71
+	UC_CPU_PPC_MPC8560_V21 = 72
+	UC_CPU_PPC_MPC8567 = 73
+	UC_CPU_PPC_MPC8567E = 73
+	UC_CPU_PPC_MPC8568 = 73
+	UC_CPU_PPC_MPC8568E = 73
+	UC_CPU_PPC_MPC8572 = 74
+	UC_CPU_PPC_MPC8572E = 74
+	UC_CPU_PPC_MPC8610 = 78
+	UC_CPU_PPC_MPC8641 = 78
+	UC_CPU_PPC_MPC8641D = 78
+
+	UC_CPU_PPC64_620 = 0
+	UC_CPU_PPC64_630 = 1
+	UC_CPU_PPC64_631 = 2
+	UC_CPU_PPC64_POWER4 = 3
+	UC_CPU_PPC64_POWER4P = 4
+	UC_CPU_PPC64_POWER5 = 5
+	UC_CPU_PPC64_POWER5P_V21 = 6
+	UC_CPU_PPC64_POWER6 = 7
+	UC_CPU_PPC64_POWER_SERVER_MASK = 8
+	UC_CPU_PPC64_POWER7_BASE = 9
+	UC_CPU_PPC64_POWER7_V23 = 10
+	UC_CPU_PPC64_POWER7P_BASE = 11
+	UC_CPU_PPC64_POWER7P_V21 = 12
+	UC_CPU_PPC64_POWER8E_BASE = 13
+	UC_CPU_PPC64_POWER8E_V21 = 14
+	UC_CPU_PPC64_POWER8_BASE = 15
+	UC_CPU_PPC64_POWER8_V20 = 16
+	UC_CPU_PPC64_POWER8NVL_BASE = 17
+	UC_CPU_PPC64_POWER8NVL_V10 = 18
+	UC_CPU_PPC64_POWER9_BASE = 19
+	UC_CPU_PPC64_POWER9_DD1 = 20
+	UC_CPU_PPC64_POWER9_DD20 = 21
+	UC_CPU_PPC64_POWER10_BASE = 22
+	UC_CPU_PPC64_POWER10_DD1 = 23
+	UC_CPU_PPC64_970_V22 = 24
+	UC_CPU_PPC64_970FX_V10 = 25
+	UC_CPU_PPC64_970FX_V20 = 26
+	UC_CPU_PPC64_970FX_V21 = 27
+	UC_CPU_PPC64_970FX_V30 = 28
+	UC_CPU_PPC64_970FX_V31 = 29
+	UC_CPU_PPC64_970MP_V10 = 30
+	UC_CPU_PPC64_970MP_V11 = 31
+	UC_CPU_PPC64_CELL_V10 = 32
+	UC_CPU_PPC64_CELL_V20 = 33
+	UC_CPU_PPC64_CELL_V30 = 34
+	UC_CPU_PPC64_CELL_V31 = 35
+	UC_CPU_PPC64_RS64 = 36
+	UC_CPU_PPC64_RS64II = 37
+	UC_CPU_PPC64_RS64III = 38
+	UC_CPU_PPC64_RS64IV = 39
+	UC_CPU_PPC64_CELL_V32 = 35
+	UC_CPU_PPC64_CELL = 35
+
 # PPC registers
 
 	UC_PPC_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
index 2122099d..5eb5cd85 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
@@ -2,6 +2,16 @@
 
 module UnicornEngine
 
+	UC_CPU_RISCV32_ANY = 0
+	UC_CPU_RISCV32_BASE32 = 1
+	UC_CPU_RISCV32_SIFIVE_E31 = 2
+	UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+	UC_CPU_RISCV64_ANY = 0
+	UC_CPU_RISCV64_BASE64 = 1
+	UC_CPU_RISCV64_SIFIVE_E51 = 2
+	UC_CPU_RISCV64_SIFIVE_U54 = 3
+
 # RISCV registers
 
 	UC_RISCV_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb
index b5c42470..dbf3f938 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb
@@ -2,6 +2,38 @@
 
 module UnicornEngine
 
+	UC_CPU_SPARC_FUJITSU_MB86904 = 0
+	UC_CPU_SPARC_FUJITSU_MB86907 = 1
+	UC_CPU_SPARC_TI_MICROSPARC_I = 2
+	UC_CPU_SPARC_TI_MICROSPARC_II = 3
+	UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+	UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+	UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+	UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+	UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+	UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+	UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+	UC_CPU_SPARC_LEON2 = 11
+	UC_CPU_SPARC_LEON3 = 12
+
+	UC_CPU_SPARC64_FUJITSU = 0
+	UC_CPU_SPARC64_FUJITSU_III = 1
+	UC_CPU_SPARC64_FUJITSU_IV = 2
+	UC_CPU_SPARC64_FUJITSU_V = 3
+	UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+	UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+	UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+	UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+	UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+	UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+	UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+	UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+	UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 # SPARC registers
 
 	UC_SPARC_REG_INVALID = 0
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
index a09f3e82..b179d3eb 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
@@ -107,6 +107,22 @@ module UnicornEngine
 	UC_QUERY_ARCH = 3
 	UC_QUERY_TIMEOUT = 4
 
+	UC_CTL_IO_NONE = 0
+	UC_CTL_IO_WRITE = 1
+	UC_CTL_IO_READ = 2
+	UC_CTL_IO_READ_WRITE = 3
+
+	UC_CTL_UC_MODE = 0
+	UC_CTL_UC_PAGE_SIZE = 1
+	UC_CTL_UC_ARCH = 2
+	UC_CTL_UC_TIMEOUT = 3
+	UC_CTL_UC_EXITS_CNT = 4
+	UC_CTL_UC_EXITS = 5
+	UC_CTL_CPU_MODEL = 6
+	UC_CTL_TB_EDGE = 7
+	UC_CTL_TB_REQUEST_CACHE = 8
+	UC_CTL_TB_REMOVE_CACHE = 9
+
 	UC_PROT_NONE = 0
 	UC_PROT_READ = 1
 	UC_PROT_WRITE = 2
diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb
index 49ef2549..6fae393c 100644
--- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb
+++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb
@@ -2,6 +2,45 @@
 
 module UnicornEngine
 
+	UC_CPU_X86_QEMU64 = 0
+	UC_CPU_X86_PHENOM = 1
+	UC_CPU_X86_CORE2DUO = 2
+	UC_CPU_X86_KVM64 = 3
+	UC_CPU_X86_QEMU32 = 4
+	UC_CPU_X86_KVM32 = 5
+	UC_CPU_X86_COREDUO = 6
+	UC_CPU_X86_486 = 7
+	UC_CPU_X86_PENTIUM = 8
+	UC_CPU_X86_PENTIUM2 = 9
+	UC_CPU_X86_PENTIUM3 = 10
+	UC_CPU_X86_ATHLON = 11
+	UC_CPU_X86_N270 = 12
+	UC_CPU_X86_CONROE = 13
+	UC_CPU_X86_PENRYN = 14
+	UC_CPU_X86_NEHALEM = 15
+	UC_CPU_X86_WESTMERE = 16
+	UC_CPU_X86_SANDYBRIDGE = 17
+	UC_CPU_X86_IVYBRIDGE = 18
+	UC_CPU_X86_HASWELL = 19
+	UC_CPU_X86_BROADWELL = 20
+	UC_CPU_X86_SKYLAKE_CLIENT = 21
+	UC_CPU_X86_SKYLAKE_SERVER = 22
+	UC_CPU_X86_CASCADELAKE_SERVER = 23
+	UC_CPU_X86_COOPERLAKE = 24
+	UC_CPU_X86_ICELAKE_CLIENT = 25
+	UC_CPU_X86_ICELAKE_SERVER = 26
+	UC_CPU_X86_DENVERTON = 27
+	UC_CPU_X86_SNOWRIDGE = 28
+	UC_CPU_X86_KNIGHTSMILL = 29
+	UC_CPU_X86_OPTERON_G1 = 30
+	UC_CPU_X86_OPTERON_G2 = 31
+	UC_CPU_X86_OPTERON_G3 = 32
+	UC_CPU_X86_OPTERON_G4 = 33
+	UC_CPU_X86_OPTERON_G5 = 34
+	UC_CPU_X86_EPYC = 35
+	UC_CPU_X86_DHYANA = 36
+	UC_CPU_X86_EPYC_ROME = 37
+
 # X86 registers
 
 	UC_X86_REG_INVALID = 0
diff --git a/include/unicorn/arm.h b/include/unicorn/arm.h
index 5bd72d63..d9cf4949 100644
--- a/include/unicorn/arm.h
+++ b/include/unicorn/arm.h
@@ -15,6 +15,42 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_arm {
+    UC_CPU_ARM_926 = 0,
+    UC_CPU_ARM_946,
+    UC_CPU_ARM_1026,
+    UC_CPU_ARM_1136_R2,
+    UC_CPU_ARM_1136,
+    UC_CPU_ARM_1176,
+    UC_CPU_ARM_11MPCORE,
+    UC_CPU_ARM_CORTEX_M0,
+    UC_CPU_ARM_CORTEX_M3,
+    UC_CPU_ARM_CORTEX_M4,
+    UC_CPU_ARM_CORTEX_M7,
+    UC_CPU_ARM_CORTEX_M33,
+    UC_CPU_ARM_CORTEX_R5,
+    UC_CPU_ARM_CORTEX_R5F,
+    UC_CPU_ARM_CORTEX_A8,
+    UC_CPU_ARM_CORTEX_A9,
+    UC_CPU_ARM_CORTEX_A7,
+    UC_CPU_ARM_CORTEX_A15,
+    UC_CPU_ARM_TI925T,
+    UC_CPU_ARM_SA1100,
+    UC_CPU_ARM_SA1110,
+    UC_CPU_ARM_PXA250,
+    UC_CPU_ARM_PXA255,
+    UC_CPU_ARM_PXA260,
+    UC_CPU_ARM_PXA261,
+    UC_CPU_ARM_PXA262,
+    UC_CPU_ARM_PXA270A0,
+    UC_CPU_ARM_PXA270A1,
+    UC_CPU_ARM_PXA270B0,
+    UC_CPU_ARM_PXA270B1,
+    UC_CPU_ARM_PXA270C0,
+    UC_CPU_ARM_PXA270C5,
+    UC_CPU_ARM_MAX
+} uc_cpu_arm;
+
 //> ARM registers
 typedef enum uc_arm_reg {
     UC_ARM_REG_INVALID = 0,
diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h
index 256b2a50..5cbd6229 100644
--- a/include/unicorn/arm64.h
+++ b/include/unicorn/arm64.h
@@ -15,6 +15,13 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_aarch64 {
+    UC_CPU_AARCH64_A57 = 0,
+    UC_CPU_AARCH64_A53,
+    UC_CPU_AARCH64_A72,
+    UC_CPU_AARCH64_MAX
+} uc_cpu_aarch64;
+
 //> ARM64 registers
 typedef enum uc_arm64_reg {
     UC_ARM64_REG_INVALID = 0,
diff --git a/include/unicorn/m68k.h b/include/unicorn/m68k.h
index 01cb0af1..27ea64df 100644
--- a/include/unicorn/m68k.h
+++ b/include/unicorn/m68k.h
@@ -15,6 +15,18 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_m68k {
+    UC_CPU_M5206_CPU = 0,
+    UC_CPU_M68000_CPU,
+    UC_CPU_M68020_CPU,
+    UC_CPU_M68030_CPU,
+    UC_CPU_M68040_CPU,
+    UC_CPU_M68060_CPU,
+    UC_CPU_M5208_CPU,
+    UC_CPU_CFV4E_CPU,
+    UC_CPU_ANY_CPU,
+} uc_cpu_m68k;
+
 //> M68K registers
 typedef enum uc_m68k_reg {
     UC_M68K_REG_INVALID = 0,
diff --git a/include/unicorn/mips.h b/include/unicorn/mips.h
index b8d203f9..977ee534 100644
--- a/include/unicorn/mips.h
+++ b/include/unicorn/mips.h
@@ -19,6 +19,38 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_mips {
+    UC_CPU_MIPS_4KC = 0,
+    UC_CPU_MIPS_4KM,
+    UC_CPU_MIPS_4KECR1,
+    UC_CPU_MIPS_4KEMR1,
+    UC_CPU_MIPS_4KEC,
+    UC_CPU_MIPS_4KEM,
+    UC_CPU_MIPS_24KC,
+    UC_CPU_MIPS_24KEC,
+    UC_CPU_MIPS_24KF,
+    UC_CPU_MIPS_34KF,
+    UC_CPU_MIPS_74KF,
+    UC_CPU_MIPS_M14K,
+    UC_CPU_MIPS_M14KC,
+    UC_CPU_MIPS_P5600,
+    UC_CPU_MIPS_MIPS32R6_GENERIC,
+    UC_CPU_MIPS_I7200,
+    UC_CPU_MIPS_R4000,
+    UC_CPU_MIPS_VR5432,
+    UC_CPU_MIPS_5KC,
+    UC_CPU_MIPS_5KF,
+    UC_CPU_MIPS_20KC,
+    UC_CPU_MIPS_MIPS64R2_GENERIC,
+    UC_CPU_MIPS_5KEC,
+    UC_CPU_MIPS_5KEF,
+    UC_CPU_MIPS_I6400,
+    UC_CPU_MIPS_I6500,
+    UC_CPU_MIPS_LOONGSON_2E,
+    UC_CPU_MIPS_LOONGSON_2F,
+    UC_CPU_MIPS_MIPS64DSPR2
+} uc_cpu_mips;
+
 //> MIPS registers
 typedef enum UC_MIPS_REG {
     UC_MIPS_REG_INVALID = 0,
diff --git a/include/unicorn/ppc.h b/include/unicorn/ppc.h
index a6181834..9d09a990 100644
--- a/include/unicorn/ppc.h
+++ b/include/unicorn/ppc.h
@@ -15,6 +15,311 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_ppc {
+    UC_CPU_PPC_401A1 = 0,
+    UC_CPU_PPC_401B2,
+    UC_CPU_PPC_401C2,
+    UC_CPU_PPC_401D2,
+    UC_CPU_PPC_401E2,
+    UC_CPU_PPC_401F2,
+    UC_CPU_PPC_401G2,
+    UC_CPU_PPC_COBRA,
+    UC_CPU_PPC_403GA,
+    UC_CPU_PPC_403GB,
+    UC_CPU_PPC_403GC,
+    UC_CPU_PPC_403GCX,
+    UC_CPU_PPC_405D2,
+    UC_CPU_PPC_405D4,
+    UC_CPU_PPC_405CRA,
+    UC_CPU_PPC_405CRB,
+    UC_CPU_PPC_405CRC,
+    UC_CPU_PPC_405EP,
+    UC_CPU_PPC_405EZ,
+    UC_CPU_PPC_405GPA,
+    UC_CPU_PPC_405GPB,
+    UC_CPU_PPC_405GPC,
+    UC_CPU_PPC_405GPD,
+    UC_CPU_PPC_405GPR,
+    UC_CPU_PPC_405LP,
+    UC_CPU_PPC_NPE405H,
+    UC_CPU_PPC_NPE405H2,
+    UC_CPU_PPC_NPE405L,
+    UC_CPU_PPC_NPE4GS3,
+    UC_CPU_PPC_STB03,
+    UC_CPU_PPC_STB04,
+    UC_CPU_PPC_STB25,
+    UC_CPU_PPC_X2VP4,
+    UC_CPU_PPC_440_XILINX,
+    UC_CPU_PPC_440EPA,
+    UC_CPU_PPC_440EPB,
+    UC_CPU_PPC_440GPB,
+    UC_CPU_PPC_440GPC,
+    UC_CPU_PPC_440GRX,
+    UC_CPU_PPC_440GXA,
+    UC_CPU_PPC_440GXB,
+    UC_CPU_PPC_440GXC,
+    UC_CPU_PPC_440GXF,
+    UC_CPU_PPC_440SP,
+    UC_CPU_PPC_440SP2,
+    UC_CPU_PPC_440SPE,
+    UC_CPU_PPC_460EXB,
+    UC_CPU_PPC_MPC5XX,
+    UC_CPU_PPC_MPC8XX,
+    UC_CPU_PPC_G2,
+    UC_CPU_PPC_G2H4,
+    UC_CPU_PPC_G2GP,
+    UC_CPU_PPC_G2LS,
+    UC_CPU_PPC_MPC603,
+    UC_CPU_PPC_G2_HIP3,
+    UC_CPU_PPC_G2_HIP4,
+    UC_CPU_PPC_G2LE,
+    UC_CPU_PPC_G2LEGP,
+    UC_CPU_PPC_G2LELS,
+    UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_G2LEGP3,
+    UC_CPU_PPC_E200Z5,
+    UC_CPU_PPC_E200Z6,
+    UC_CPU_PPC_E300C1,
+    UC_CPU_PPC_E300C2,
+    UC_CPU_PPC_E300C3,
+    UC_CPU_PPC_E300C4,
+    UC_CPU_PPC_E500V1_V10,
+    UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_E500MC,
+    UC_CPU_PPC_E5500,
+    UC_CPU_PPC_E6500,
+    UC_CPU_PPC_E600,
+    UC_CPU_PPC_601_V0,
+    UC_CPU_PPC_601_V1,
+    UC_CPU_PPC_601_V2,
+    UC_CPU_PPC_602,
+    UC_CPU_PPC_603,
+    UC_CPU_PPC_603E_V11,
+    UC_CPU_PPC_603E_V12,
+    UC_CPU_PPC_603E_V13,
+    UC_CPU_PPC_603E_V14,
+    UC_CPU_PPC_603E_V22,
+    UC_CPU_PPC_603E_V3,
+    UC_CPU_PPC_603E_V4,
+    UC_CPU_PPC_603E_V41,
+    UC_CPU_PPC_603E7T,
+    UC_CPU_PPC_603E7V,
+    UC_CPU_PPC_603E7V1,
+    UC_CPU_PPC_603E7V2,
+    UC_CPU_PPC_603E7,
+    UC_CPU_PPC_603P,
+    UC_CPU_PPC_604,
+    UC_CPU_PPC_604E_V10,
+    UC_CPU_PPC_604E_V22,
+    UC_CPU_PPC_604E_V24,
+    UC_CPU_PPC_604R,
+    UC_CPU_PPC_7X0_V10,
+    UC_CPU_PPC_7X0_V20,
+    UC_CPU_PPC_7X0_V21,
+    UC_CPU_PPC_7X0_V22,
+    UC_CPU_PPC_7X0_V30,
+    UC_CPU_PPC_7X0_V31,
+    UC_CPU_PPC_740E,
+    UC_CPU_PPC_750E,
+    UC_CPU_PPC_7X0P,
+    UC_CPU_PPC_750CL_V10,
+    UC_CPU_PPC_750CL_V20,
+    UC_CPU_PPC_750CX_V10,
+    UC_CPU_PPC_750CX_V20,
+    UC_CPU_PPC_750CX_V21,
+    UC_CPU_PPC_750CX_V22,
+    UC_CPU_PPC_750CXE_V21,
+    UC_CPU_PPC_750CXE_V22,
+    UC_CPU_PPC_750CXE_V23,
+    UC_CPU_PPC_750CXE_V24,
+    UC_CPU_PPC_750CXE_V24B,
+    UC_CPU_PPC_750CXE_V30,
+    UC_CPU_PPC_750CXE_V31,
+    UC_CPU_PPC_750CXE_V31B,
+    UC_CPU_PPC_750CXR,
+    UC_CPU_PPC_750FL,
+    UC_CPU_PPC_750FX_V10,
+    UC_CPU_PPC_750FX_V20,
+    UC_CPU_PPC_750FX_V21,
+    UC_CPU_PPC_750FX_V22,
+    UC_CPU_PPC_750FX_V23,
+    UC_CPU_PPC_750GL,
+    UC_CPU_PPC_750GX_V10,
+    UC_CPU_PPC_750GX_V11,
+    UC_CPU_PPC_750GX_V12,
+    UC_CPU_PPC_750L_V20,
+    UC_CPU_PPC_750L_V21,
+    UC_CPU_PPC_750L_V22,
+    UC_CPU_PPC_750L_V30,
+    UC_CPU_PPC_750L_V32,
+    UC_CPU_PPC_7X5_V10,
+    UC_CPU_PPC_7X5_V11,
+    UC_CPU_PPC_7X5_V20,
+    UC_CPU_PPC_7X5_V21,
+    UC_CPU_PPC_7X5_V22,
+    UC_CPU_PPC_7X5_V23,
+    UC_CPU_PPC_7X5_V24,
+    UC_CPU_PPC_7X5_V25,
+    UC_CPU_PPC_7X5_V26,
+    UC_CPU_PPC_7X5_V27,
+    UC_CPU_PPC_7X5_V28,
+    UC_CPU_PPC_7400_V10,
+    UC_CPU_PPC_7400_V11,
+    UC_CPU_PPC_7400_V20,
+    UC_CPU_PPC_7400_V21,
+    UC_CPU_PPC_7400_V22,
+    UC_CPU_PPC_7400_V26,
+    UC_CPU_PPC_7400_V27,
+    UC_CPU_PPC_7400_V28,
+    UC_CPU_PPC_7400_V29,
+    UC_CPU_PPC_7410_V10,
+    UC_CPU_PPC_7410_V11,
+    UC_CPU_PPC_7410_V12,
+    UC_CPU_PPC_7410_V13,
+    UC_CPU_PPC_7410_V14,
+    UC_CPU_PPC_7448_V10,
+    UC_CPU_PPC_7448_V11,
+    UC_CPU_PPC_7448_V20,
+    UC_CPU_PPC_7448_V21,
+    UC_CPU_PPC_7450_V10,
+    UC_CPU_PPC_7450_V11,
+    UC_CPU_PPC_7450_V12,
+    UC_CPU_PPC_7450_V20,
+    UC_CPU_PPC_7450_V21,
+    UC_CPU_PPC_74X1_V23,
+    UC_CPU_PPC_74X1_V210,
+    UC_CPU_PPC_74X5_V10,
+    UC_CPU_PPC_74X5_V21,
+    UC_CPU_PPC_74X5_V32,
+    UC_CPU_PPC_74X5_V33,
+    UC_CPU_PPC_74X5_V34,
+    UC_CPU_PPC_74X7_V10,
+    UC_CPU_PPC_74X7_V11,
+    UC_CPU_PPC_74X7_V12,
+    UC_CPU_PPC_74X7A_V10,
+    UC_CPU_PPC_74X7A_V11,
+    UC_CPU_PPC_74X7A_V12,
+    UC_CPU_PPC_IOP480 = UC_CPU_PPC_401B2,
+    UC_CPU_PPC_X2VP20 = UC_CPU_PPC_440GXF,
+    UC_CPU_PPC_440GRA = UC_CPU_PPC_440EPB,
+    UC_CPU_PPC_440EPX = UC_CPU_PPC_440GRX,
+    UC_CPU_PPC_MPC5200_V10 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200_V11 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200_V12 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200B_V20 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200B_V21 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC834X = UC_CPU_PPC_E300C1,
+    UC_CPU_PPC_MPC837X = UC_CPU_PPC_E300C4,
+    UC_CPU_PPC_E500 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8533_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8533_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8533E_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8533E_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8540_V10 = UC_CPU_PPC_E500V1_V10,
+    UC_CPU_PPC_MPC8540_V20 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8540_V21 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541_V10 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541_V11 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541E_V10 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541E_V11 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8543_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8543_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8543_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8543_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8543E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8543E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8543E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8543E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8544_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8544_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8544E_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8544E_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8545_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8545_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8545_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8545E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8545E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8545E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8547E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8547E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8547E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8548_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8548_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8548_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8548_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8548E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8548E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8548E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8548E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8555_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8555_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8555E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8555E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8560_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8560_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8560_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8567 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8567E = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8568 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8568E = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8572 = UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_MPC8572E = UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_MPC8610 = UC_CPU_PPC_E600,
+    UC_CPU_PPC_MPC8641 = UC_CPU_PPC_E600,
+    UC_CPU_PPC_MPC8641D = UC_CPU_PPC_E600,
+} uc_cpu_ppc;
+
+typedef enum uc_cpu_ppc64 {
+    UC_CPU_PPC64_620 = 0,
+    UC_CPU_PPC64_630,
+    UC_CPU_PPC64_631,
+    UC_CPU_PPC64_POWER4,
+    UC_CPU_PPC64_POWER4P,
+    UC_CPU_PPC64_POWER5,
+    UC_CPU_PPC64_POWER5P_V21,
+    UC_CPU_PPC64_POWER6,
+    UC_CPU_PPC64_POWER_SERVER_MASK,
+    UC_CPU_PPC64_POWER7_BASE,
+    UC_CPU_PPC64_POWER7_V23,
+    UC_CPU_PPC64_POWER7P_BASE,
+    UC_CPU_PPC64_POWER7P_V21,
+    UC_CPU_PPC64_POWER8E_BASE,
+    UC_CPU_PPC64_POWER8E_V21,
+    UC_CPU_PPC64_POWER8_BASE,
+    UC_CPU_PPC64_POWER8_V20,
+    UC_CPU_PPC64_POWER8NVL_BASE,
+    UC_CPU_PPC64_POWER8NVL_V10,
+    UC_CPU_PPC64_POWER9_BASE,
+    UC_CPU_PPC64_POWER9_DD1,
+    UC_CPU_PPC64_POWER9_DD20,
+    UC_CPU_PPC64_POWER10_BASE,
+    UC_CPU_PPC64_POWER10_DD1,
+    UC_CPU_PPC64_970_V22,
+    UC_CPU_PPC64_970FX_V10,
+    UC_CPU_PPC64_970FX_V20,
+    UC_CPU_PPC64_970FX_V21,
+    UC_CPU_PPC64_970FX_V30,
+    UC_CPU_PPC64_970FX_V31,
+    UC_CPU_PPC64_970MP_V10,
+    UC_CPU_PPC64_970MP_V11,
+    UC_CPU_PPC64_CELL_V10,
+    UC_CPU_PPC64_CELL_V20,
+    UC_CPU_PPC64_CELL_V30,
+    UC_CPU_PPC64_CELL_V31,
+    UC_CPU_PPC64_RS64,
+    UC_CPU_PPC64_RS64II,
+    UC_CPU_PPC64_RS64III,
+    UC_CPU_PPC64_RS64IV,
+    UC_CPU_PPC64_CELL_V32 = UC_CPU_PPC64_CELL_V31,
+    UC_CPU_PPC64_CELL = UC_CPU_PPC64_CELL_V32,
+} uc_cpu_ppc64;
+
 //> PPC registers
 typedef enum uc_ppc_reg {
     UC_PPC_REG_INVALID = 0,
diff --git a/include/unicorn/riscv.h b/include/unicorn/riscv.h
index a058ebab..be821d77 100644
--- a/include/unicorn/riscv.h
+++ b/include/unicorn/riscv.h
@@ -15,6 +15,20 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_riscv32 {
+    UC_CPU_RISCV32_ANY = 0,
+    UC_CPU_RISCV32_BASE32,
+    UC_CPU_RISCV32_SIFIVE_E31,
+    UC_CPU_RISCV32_SIFIVE_U34,
+} uc_cpu_riscv32;
+
+typedef enum uc_cpu_riscv64 {
+    UC_CPU_RISCV64_ANY = 0,
+    UC_CPU_RISCV64_BASE64,
+    UC_CPU_RISCV64_SIFIVE_E51,
+    UC_CPU_RISCV64_SIFIVE_U54,
+} uc_cpu_riscv64;
+
 //> RISCV registers
 typedef enum uc_riscv_reg {
     UC_RISCV_REG_INVALID = 0,
diff --git a/include/unicorn/sparc.h b/include/unicorn/sparc.h
index f9ec729d..1bed80ae 100644
--- a/include/unicorn/sparc.h
+++ b/include/unicorn/sparc.h
@@ -19,6 +19,42 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_sparc {
+    UC_CPU_SPARC_FUJITSU_MB86904 = 0,
+    UC_CPU_SPARC_FUJITSU_MB86907,
+    UC_CPU_SPARC_TI_MICROSPARC_I,
+    UC_CPU_SPARC_TI_MICROSPARC_II,
+    UC_CPU_SPARC_TI_MICROSPARC_IIEP,
+    UC_CPU_SPARC_TI_SUPERSPARC_40,
+    UC_CPU_SPARC_TI_SUPERSPARC_50,
+    UC_CPU_SPARC_TI_SUPERSPARC_51,
+    UC_CPU_SPARC_TI_SUPERSPARC_60,
+    UC_CPU_SPARC_TI_SUPERSPARC_61,
+    UC_CPU_SPARC_TI_SUPERSPARC_II,
+    UC_CPU_SPARC_LEON2,
+    UC_CPU_SPARC_LEON3
+} uc_cpu_sparc;
+
+typedef enum uc_cpu_sparc64 {
+    UC_CPU_SPARC64_FUJITSU = 0,
+    UC_CPU_SPARC64_FUJITSU_III,
+    UC_CPU_SPARC64_FUJITSU_IV,
+    UC_CPU_SPARC64_FUJITSU_V,
+    UC_CPU_SPARC64_TI_ULTRASPARC_I,
+    UC_CPU_SPARC64_TI_ULTRASPARC_II,
+    UC_CPU_SPARC64_TI_ULTRASPARC_III,
+    UC_CPU_SPARC64_TI_ULTRASPARC_IIE,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_III,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IIII,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IV,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_T1,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_T2,
+    UC_CPU_SPARC64_NEC_ULTRASPARC_I,
+} uc_cpu_sparc64;
+
 //> SPARC registers
 typedef enum uc_sparc_reg {
     UC_SPARC_REG_INVALID = 0,
diff --git a/include/unicorn/unicorn.h b/include/unicorn/unicorn.h
index 0d217bd4..51dc212c 100644
--- a/include/unicorn/unicorn.h
+++ b/include/unicorn/unicorn.h
@@ -391,6 +391,108 @@ typedef enum uc_query_type {
                       // result = True)
 } uc_query_type;
 
+// The implementation of uc_ctl is like what Linux ioctl does but slightly
+// different.
+//
+// A uc_control_type passed to uc_ctl is constructed as:
+//
+//    R/W       NR       Reserved     Type
+//  [      ] [      ]  [         ] [       ]
+//  31    30 29     26 25       16 15      0
+//
+//  @R/W: Whether the operation is a read or write access.
+//  @NR: Number of arguments.
+//  @Reserved: Should be zero, reserved for future extension.
+//  @Type: Taken from uc_control_type enum.
+//
+// See the helper macros below.
+
+// No input and output arguments.
+#define UC_CTL_IO_NONE (0)
+// The arguments are used for input.
+#define UC_CTL_IO_WRITE (1)
+// The arguments are used for ouput.
+#define UC_CTL_IO_READ (2)
+// The arguments include both input and output arugments.
+#define UC_CTL_IO_READ_WRITE (UC_CTL_IO_WRITE | UC_CTL_IO_READ)
+
+#define UC_CTL(type, nr, rw) ((type) | ((nr) << 26) | ((rw) << 30))
+#define UC_CTL_NONE(type, nr) UC_CTL(type, nr, UC_CTL_IO_NONE)
+#define UC_CTL_READ(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ)
+#define UC_CTL_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_WRITE)
+#define UC_CTL_READ_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ_WRITE)
+
+// All type of controls for uc_ctl API.
+// The controls are organized in a tree level.
+// If a control don't have `Set` or `Get` for @args, it means it's r/o or w/o.
+typedef enum uc_control_type {
+    // Current mode.
+    // Read: @args = (*int)
+    UC_CTL_UC_MODE = 0,
+    // Curent page size.
+    // Write: @args = (int)
+    // Read: @args = (*int)
+    UC_CTL_UC_PAGE_SIZE,
+    // Current arch.
+    // Read: @args = (*int)
+    UC_CTL_UC_ARCH,
+    // Current timeout.
+    // Read: @args = (*uint64_t)
+    UC_CTL_UC_TIMEOUT,
+    // The number of current exists.
+    // Read: @args = (*size_t)
+    UC_CTL_UC_EXITS_CNT,
+    // Current exists.
+    // Write: @args = (*uint64_t exists, size_t len)
+    //        @len = UC_CTL_UC_EXITS_CNT
+    // Read: @args = (*uint64_t exists, size_t len)
+    //       @len = UC_CTL_UC_EXITS_CNT
+    UC_CTL_UC_EXITS,
+    // Set the cpu model of uc.
+    // Note this option can only be set before any Unicorn
+    // API is called except for uc_open.
+    // Write: @args = (int)
+    // Read:  @args = (int)
+    UC_CTL_CPU_MODEL,
+    // Request the edge of two TBs.
+    // Read: @args = (uint64_t, uint64_t, *uint64_t)
+    UC_CTL_TB_EDGE,
+    // Request a tb cache at a specific address
+    // Read: @args = (uint64_t)
+    UC_CTL_TB_REQUEST_CACHE,
+    // Remove a tb cache at a specific address
+    // Read: @args = (uint64_t)
+    UC_CTL_TB_REMOVE_CACHE
+
+} uc_control_type;
+
+#define uc_ctl_get_mode(uc, mode)                                              \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_MODE, 1), (mode))
+#define uc_ctl_get_page_size(uc, ptr)                                          \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_PAGE_SIZE, 1, (ptr))
+#define uc_ctl_set_page_size(uc, page_size)                                    \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_PAGE_SIZE, 1), (page_size))
+#define uc_ctl_get_arch(uc, arch)                                              \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_ARCH, 1), (arch))
+#define uc_ctl_get_timeout(uc, ptr)                                            \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_TIMEOUT, 1), (ptr))
+#define uc_ctl_get_exists_cnt(uc, ptr)                                         \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS_CNT, 1), (ptr))
+#define uc_ctl_get_exists(uc, buffer, len)                                     \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS, 2), (buffer), (len))
+#define uc_ctl_set_exists(uc, buffer, len)                                     \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_EXITS, 2), (buffer), (len))
+#define uc_ctl_get_cpu_model(uc, model)                                        \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_CPU_MODEL, 1), (model))
+#define uc_ctl_set_cpu_model(uc, model)                                        \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_CPU_MODEL, 1), (model))
+#define uc_ctl_remove_cache(uc, address)                                       \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REMOVE_CACHE, 1), (address))
+#define uc_ctl_request_cache(uc, address)                                      \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REQUEST_CACHE, 1), (address))
+#define uc_ctl_get_edge(uc, addr1, addr2, ptr)                                 \
+    uc_ctl(uc, UC_CTL_READ_WRITE(UC_CTL_TB_EDGE, 3), (addr1), (addr2), (ptr))
+
 // Opaque storage for CPU context, used with uc_context_*()
 struct uc_context;
 typedef struct uc_context uc_context;
@@ -467,6 +569,20 @@ uc_err uc_close(uc_engine *uc);
 UNICORN_EXPORT
 uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result);
 
+/*
+ Control internal states of engine.
+
+ Also see uc_ctl_* macro helpers for easy use.
+
+ @uc: handle returned by uc_open()
+ @option: control type.
+ @args: See uc_control_type for details about variadic arguments.
+
+ @return: error code of uc_err enum type (UC_ERR_*, see above)
+*/
+UNICORN_EXPORT
+uc_err uc_ctl(uc_engine *uc, uc_control_type option, ...);
+
 /*
  Report the last error number when some API function fail.
  Like glibc's errno, uc_errno might not retain its old value once accessed.
diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h
index 1f9b740e..f91ce057 100644
--- a/include/unicorn/x86.h
+++ b/include/unicorn/x86.h
@@ -13,6 +13,47 @@ extern "C" {
 
 #include "platform.h"
 
+typedef enum uc_cpu_x86 {
+    UC_CPU_X86_QEMU64 = 0,
+    UC_CPU_X86_PHENOM,
+    UC_CPU_X86_CORE2DUO,
+    UC_CPU_X86_KVM64,
+    UC_CPU_X86_QEMU32,
+    UC_CPU_X86_KVM32,
+    UC_CPU_X86_COREDUO,
+    UC_CPU_X86_486,
+    UC_CPU_X86_PENTIUM,
+    UC_CPU_X86_PENTIUM2,
+    UC_CPU_X86_PENTIUM3,
+    UC_CPU_X86_ATHLON,
+    UC_CPU_X86_N270,
+    UC_CPU_X86_CONROE,
+    UC_CPU_X86_PENRYN,
+    UC_CPU_X86_NEHALEM,
+    UC_CPU_X86_WESTMERE,
+    UC_CPU_X86_SANDYBRIDGE,
+    UC_CPU_X86_IVYBRIDGE,
+    UC_CPU_X86_HASWELL,
+    UC_CPU_X86_BROADWELL,
+    UC_CPU_X86_SKYLAKE_CLIENT,
+    UC_CPU_X86_SKYLAKE_SERVER,
+    UC_CPU_X86_CASCADELAKE_SERVER,
+    UC_CPU_X86_COOPERLAKE,
+    UC_CPU_X86_ICELAKE_CLIENT,
+    UC_CPU_X86_ICELAKE_SERVER,
+    UC_CPU_X86_DENVERTON,
+    UC_CPU_X86_SNOWRIDGE,
+    UC_CPU_X86_KNIGHTSMILL,
+    UC_CPU_X86_OPTERON_G1,
+    UC_CPU_X86_OPTERON_G2,
+    UC_CPU_X86_OPTERON_G3,
+    UC_CPU_X86_OPTERON_G4,
+    UC_CPU_X86_OPTERON_G5,
+    UC_CPU_X86_EPYC,
+    UC_CPU_X86_DHYANA,
+    UC_CPU_X86_EPYC_ROME
+} uc_cpu_x86;
+
 // Memory-Management Register for instructions IDTR, GDTR, LDTR, TR.
 // Borrow from SegmentCache in qemu/target-i386/cpu.h
 typedef struct uc_x86_mmr {
diff --git a/uc.c b/uc.c
index 07ae921f..ec0b7d5f 100644
--- a/uc.c
+++ b/uc.c
@@ -1519,6 +1519,12 @@ uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result)
     return UC_ERR_OK;
 }
 
+UNICORN_EXPORT
+uc_err uc_ctl(uc_engine *uc, uc_control_type option, ...)
+{
+    return UC_ERR_ARG;
+}
+
 UNICORN_EXPORT
 uc_err uc_context_alloc(uc_engine *uc, uc_context **context)
 {