From 09aa0f944f595b9e534ba5ab11c8c024f92ac14d Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 3 Nov 2021 13:20:46 +0100 Subject: [PATCH] Merge QDucasse:riscv_extension_d Fix and close #1469 Fix test for riscv float points Fix the riscv cpu config we left out --- qemu/target/riscv/cpu.c | 19 ++++++ tests/unit/test_riscv.c | 134 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 146 insertions(+), 7 deletions(-) diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index 7b83d5ef..bc3d4a47 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -364,6 +364,25 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model) /* init RISCVCPUClass */ riscv_cpu_class_init(uc, cc, NULL); + /* init device properties*/ + cpu->cfg.ext_i = true; + cpu->cfg.ext_e = false; + cpu->cfg.ext_g = true; + cpu->cfg.ext_m = true; + cpu->cfg.ext_a = true; + cpu->cfg.ext_f = true; + cpu->cfg.ext_d = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_h = false; + cpu->cfg.ext_counters = true; + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.priv_spec = "v1.11.0"; + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; + /* init CPUState */ cpu_common_initfn(uc, cs); diff --git a/tests/unit/test_riscv.c b/tests/unit/test_riscv.c index 24fb87e1..0ca9a09c 100644 --- a/tests/unit/test_riscv.c +++ b/tests/unit/test_riscv.c @@ -217,10 +217,130 @@ static void test_riscv64_3steps_pc_update() OK(uc_close(uc)); } -TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop}, - {"test_riscv64_nop", test_riscv64_nop}, - {"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update}, - {"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update}, - {"test_riscv32_until_pc_update", test_riscv32_until_pc_update}, - {"test_riscv64_until_pc_update", test_riscv64_until_pc_update}, - {NULL, NULL}}; +static void test_riscv32_fp_move(void) { + uc_engine *uc; + char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1 + + uint32_t r_f1 = 0x1234; + uint32_t r_f3 = 0x5678; + + uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1); + + // initialize machine registers + uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1); + uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3); + + // emulate the instruction + OK(uc_emu_start(uc, code_start, -1, 0, 1)); + + OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1)); + OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3)); + + TEST_CHECK(r_f1 == 0x1234); + TEST_CHECK(r_f3 == 0x1234); + + uc_close(uc); +} + +static void test_riscv64_fp_move(void) { + uc_engine *uc; + char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1 + + uint64_t r_f1 = 0x12341234; + uint64_t r_f3 = 0x56785678; + + uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); + + // initialize machine registers + OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1)); + OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3)); + + // emulate the instruction + OK(uc_emu_start(uc, code_start, -1, 0, 1)); + + OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1)); + OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3)); + + TEST_CHECK(r_f1 == 0x12341234); + TEST_CHECK(r_f3 == 0x12341234); + + uc_close(uc); +} + +static void test_riscv64_fp_move_from_int(void) { + uc_engine *uc; + // https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf + // https://five-embeddev.com/quickref/csrs.html + // We have to enable mstatus.fs + char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3; fmvd.d.x ft0, s6 + + uint64_t r_ft0 = 0x12341234; + uint64_t r_s6 = 0x56785678; + uint64_t r_x3 = 0x6000; + + uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); + + // initialize machine registers + OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0)); + OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6)); + + // mstatus.fs + OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3)); + + // emulate the instruction + OK(uc_emu_start(uc, code_start, -1, 0, 2)); + + OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0)); + OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6)); + + TEST_CHECK(r_ft0 == 0x56785678); + TEST_CHECK(r_s6 == 0x56785678); + + uc_close(uc); +} + +static void test_riscv64_fp_move_to_int(void) { + uc_engine *uc; + // https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf + // https://five-embeddev.com/quickref/csrs.html + // We have to enable mstatus.fs + char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3; fmv.x.d s6, ft0 + + uint64_t r_ft0 = 0x12341234; + uint64_t r_s6 = 0x56785678; + uint64_t r_x3 = 0x6000; + + uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); + + // initialize machine registers + OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0)); + OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6)); + + // mstatus.fs + OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3)); + + // emulate the instruction + OK(uc_emu_start(uc, code_start, -1, 0, 2)); + + OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0)); + OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6)); + + TEST_CHECK(r_ft0 == 0x12341234); + TEST_CHECK(r_s6 == 0x12341234); + + uc_close(uc); +} + +TEST_LIST = { + { "test_riscv32_nop", test_riscv32_nop }, + { "test_riscv64_nop", test_riscv64_nop }, + { "test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update }, + { "test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update }, + { "test_riscv32_until_pc_update", test_riscv32_until_pc_update }, + { "test_riscv64_until_pc_update", test_riscv64_until_pc_update }, + { "test_riscv32_fp_move", test_riscv32_fp_move }, + { "test_riscv64_fp_move", test_riscv64_fp_move }, + { "test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int }, + { "test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int }, + { NULL, NULL } +};