From 172a2fbe6d5b3354eb40ffe1bf7fcb3bc879393a Mon Sep 17 00:00:00 2001
From: lazymio <mio@lazym.io>
Date: Thu, 4 Nov 2021 19:13:53 +0100
Subject: [PATCH] Support changing cpu model for riscv

---
 qemu/target/riscv/cpu.c     | 22 +++++++++++-----------
 qemu/target/riscv/unicorn.c |  4 ++--
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index bc3d4a47..daed9c47 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -329,7 +329,7 @@ static const CPUModelInfo cpu_models[] = {
 #endif
 };
 
-RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model)
+RISCVCPU *cpu_riscv_init(struct uc_struct *uc)
 {
     RISCVCPU *cpu;
     CPUState *cs;
@@ -342,16 +342,21 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model)
     }
 
 #ifdef TARGET_RISCV32
-    if (!cpu_model) {
-        cpu_model = TYPE_RISCV_CPU_SIFIVE_U34;
+    if (uc->cpu_model == INT_MAX) {
+        uc->cpu_model = 3;
     }
 #else
     /* TARGET_RISCV64 */
-    if (!cpu_model) {
-        cpu_model = TYPE_RISCV_CPU_SIFIVE_U54;
+    if (uc->cpu_model == INT_MAX) {
+        uc->cpu_model = 3;
     }
 #endif
 
+    if (uc->cpu_model >= ARRAY_SIZE(cpu_models)) {
+        free(cpu);
+        return NULL;
+    }
+
     cs = (CPUState *)cpu;
     cc = (CPUClass *)&cpu->cc;
     cs->cc = cc;
@@ -390,12 +395,7 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model)
     riscv_cpu_init(uc, cs);
 
     /* init specific CPU model */
-    for (i = 0; i < ARRAY_SIZE(cpu_models); i++) {
-        if (strcmp(cpu_model, cpu_models[i].name) == 0) {
-            cpu_models[i].initfn(cs);
-            break;
-        }
-    }
+    cpu_models[uc->cpu_model].initfn(cs);
 
     /* realize CPU */
     riscv_cpu_realize(uc, cs);
diff --git a/qemu/target/riscv/unicorn.c b/qemu/target/riscv/unicorn.c
index c66a5c9a..1badb57a 100644
--- a/qemu/target/riscv/unicorn.c
+++ b/qemu/target/riscv/unicorn.c
@@ -10,7 +10,7 @@
 #include <unicorn/riscv.h>
 #include "unicorn.h"
 
-RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model);
+RISCVCPU *cpu_riscv_init(struct uc_struct *uc);
 
 static void riscv_set_pc(struct uc_struct *uc, uint64_t address)
 {
@@ -326,7 +326,7 @@ static int riscv_cpus_init(struct uc_struct *uc, const char *cpu_model)
 
     RISCVCPU *cpu;
 
-    cpu = cpu_riscv_init(uc, cpu_model);
+    cpu = cpu_riscv_init(uc);
     if (cpu == NULL) {
         return -1;
     }