Removed hardcoded CP0C3_ULRI (#1098)

* activate CP0C3_ULRI for CONFIG3, mips

* updated with mips patches

* updated with mips patches

* remove hardcoded config3

* git ignore vscode

* fix spacing issue and turn on floating point

.gitignore

@@ -72,8 +72,6 @@ bindings/python/MANIFEST
 config.log
 
 
-
-
 #################
 ## Visual Studio
 #################
@@ -81,6 +79,10 @@ config.log
 ## Ignore Visual Studio temporary files, build results, and
 ## files generated by popular Visual Studio add-ons.
 
+# vscode
+.vscode
+.vscode/
+
 # User-specific files
 *.opensdf
 *.sdf

bindings/dotnet/UnicornManaged/Const/Mips.fs

@@ -158,7 +158,9 @@ module Mips =
     let UC_MIPS_REG_MPL0 = 134
     let UC_MIPS_REG_MPL1 = 135
     let UC_MIPS_REG_MPL2 = 136
-    let UC_MIPS_REG_ENDING = 137
+    let UC_MIPS_REG_CP0_CONFIG3 = 137
+    let UC_MIPS_REG_CP0_USERLOCAL = 138
+    let UC_MIPS_REG_ENDING = 139
     let UC_MIPS_REG_ZERO = 2
     let UC_MIPS_REG_AT = 3
     let UC_MIPS_REG_V0 = 4

bindings/go/unicorn/mips_const.go

@@ -153,7 +153,9 @@ const (
 	MIPS_REG_MPL0 = 134
 	MIPS_REG_MPL1 = 135
 	MIPS_REG_MPL2 = 136
-	MIPS_REG_ENDING = 137
+	MIPS_REG_CP0_CONFIG3 = 137
+	MIPS_REG_CP0_USERLOCAL = 138
+	MIPS_REG_ENDING = 139
 	MIPS_REG_ZERO = 2
 	MIPS_REG_AT = 3
 	MIPS_REG_V0 = 4

bindings/java/unicorn/MipsConst.java

@@ -155,7 +155,9 @@ public interface MipsConst {
    public static final int UC_MIPS_REG_MPL0 = 134;
    public static final int UC_MIPS_REG_MPL1 = 135;
    public static final int UC_MIPS_REG_MPL2 = 136;
-   public static final int UC_MIPS_REG_ENDING = 137;
+   public static final int UC_MIPS_REG_CP0_CONFIG3 = 137;
+   public static final int UC_MIPS_REG_CP0_USERLOCAL = 138;
+   public static final int UC_MIPS_REG_ENDING = 139;
    public static final int UC_MIPS_REG_ZERO = 2;
    public static final int UC_MIPS_REG_AT = 3;
    public static final int UC_MIPS_REG_V0 = 4;

bindings/pascal/unicorn/MipsConst.pas

@@ -156,7 +156,9 @@ const
   UC_MIPS_REG_MPL0 = 134;
   UC_MIPS_REG_MPL1 = 135;
   UC_MIPS_REG_MPL2 = 136;
-  UC_MIPS_REG_ENDING = 137;
+  UC_MIPS_REG_CP0_CONFIG3 = 137;
+  UC_MIPS_REG_CP0_USERLOCAL = 138;
+  UC_MIPS_REG_ENDING = 139;
   UC_MIPS_REG_ZERO = 2;
   UC_MIPS_REG_AT = 3;
   UC_MIPS_REG_V0 = 4;

bindings/python/unicorn/mips_const.py

@@ -151,7 +151,9 @@ UC_MIPS_REG_P2 = 133
 UC_MIPS_REG_MPL0 = 134
 UC_MIPS_REG_MPL1 = 135
 UC_MIPS_REG_MPL2 = 136
-UC_MIPS_REG_ENDING = 137
+UC_MIPS_REG_CP0_CONFIG3 = 137
+UC_MIPS_REG_CP0_USERLOCAL = 138
+UC_MIPS_REG_ENDING = 139
 UC_MIPS_REG_ZERO = 2
 UC_MIPS_REG_AT = 3
 UC_MIPS_REG_V0 = 4

bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb

@@ -153,7 +153,9 @@ module UnicornEngine
 	UC_MIPS_REG_MPL0 = 134
 	UC_MIPS_REG_MPL1 = 135
 	UC_MIPS_REG_MPL2 = 136
-	UC_MIPS_REG_ENDING = 137
+	UC_MIPS_REG_CP0_CONFIG3 = 137
+	UC_MIPS_REG_CP0_USERLOCAL = 138
+	UC_MIPS_REG_ENDING = 139
 	UC_MIPS_REG_ZERO = 2
 	UC_MIPS_REG_AT = 3
 	UC_MIPS_REG_V0 = 4

include/unicorn/mips.h

@@ -175,6 +175,9 @@ typedef enum UC_MIPS_REG {
     UC_MIPS_REG_MPL1,
     UC_MIPS_REG_MPL2,
 
+    UC_MIPS_REG_CP0_CONFIG3,
+    UC_MIPS_REG_CP0_USERLOCAL,
+
     UC_MIPS_REG_ENDING,	// <-- mark the end of the list or registers
 
     // alias registers

qemu/target-mips/op_helper.c

@@ -47,6 +47,10 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
         cpu_restore_state(cs, pc);
     }
 
+    if (exception == 0x11) {
+        env->uc->next_pc = env->active_tc.PC + 4;
+    }
+
     cpu_loop_exit(cs);
 }
 

qemu/target-mips/translate.c

@@ -19711,6 +19711,9 @@ void cpu_state_reset(CPUMIPSState *env)
             env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A);
         }
     }
+    if (env->CP0_Config1 & (1 << CP0C1_FP)) {
+        env->CP0_Status |= (1 << CP0St_CU1);
+    }
 #endif
     if ((env->insn_flags & ISA_MIPS32R6) &&
         (env->active_fpu.fcr0 & (1 << FCR0_F64))) {

qemu/target-mips/translate_init.c

@@ -43,8 +43,7 @@
 #define MIPS_CONFIG3                                              \
 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) |          \
  (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) |        \
- (0 << CP0C3_SM) | (0 << CP0C3_TL)) | (1 << CP0C3_ULRI)
+ (0 << CP0C3_SM) | (0 << CP0C3_TL))
-
 #define MIPS_CONFIG4                                              \
 ((0 << CP0C4_M))
 

qemu/target-mips/unicorn.c

@@ -96,6 +96,12 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
                 case UC_MIPS_REG_PC:
                          *(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
                          break;
+                case UC_MIPS_REG_CP0_CONFIG3:
+                         *(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.CP0_Config3;
+                         break;
+                case UC_MIPS_REG_CP0_USERLOCAL:
+                         *(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.CP0_UserLocal;
+                         break;                              
             }
         }
     }
@@ -122,6 +128,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
                          uc->quit_request = true;
                          uc_emu_stop(uc);
                          break;
+                case UC_MIPS_REG_CP0_CONFIG3:
+                         MIPS_CPU(uc, mycpu)->env.CP0_Config3 = *(mipsreg_t *)value;
+                         break;
+                case UC_MIPS_REG_CP0_USERLOCAL:
+                         MIPS_CPU(uc, mycpu)->env.active_tc.CP0_UserLocal = *(mipsreg_t *)value;
+                         break;                         
             }
         }
     }