Basic implementation of uc_ctl
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@ -427,40 +427,43 @@ typedef enum uc_query_type {
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// If a control don't have `Set` or `Get` for @args, it means it's r/o or w/o.
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typedef enum uc_control_type {
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// Current mode.
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// Read: @args = (*int)
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// Read: @args = (int*)
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UC_CTL_UC_MODE = 0,
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// Curent page size.
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// Write: @args = (int)
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// Read: @args = (*int)
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// Write: @args = (uint32_t)
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// Read: @args = (uint32_t*)
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UC_CTL_UC_PAGE_SIZE,
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// Current arch.
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// Read: @args = (*int)
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// Read: @args = (int*)
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UC_CTL_UC_ARCH,
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// Current timeout.
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// Read: @args = (*uint64_t)
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// Read: @args = (uint64_t*)
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UC_CTL_UC_TIMEOUT,
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// Enable multiple exists.
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// Without this control, reading/setting exists won't work.
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// This is for API backward compatibility.
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// Write: @args = (int)
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UC_CTL_UC_USE_EXITS,
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// The number of current exists.
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// Read: @args = (*size_t)
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// Read: @args = (size_t*)
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UC_CTL_UC_EXITS_CNT,
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// Current exists.
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// Write: @args = (*uint64_t exists, size_t len)
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// Write: @args = (uint64_t* exists, size_t len)
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// @len = UC_CTL_UC_EXITS_CNT
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// Read: @args = (*uint64_t exists, size_t len)
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// Read: @args = (uint64_t* exists, size_t len)
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// @len = UC_CTL_UC_EXITS_CNT
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UC_CTL_UC_EXITS,
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// Set the cpu model of uc.
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// Note this option can only be set before any Unicorn
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// API is called except for uc_open.
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// Write: @args = (int)
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// Read: @args = (int)
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UC_CTL_CPU_MODEL,
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// Request the edge of two TBs.
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// Read: @args = (uint64_t, uint64_t, *uint64_t)
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UC_CTL_TB_EDGE,
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// Request a tb cache at a specific address
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// Read: @args = (uint64_t)
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UC_CTL_TB_REQUEST_CACHE,
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// Remove a tb cache at a specific address
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// Invalidate a tb cache at a specific address
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// Read: @args = (uint64_t)
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UC_CTL_TB_REMOVE_CACHE
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@ -469,13 +472,15 @@ typedef enum uc_control_type {
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#define uc_ctl_get_mode(uc, mode) \
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_MODE, 1), (mode))
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#define uc_ctl_get_page_size(uc, ptr) \
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_PAGE_SIZE, 1, (ptr))
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_PAGE_SIZE, 1), (ptr))
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#define uc_ctl_set_page_size(uc, page_size) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_PAGE_SIZE, 1), (page_size))
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#define uc_ctl_get_arch(uc, arch) \
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_ARCH, 1), (arch))
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#define uc_ctl_get_timeout(uc, ptr) \
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_TIMEOUT, 1), (ptr))
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#define uc_ctl_exits_enabled(uc, enabled) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_USE_EXITS, 1), (enabled))
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#define uc_ctl_get_exists_cnt(uc, ptr) \
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uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS_CNT, 1), (ptr))
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#define uc_ctl_get_exists(uc, buffer, len) \
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@ -487,11 +492,9 @@ typedef enum uc_control_type {
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#define uc_ctl_set_cpu_model(uc, model) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_CPU_MODEL, 1), (model))
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#define uc_ctl_remove_cache(uc, address) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REMOVE_CACHE, 1), (address))
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uc_ctl(uc, UC_CTL_READ(UC_CTL_TB_REMOVE_CACHE, 1), (address))
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#define uc_ctl_request_cache(uc, address) \
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uc_ctl(uc, UC_CTL_WRITE(UC_CTL_TB_REQUEST_CACHE, 1), (address))
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#define uc_ctl_get_edge(uc, addr1, addr2, ptr) \
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uc_ctl(uc, UC_CTL_READ_WRITE(UC_CTL_TB_EDGE, 3), (addr1), (addr2), (ptr))
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uc_ctl(uc, UC_CTL_READ(UC_CTL_TB_REQUEST_CACHE, 1), (address))
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// Opaque storage for CPU context, used with uc_context_*()
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struct uc_context;
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