reg_read and reg_write now work with registers W0 through W30 in Aarch64 (#716)

* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton

* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write

* Fixed WRITE_DWORD macro

reg_write would zero out the high order bits when writing to 32 bit registers

e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero

tests/regress/arm64_reg_rw_w0_w30.py

@@ -0,0 +1,30 @@
+#!/usr/bin/python
+
+from unicorn import *
+from unicorn.arm64_const import *
+from unicorn.x86_const import *
+
+import regress
+
+class Arm64RegReadWriteW0ThroughW30(regress.RegressTest):
+    """
+    Testing the functionality to read/write 32-bit registers in AArch64
+    See issue #716 
+    """
+
+    def runTest(self):
+        uc = Uc(UC_ARCH_ARM64, UC_MODE_ARM)
+        
+        uc.reg_write(UC_ARM64_REG_X0, 0x1234567890abcdef)
+        self.assertEquals(uc.reg_read(UC_ARM64_REG_X0), 0x1234567890abcdef)
+        self.assertEquals(uc.reg_read(UC_ARM64_REG_W0), 0x90abcdef)
+        
+        uc.reg_write(UC_ARM64_REG_X30, 0xa1b2c3d4e5f6a7b8)
+        self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xe5f6a7b8)
+
+        uc.reg_write(UC_ARM64_REG_W30, 0xaabbccdd)
+        self.assertEquals(uc.reg_read(UC_ARM64_REG_X30), 0xa1b2c3d4aabbccdd)
+        self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xaabbccdd)
+
+if __name__ == '__main__':
+    regress.main()