diff --git a/tests/unit/test_arm64.c b/tests/unit/test_arm64.c
index 972d24c6..59333f4d 100644
--- a/tests/unit/test_arm64.c
+++ b/tests/unit/test_arm64.c
@@ -3,6 +3,52 @@
 const uint64_t code_start = 0x1000;
 const uint64_t code_len = 0x4000;
 
+static void uc_common_setup(uc_engine** uc, uc_arch arch, uc_mode mode, const char* code, uint64_t size) {
+    OK(uc_open(arch, mode, uc));
+    OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
+    OK(uc_mem_write(*uc, code_start, code, size));
+}
+
+static void test_arm64_until() {
+  uc_engine *uc;
+  char code[] = "\x30\x00\x80\xd2\x11\x04\x80\xd2\x9c\x23\x00\x91";
+
+  /*
+  mov x16, #1
+  mov x17, #0x20
+  add x28, x28, 8
+  */
+
+  uint64_t r_x16 = 0x12341234;
+  uint64_t r_x17 = 0x78907890;
+  uint64_t r_pc  = 0x00000000;
+  uint64_t r_x28 = 0x12341234;
+
+  uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1);
+
+  // initialize machine registers
+  OK(uc_reg_write(uc, UC_ARM64_REG_X16, &r_x16));
+  OK(uc_reg_write(uc, UC_ARM64_REG_X17, &r_x17));
+  OK(uc_reg_write(uc, UC_ARM64_REG_X28, &r_x28));
+
+  // emulate the three instructions
+  OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 3));
+
+  OK(uc_reg_read(uc, UC_ARM64_REG_X16, &r_x16));
+  OK(uc_reg_read(uc, UC_ARM64_REG_X17, &r_x17));
+  OK(uc_reg_read(uc, UC_ARM64_REG_X28, &r_x28));
+  OK(uc_reg_read(uc, UC_ARM64_REG_PC, &r_pc));
+
+  TEST_CHECK(r_x16 == 0x1);
+  TEST_CHECK(r_x17 == 0x20);
+  TEST_CHECK(r_x28 == 0x1234123c);
+  TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
+
+  OK(uc_close(uc));
+}
+
+
 TEST_LIST = {
+    { "test_arm64_until", test_arm64_until },
     { NULL, NULL }
-};
\ No newline at end of file
+};
diff --git a/tests/unit/test_riscv.c b/tests/unit/test_riscv.c
index 972d24c6..674954db 100644
--- a/tests/unit/test_riscv.c
+++ b/tests/unit/test_riscv.c
@@ -3,6 +3,133 @@
 const uint64_t code_start = 0x1000;
 const uint64_t code_len = 0x4000;
 
+static void uc_common_setup(uc_engine** uc, uc_arch arch, uc_mode mode, const char* code, uint64_t size) {
+    OK(uc_open(arch, mode, uc));
+    OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
+    OK(uc_mem_write(*uc, code_start, code, size));
+}
+
+static void test_riscv32_nop() {
+    uc_engine* uc;
+    char code[] = "\x13\x00\x00\x00"; // nop
+    uint32_t r_t0 = 0x1234;
+    uint32_t r_t1 = 0x5678;
+
+    uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1);
+    OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
+    OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
+
+    OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
+
+    OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
+    OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
+    TEST_CHECK(r_t0 == 0x1234);
+    TEST_CHECK(r_t1 == 0x5678);
+
+    OK(uc_close(uc));
+}
+
+static void test_riscv64_nop() {
+    uc_engine* uc;
+    char code[] = "\x13\x00\x00\x00"; // nop
+    uint64_t r_t0 = 0x1234;
+    uint64_t r_t1 = 0x5678;
+
+    uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
+    OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
+    OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
+
+    OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
+
+    OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
+    OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
+    TEST_CHECK(r_t0 == 0x1234);
+    TEST_CHECK(r_t1 == 0x5678);
+
+    OK(uc_close(uc));
+}
+
+static void test_riscv32_until_pc_update() {
+  uc_engine *uc;
+  char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
+
+  /*
+  addi t0, zero, 1
+  addi t1, zero, 0x20
+  addi sp, sp, 8
+  */
+
+  uint32_t r_t0 = 0x1234;
+  uint32_t r_t1 = 0x7890;
+  uint32_t r_pc = 0x0000;
+  uint32_t r_sp = 0x1234;
+
+  uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1);
+
+  // initialize machine registers
+  OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
+  OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
+  OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
+
+  // emulate the three instructions
+  OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
+
+  OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
+  OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
+  OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
+  OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
+
+  TEST_CHECK(r_t0 == 0x1);
+  TEST_CHECK(r_t1 == 0x20);
+  TEST_CHECK(r_sp == 0x123c);
+
+  TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
+
+  OK(uc_close(uc));
+}
+
+static void test_riscv64_until_pc_update() {
+  uc_engine *uc;
+  char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
+
+  /*
+  addi t0, zero, 1
+  addi t1, zero, 0x20
+  addi sp, sp, 8
+  */
+
+  uint64_t r_t0 = 0x1234;
+  uint64_t r_t1 = 0x7890;
+  uint64_t r_pc = 0x0000;
+  uint64_t r_sp = 0x1234;
+
+  uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
+
+  // initialize machine registers
+  OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
+  OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
+  OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
+
+  // emulate the three instructions
+  OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
+
+  OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
+  OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
+  OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
+  OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
+
+  TEST_CHECK(r_t0 == 0x1);
+  TEST_CHECK(r_t1 == 0x20);
+  TEST_CHECK(r_sp == 0x123c);
+  TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
+
+  OK(uc_close(uc));
+}
+
 TEST_LIST = {
+    { "test_riscv32_nop", test_riscv32_nop },
+    { "test_riscv64_nop", test_riscv64_nop },
+    { "test_riscv32_until_pc_update", test_riscv32_until_pc_update },
+    { "test_riscv64_until_pc_update", test_riscv64_until_pc_update },
     { NULL, NULL }
-};
\ No newline at end of file
+};