diff --git a/qemu/fpu/softfloat-specialize.h b/qemu/fpu/softfloat-specialize.h
index 518f694a..549b4256 100644
--- a/qemu/fpu/softfloat-specialize.h
+++ b/qemu/fpu/softfloat-specialize.h
@@ -122,7 +122,7 @@ const float128 float128_default_nan
 | should be simply `float_exception_flags |= flags;'.
 *----------------------------------------------------------------------------*/
 
-void float_raise( int8 flags STATUS_PARAM )
+void float_raise( uint8_t flags STATUS_PARAM )
 {
     STATUS(float_exception_flags) |= flags;
 }
diff --git a/qemu/fpu/softfloat.c b/qemu/fpu/softfloat.c
index d409e78f..c299e803 100644
--- a/qemu/fpu/softfloat.c
+++ b/qemu/fpu/softfloat.c
@@ -2974,7 +2974,7 @@ int32 float64_to_int32_round_to_zero( float64 a STATUS_PARAM )
     savedASig = aSig;
     aSig >>= shiftCount;
     z = (int32_t)aSig;
-    if ( aSign ) z = - z;
+    if ( aSign && (z != 0x80000000)) z = - z;
     if ( ( z < 0 ) ^ aSign ) {
  invalid:
         float_raise( float_flag_invalid STATUS_VAR);
diff --git a/qemu/include/fpu/softfloat.h b/qemu/include/fpu/softfloat.h
index 94b4e194..d15678d5 100644
--- a/qemu/include/fpu/softfloat.h
+++ b/qemu/include/fpu/softfloat.h
@@ -246,7 +246,7 @@ static inline flag get_default_nan_mode(float_status *status)
 | Routine to raise any or all of the software IEC/IEEE floating-point
 | exception flags.
 *----------------------------------------------------------------------------*/
-void float_raise( int8 flags STATUS_PARAM);
+void float_raise( uint8_t flags STATUS_PARAM);
 
 /*----------------------------------------------------------------------------
 | If `a' is denormal and we are in flush-to-zero mode then set the
diff --git a/qemu/target-arm/neon_helper.c b/qemu/target-arm/neon_helper.c
index a1f4af7a..72acdf13 100644
--- a/qemu/target-arm/neon_helper.c
+++ b/qemu/target-arm/neon_helper.c
@@ -732,7 +732,7 @@ uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)
             val >>= 1;
         }
     } else {
-        val <<= shift;
+        val = ((uint64_t)val) << shift;
     }
     return val;
 }
diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c
index e4ce6029..a6e0a8ec 100644
--- a/qemu/target-arm/translate-a64.c
+++ b/qemu/target-arm/translate-a64.c
@@ -5584,7 +5584,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
 {
     TCGContext *tcg_ctx = s->uc->tcg_ctx;
     int size = ctz32(imm5);
-    int esize = 8 << size;
+    int esize = 8 << (size & 0x1f);
     int elements = (is_q ? 128 : 64) / esize;
     int index, i;
     TCGv_i64 tmp;
diff --git a/qemu/target-i386/ops_sse.h b/qemu/target-i386/ops_sse.h
index e8c01f85..0f628515 100644
--- a/qemu/target-i386/ops_sse.h
+++ b/qemu/target-i386/ops_sse.h
@@ -1678,7 +1678,7 @@ SSE_HELPER_L(helper_pmaxsd, FMAXSD)
 SSE_HELPER_W(helper_pmaxuw, MAX)
 SSE_HELPER_L(helper_pmaxud, MAX)
 
-#define FMULLD(d, s) ((int32_t)d * (int32_t)s)
+#define FMULLD(d, s) ((int64_t)d * (int32_t)s)
 SSE_HELPER_L(helper_pmulld, FMULLD)
 
 void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h
index 38b7dd9d..51a0631e 100644
--- a/qemu/tcg/tcg-op.h
+++ b/qemu/tcg/tcg-op.h
@@ -2079,7 +2079,7 @@ static inline void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg
         return;
     }
 
-    mask = (1u << len) - 1;
+    mask = (1u << (len & 0x1f)) - 1;
     t1 = tcg_temp_new_i32(s);
 
     if (ofs + len < 32) {