Fix #1500
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@ -308,6 +308,43 @@ static void test_arm_und32_to_svc32()
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OK(uc_close(uc));
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}
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static void test_arm_usr32_to_svc32()
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{
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uc_engine *uc;
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int r_cpsr, r_sp, r_spsr, r_lr;
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OK(uc_open(UC_ARCH_ARM, UC_MODE_ARM, &uc));
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OK(uc_ctl_set_cpu_model(uc, UC_CPU_ARM_CORTEX_A9));
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// https://www.keil.com/pack/doc/CMSIS/Core_A/html/group__CMSIS__CPSR__M.html
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r_cpsr = 0x40000093; // SVC32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_sp = 0x12345678;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_cpsr = 0x4000009b; // UND32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_spsr = 0x40000093; // Save previous CPSR
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OK(uc_reg_write(uc, UC_ARM_REG_SPSR, &r_spsr));
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r_sp = 0xDEAD0000;
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OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp));
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r_lr = code_start + 8;
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OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr));
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r_cpsr = 0x40000090; // USR32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_sp = 0x0010000;
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OK(uc_reg_write(uc, UC_ARM_REG_R13, &r_sp));
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r_cpsr = 0x40000093; // SVC32
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp));
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TEST_CHECK(r_sp == 0x12345678);
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_thumb_sub", test_arm_thumb_sub},
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{"test_armeb_sub", test_armeb_sub},
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@ -317,4 +354,5 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_m_control", test_arm_m_control},
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{"test_arm_m_exc_return", test_arm_m_exc_return},
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{"test_arm_und32_to_svc32", test_arm_und32_to_svc32},
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{"test_arm_usr32_to_svc32", test_arm_usr32_to_svc32},
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{NULL, NULL}};
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