bindings: add Rust

2021-10-04 01:01:43 +08:00
parent 5460bfd97d
commit 54e7e3b9ef
15 changed files with 3440 additions and 0 deletions
--- a/bindings/rust/src/arm.rs
+++ b/bindings/rust/src/arm.rs
@ -0,0 +1,146 @@
+#![allow(non_camel_case_types)]
+// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
+
+#[repr(C)]
+#[derive(PartialEq, Debug, Clone, Copy)]
+pub enum RegisterARM {
+    // ARM registers
+    INVALID = 0,
+    APSR = 1,
+    APSR_NZCV = 2,
+    CPSR = 3,
+    FPEXC = 4,
+    FPINST = 5,
+    FPSCR = 6,
+    FPSCR_NZCV = 7,
+    FPSID = 8,
+    ITSTATE = 9,
+    LR = 10,
+    PC = 11,
+    SP = 12,
+    SPSR = 13,
+    D0 = 14,
+    D1 = 15,
+    D2 = 16,
+    D3 = 17,
+    D4 = 18,
+    D5 = 19,
+    D6 = 20,
+    D7 = 21,
+    D8 = 22,
+    D9 = 23,
+    D10 = 24,
+    D11 = 25,
+    D12 = 26,
+    D13 = 27,
+    D14 = 28,
+    D15 = 29,
+    D16 = 30,
+    D17 = 31,
+    D18 = 32,
+    D19 = 33,
+    D20 = 34,
+    D21 = 35,
+    D22 = 36,
+    D23 = 37,
+    D24 = 38,
+    D25 = 39,
+    D26 = 40,
+    D27 = 41,
+    D28 = 42,
+    D29 = 43,
+    D30 = 44,
+    D31 = 45,
+    FPINST2 = 46,
+    MVFR0 = 47,
+    MVFR1 = 48,
+    MVFR2 = 49,
+    Q0 = 50,
+    Q1 = 51,
+    Q2 = 52,
+    Q3 = 53,
+    Q4 = 54,
+    Q5 = 55,
+    Q6 = 56,
+    Q7 = 57,
+    Q8 = 58,
+    Q9 = 59,
+    Q10 = 60,
+    Q11 = 61,
+    Q12 = 62,
+    Q13 = 63,
+    Q14 = 64,
+    Q15 = 65,
+    R0 = 66,
+    R1 = 67,
+    R2 = 68,
+    R3 = 69,
+    R4 = 70,
+    R5 = 71,
+    R6 = 72,
+    R7 = 73,
+    R8 = 74,
+    R9 = 75,
+    R10 = 76,
+    R11 = 77,
+    R12 = 78,
+    S0 = 79,
+    S1 = 80,
+    S2 = 81,
+    S3 = 82,
+    S4 = 83,
+    S5 = 84,
+    S6 = 85,
+    S7 = 86,
+    S8 = 87,
+    S9 = 88,
+    S10 = 89,
+    S11 = 90,
+    S12 = 91,
+    S13 = 92,
+    S14 = 93,
+    S15 = 94,
+    S16 = 95,
+    S17 = 96,
+    S18 = 97,
+    S19 = 98,
+    S20 = 99,
+    S21 = 100,
+    S22 = 101,
+    S23 = 102,
+    S24 = 103,
+    S25 = 104,
+    S26 = 105,
+    S27 = 106,
+    S28 = 107,
+    S29 = 108,
+    S30 = 109,
+    S31 = 110,
+    C1_C0_2 = 111,
+    C13_C0_2 = 112,
+    C13_C0_3 = 113,
+    IPSR = 114,
+    MSP = 115,
+    PSP = 116,
+    CONTROL = 117,
+    XPSR = 118,
+    ENDING = 119,
+    // alias registers
+    // (assoc) R13 = 12,
+    // (assoc) R14 = 10,
+    // (assoc) R15 = 11,
+    // (assoc) SB = 75,
+    // (assoc) SL = 76,
+    // (assoc) FP = 77,
+    // (assoc) IP = 78,
+}
+
+impl RegisterARM {
+    pub const R13: RegisterARM = RegisterARM::SP;
+    pub const R14: RegisterARM = RegisterARM::LR;
+    pub const R15: RegisterARM = RegisterARM::PC;
+    pub const SB: RegisterARM = RegisterARM::R9;
+    pub const SL: RegisterARM = RegisterARM::R10;
+    pub const FP: RegisterARM = RegisterARM::R11;
+    pub const IP: RegisterARM = RegisterARM::R12;
+}