bindings: add Rust
This commit is contained in:
Nguyen Anh Quynh
246
bindings/rust/src/mips.rs
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246
bindings/rust/src/mips.rs
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#![allow(non_camel_case_types)]
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// MIPS registers
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#[repr(C)]
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#[derive(PartialEq, Debug, Clone, Copy)]
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pub enum RegisterMIPS {
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INVALID = 0,
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// General purpose registers
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PC = 1,
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GPR0 = 2,
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GPR1 = 3,
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GPR2 = 4,
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GPR3 = 5,
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GPR4 = 6,
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GPR5 = 7,
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GPR6 = 8,
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GPR7 = 9,
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GPR8 = 10,
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GPR9 = 11,
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GPR10 = 12,
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GPR11 = 13,
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GPR12 = 14,
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GPR13 = 15,
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GPR14 = 16,
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GPR15 = 17,
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GPR16 = 18,
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GPR17 = 19,
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GPR18 = 20,
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GPR19 = 21,
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GPR20 = 22,
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GPR21 = 23,
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GPR22 = 24,
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GPR23 = 25,
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GPR24 = 26,
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GPR25 = 27,
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GPR26 = 28,
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GPR27 = 29,
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GPR28 = 30,
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GPR29 = 31,
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GPR30 = 32,
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GPR31 = 33,
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// DSP registers
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DSPCCOND = 34,
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DSPCARRY = 35,
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DSPEFI = 36,
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DSPOUTFLAG = 37,
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DSPOUTFLAG16_19 = 38,
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DSPOUTFLAG20 = 39,
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DSPOUTFLAG21 = 40,
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DSPOUTFLAG22 = 41,
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DSPOUTFLAG23 = 42,
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DSPPOS = 43,
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DSPSCOUNT = 44,
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// ACC registers
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AC0 = 45,
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AC1 = 46,
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AC2 = 47,
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AC3 = 48,
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// COP registers
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CC0 = 49,
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CC1 = 50,
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CC2 = 51,
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CC3 = 52,
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CC4 = 53,
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CC5 = 54,
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CC6 = 55,
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CC7 = 56,
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// FPU registers
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F0 = 57,
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F1 = 58,
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F2 = 59,
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F3 = 60,
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F4 = 61,
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F5 = 62,
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F6 = 63,
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F7 = 64,
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F8 = 65,
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F9 = 66,
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F10 = 67,
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F11 = 68,
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F12 = 69,
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F13 = 70,
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F14 = 71,
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F15 = 72,
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F16 = 73,
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F17 = 74,
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F18 = 75,
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F19 = 76,
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F20 = 77,
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F21 = 78,
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F22 = 79,
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F23 = 80,
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F24 = 81,
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F25 = 82,
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F26 = 83,
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F27 = 84,
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F28 = 85,
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F29 = 86,
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F30 = 87,
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F31 = 88,
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FCC0 = 89,
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FCC1 = 90,
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FCC2 = 91,
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FCC3 = 92,
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FCC4 = 93,
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FCC5 = 94,
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FCC6 = 95,
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FCC7 = 96,
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// AFPR128
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W0 = 97,
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W1 = 98,
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W2 = 99,
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W3 = 100,
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W4 = 101,
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W5 = 102,
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W6 = 103,
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W7 = 104,
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W8 = 105,
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W9 = 106,
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W10 = 107,
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W11 = 108,
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W12 = 109,
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W13 = 110,
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W14 = 111,
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W15 = 112,
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W16 = 113,
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W17 = 114,
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W18 = 115,
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W19 = 116,
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W20 = 117,
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W21 = 118,
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W22 = 119,
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W23 = 120,
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W24 = 121,
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W25 = 122,
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W26 = 123,
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W27 = 124,
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W28 = 125,
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W29 = 126,
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W30 = 127,
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W31 = 128,
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HI = 129,
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LO = 130,
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P0 = 131,
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P1 = 132,
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P2 = 133,
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MPL0 = 134,
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MPL1 = 135,
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MPL2 = 136,
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CP0_CONFIG3 = 137,
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CP0_USERLOCAL = 138,
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ENDING = 139,
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// alias registers
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// (assoc) ZERO = 2,
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// (assoc) AT = 3,
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// (assoc) V0 = 4,
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// (assoc) V1 = 5,
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// (assoc) A0 = 6,
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// (assoc) A1 = 7,
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// (assoc) A2 = 8,
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// (assoc) A3 = 9,
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// (assoc) T0 = 10,
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// (assoc) T1 = 11,
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// (assoc) T2 = 12,
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// (assoc) T3 = 13,
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// (assoc) T4 = 14,
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// (assoc) T5 = 15,
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// (assoc) T6 = 16,
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// (assoc) T7 = 17,
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// (assoc) S0 = 18,
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// (assoc) S1 = 19,
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// (assoc) S2 = 20,
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// (assoc) S3 = 21,
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// (assoc) S4 = 22,
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// (assoc) S5 = 23,
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// (assoc) S6 = 24,
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// (assoc) S7 = 25,
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// (assoc) T8 = 26,
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// (assoc) T9 = 27,
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// (assoc) K0 = 28,
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// (assoc) K1 = 29,
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// (assoc) GP = 30,
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// (assoc) SP = 31,
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// (assoc) FP = 32,
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// (assoc) S8 = 32,
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// (assoc) RA = 33,
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// (assoc) HI0 = 45,
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// (assoc) HI1 = 46,
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// (assoc) HI2 = 47,
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// (assoc) HI3 = 48,
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// (assoc) LO0 = 45,
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// (assoc) LO1 = 46,
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// (assoc) LO2 = 47,
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// (assoc) LO3 = 48,
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}
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impl RegisterMIPS {
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pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0;
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pub const AT: RegisterMIPS = RegisterMIPS::GPR1;
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pub const V0: RegisterMIPS = RegisterMIPS::GPR2;
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pub const V1: RegisterMIPS = RegisterMIPS::GPR3;
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pub const A0: RegisterMIPS = RegisterMIPS::GPR4;
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pub const A1: RegisterMIPS = RegisterMIPS::GPR5;
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pub const A2: RegisterMIPS = RegisterMIPS::GPR6;
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pub const A3: RegisterMIPS = RegisterMIPS::GPR7;
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pub const T0: RegisterMIPS = RegisterMIPS::GPR8;
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pub const T1: RegisterMIPS = RegisterMIPS::GPR9;
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pub const T2: RegisterMIPS = RegisterMIPS::GPR10;
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pub const T3: RegisterMIPS = RegisterMIPS::GPR11;
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pub const T4: RegisterMIPS = RegisterMIPS::GPR12;
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pub const T5: RegisterMIPS = RegisterMIPS::GPR13;
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pub const T6: RegisterMIPS = RegisterMIPS::GPR14;
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pub const T7: RegisterMIPS = RegisterMIPS::GPR15;
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pub const S0: RegisterMIPS = RegisterMIPS::GPR16;
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pub const S1: RegisterMIPS = RegisterMIPS::GPR17;
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pub const S2: RegisterMIPS = RegisterMIPS::GPR18;
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pub const S3: RegisterMIPS = RegisterMIPS::GPR19;
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pub const S4: RegisterMIPS = RegisterMIPS::GPR20;
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pub const S5: RegisterMIPS = RegisterMIPS::GPR21;
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pub const S6: RegisterMIPS = RegisterMIPS::GPR22;
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pub const S7: RegisterMIPS = RegisterMIPS::GPR23;
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pub const T8: RegisterMIPS = RegisterMIPS::GPR24;
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pub const T9: RegisterMIPS = RegisterMIPS::GPR25;
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pub const K0: RegisterMIPS = RegisterMIPS::GPR26;
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pub const K1: RegisterMIPS = RegisterMIPS::GPR27;
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pub const GP: RegisterMIPS = RegisterMIPS::GPR28;
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pub const SP: RegisterMIPS = RegisterMIPS::GPR29;
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pub const FP: RegisterMIPS = RegisterMIPS::GPR30;
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pub const S8: RegisterMIPS = RegisterMIPS::GPR30;
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pub const RA: RegisterMIPS = RegisterMIPS::GPR31;
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pub const HI0: RegisterMIPS = RegisterMIPS::AC0;
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pub const HI1: RegisterMIPS = RegisterMIPS::AC1;
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pub const HI2: RegisterMIPS = RegisterMIPS::AC2;
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pub const HI3: RegisterMIPS = RegisterMIPS::AC3;
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pub const LO0: RegisterMIPS = RegisterMIPS::AC0;
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pub const LO1: RegisterMIPS = RegisterMIPS::AC1;
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pub const LO2: RegisterMIPS = RegisterMIPS::AC2;
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pub const LO3: RegisterMIPS = RegisterMIPS::AC3;
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}
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