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This commit is contained in:
lazymio
2021-11-03 13:28:12 +01:00
parent 09aa0f944f
commit 58edb2abe7
1 changed files with 98 additions and 90 deletions
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188
tests/unit/test_riscv.c
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@ -217,130 +217,138 @@ static void test_riscv64_3steps_pc_update()
OK(uc_close(uc)); OK(uc_close(uc));
} }
static void test_riscv32_fp_move(void) { static void test_riscv32_fp_move(void)
uc_engine *uc; {
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1 uc_engine *uc;
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
uint32_t r_f1 = 0x1234; uint32_t r_f1 = 0x1234;
uint32_t r_f3 = 0x5678; uint32_t r_f3 = 0x5678;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1); uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
sizeof(code) - 1);
// initialize machine registers // initialize machine registers
uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1); uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1);
uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3); uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3);
// emulate the instruction // emulate the instruction
OK(uc_emu_start(uc, code_start, -1, 0, 1)); OK(uc_emu_start(uc, code_start, -1, 0, 1));
OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1)); OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3)); OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
TEST_CHECK(r_f1 == 0x1234); TEST_CHECK(r_f1 == 0x1234);
TEST_CHECK(r_f3 == 0x1234); TEST_CHECK(r_f3 == 0x1234);
uc_close(uc); uc_close(uc);
} }
static void test_riscv64_fp_move(void) { static void test_riscv64_fp_move(void)
uc_engine *uc; {
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1 uc_engine *uc;
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
uint64_t r_f1 = 0x12341234; uint64_t r_f1 = 0x12341234;
uint64_t r_f3 = 0x56785678; uint64_t r_f3 = 0x56785678;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers // initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1)); OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1));
OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3)); OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3));
// emulate the instruction // emulate the instruction
OK(uc_emu_start(uc, code_start, -1, 0, 1)); OK(uc_emu_start(uc, code_start, -1, 0, 1));
OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1)); OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3)); OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
TEST_CHECK(r_f1 == 0x12341234); TEST_CHECK(r_f1 == 0x12341234);
TEST_CHECK(r_f3 == 0x12341234); TEST_CHECK(r_f3 == 0x12341234);
uc_close(uc); uc_close(uc);
} }
static void test_riscv64_fp_move_from_int(void) { static void test_riscv64_fp_move_from_int(void)
uc_engine *uc; {
// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf uc_engine *uc;
// https://five-embeddev.com/quickref/csrs.html // https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// We have to enable mstatus.fs // https://five-embeddev.com/quickref/csrs.html
char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3; fmvd.d.x ft0, s6 // We have to enable mstatus.fs
char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3;
// fmvd.d.x ft0, s6
uint64_t r_ft0 = 0x12341234; uint64_t r_ft0 = 0x12341234;
uint64_t r_s6 = 0x56785678; uint64_t r_s6 = 0x56785678;
uint64_t r_x3 = 0x6000; uint64_t r_x3 = 0x6000;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers // initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0)); OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6)); OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
// mstatus.fs // mstatus.fs
OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3)); OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
// emulate the instruction // emulate the instruction
OK(uc_emu_start(uc, code_start, -1, 0, 2)); OK(uc_emu_start(uc, code_start, -1, 0, 2));
OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0)); OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6)); OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
TEST_CHECK(r_ft0 == 0x56785678); TEST_CHECK(r_ft0 == 0x56785678);
TEST_CHECK(r_s6 == 0x56785678); TEST_CHECK(r_s6 == 0x56785678);
uc_close(uc); uc_close(uc);
} }
static void test_riscv64_fp_move_to_int(void) { static void test_riscv64_fp_move_to_int(void)
uc_engine *uc; {
// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf uc_engine *uc;
// https://five-embeddev.com/quickref/csrs.html // https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// We have to enable mstatus.fs // https://five-embeddev.com/quickref/csrs.html
char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3; fmv.x.d s6, ft0 // We have to enable mstatus.fs
char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3;
// fmv.x.d s6, ft0
uint64_t r_ft0 = 0x12341234; uint64_t r_ft0 = 0x12341234;
uint64_t r_s6 = 0x56785678; uint64_t r_s6 = 0x56785678;
uint64_t r_x3 = 0x6000; uint64_t r_x3 = 0x6000;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1); uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers // initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0)); OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6)); OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
// mstatus.fs
OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
// emulate the instruction // mstatus.fs
OK(uc_emu_start(uc, code_start, -1, 0, 2)); OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0)); // emulate the instruction
OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6)); OK(uc_emu_start(uc, code_start, -1, 0, 2));
TEST_CHECK(r_ft0 == 0x12341234); OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
TEST_CHECK(r_s6 == 0x12341234); OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
uc_close(uc); TEST_CHECK(r_ft0 == 0x12341234);
TEST_CHECK(r_s6 == 0x12341234);
uc_close(uc);
} }
TEST_LIST = { TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
{ "test_riscv32_nop", test_riscv32_nop }, {"test_riscv64_nop", test_riscv64_nop},
{ "test_riscv64_nop", test_riscv64_nop }, {"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
{ "test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update }, {"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
{ "test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update }, {"test_riscv32_until_pc_update", test_riscv32_until_pc_update},
{ "test_riscv32_until_pc_update", test_riscv32_until_pc_update }, {"test_riscv64_until_pc_update", test_riscv64_until_pc_update},
{ "test_riscv64_until_pc_update", test_riscv64_until_pc_update }, {"test_riscv32_fp_move", test_riscv32_fp_move},
{ "test_riscv32_fp_move", test_riscv32_fp_move }, {"test_riscv64_fp_move", test_riscv64_fp_move},
{ "test_riscv64_fp_move", test_riscv64_fp_move }, {"test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int},
{ "test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int }, {"test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int},
{ "test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int }, {NULL, NULL}};
{ NULL, NULL }
};