From 65614075d23a53664f901f85e845c75a2dbc7d5d Mon Sep 17 00:00:00 2001 From: Chen Huitao Date: Wed, 26 Feb 2020 17:58:19 +0800 Subject: [PATCH] fix some oss-fuzz (#1213) * fix oss-fuzz 18138. * fix oss-fuzz 20079. * fix oss-fuzz 20209. * fix oss-fuzz 20210. * fix oss-fuzz 20262. * rollback. * rollback. * fix oss-fuzz 20079. * fix oss-fuzz 20179. * fix oss-fuzz 20195. * fix oss-fuzz 20206. * fix oss-fuzz 20207. * fix oss-fuzz 20265. * fix oss-fuzz 20285. * fix oss-fuzz 20868. --- qemu/include/qemu/bitops.h | 2 +- qemu/target-mips/translate.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/qemu/include/qemu/bitops.h b/qemu/include/qemu/bitops.h index 4ae468e3..b523df9d 100644 --- a/qemu/include/qemu/bitops.h +++ b/qemu/include/qemu/bitops.h @@ -242,7 +242,7 @@ static inline uint32_t rol32(uint32_t word, unsigned int shift) */ static inline uint32_t ror32(uint32_t word, unsigned int shift) { - return (word >> shift) | (word << (32 - shift)); + return (word >> shift) | (word << ((32 - shift) & 0x1f)); } /** diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index ad8e3093..656a67b6 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -3217,14 +3217,14 @@ static inline void gen_pcrel(DisasContext *ctx, int rs, int16_t imm) switch (MASK_OPC_PCREL_TOP5BITS(ctx->opcode)) { case OPC_AUIPC: if (rs != 0) { - offset = imm << 16; + offset = ((target_ulong)imm) << 16; addr = addr_add(ctx, ctx->pc, offset); tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr); } break; case OPC_ALUIPC: if (rs != 0) { - offset = imm << 16; + offset = ((target_ulong)imm) << 16; addr = ~0xFFFF & addr_add(ctx, ctx->pc, offset); tcg_gen_movi_tl(tcg_ctx, *cpu_gpr[rs], addr); }