diff --git a/bindings/rust/src/lib.rs b/bindings/rust/src/lib.rs
index 197d3c9d..b2a82252 100644
--- a/bindings/rust/src/lib.rs
+++ b/bindings/rust/src/lib.rs
@@ -10,19 +10,18 @@
 //! use unicorn_engine::unicorn_const::{Arch, Mode, Permission, SECOND_SCALE};
 //!
 //! fn emulate() {
-//!     let arm_code32: Vec<u8> = vec![0x17, 0x00, 0x40, 0xe2]; // sub r0, #23
+//!     let arm_code32 = [0x17, 0x00, 0x40, 0xe2]; // sub r0, #23
 //!
-//!     let mut unicorn = unicorn_engine::Unicorn::new(Arch::ARM, Mode::LITTLE_ENDIAN).expect("failed to initialize Unicorn instance");
-//!     let mut emu = unicorn.borrow();
+//!     let mut emu = unicorn_engine::Unicorn::new(Arch::ARM, Mode::LITTLE_ENDIAN).expect("failed to initialize Unicorn instance");
 //!     emu.mem_map(0x1000, 0x4000, Permission::ALL).expect("failed to map code page");
 //!     emu.mem_write(0x1000, &arm_code32).expect("failed to write instructions");
 //!
-//!     emu.reg_write(RegisterARM::R0 as i32, 123).expect("failed write R0");
-//!     emu.reg_write(RegisterARM::R5 as i32, 1337).expect("failed write R5");
+//!     emu.reg_write(RegisterARM::R0, 123).expect("failed write R0");
+//!     emu.reg_write(RegisterARM::R5, 1337).expect("failed write R5");
 //!
-//!     let _ = emu.emu_start(0x1000, (0x1000 + arm_code32.len()) as u64, 10 * SECOND_SCALE, 1000);
-//!     assert_eq!(emu.reg_read(RegisterARM::R0 as i32), Ok(100));
-//!     assert_eq!(emu.reg_read(RegisterARM::R5 as i32), Ok(1337));
+//!     emu.emu_start(0x1000, (0x1000 + arm_code32.len()) as u64, 10 * SECOND_SCALE, 1000).unwrap();
+//!     assert_eq!(emu.reg_read(RegisterARM::R0), Ok(100));
+//!     assert_eq!(emu.reg_read(RegisterARM::R5), Ok(1337));
 //! }
 //! ```
 //!