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bindings: update const_generator.py, and update all binding constants

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This commit is contained in:
Nguyen Anh Quynh
2022-01-01 09:24:28 +08:00
parent 57699b69bb
commit 6813e4a042
21 changed files with 1679 additions and 386 deletions
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18
bindings/pascal/unicorn/M68kConst.pas
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@ -7,15 +7,15 @@ interface
const
// M68K CPU
UC_CPU_M5206_CPU = 0;
UC_CPU_M68000_CPU = 1;
UC_CPU_M68020_CPU = 2;
UC_CPU_M68030_CPU = 3;
UC_CPU_M68040_CPU = 4;
UC_CPU_M68060_CPU = 5;
UC_CPU_M5208_CPU = 6;
UC_CPU_CFV4E_CPU = 7;
UC_CPU_ANY_CPU = 8;
UC_CPU_M68K_M5206 = 0;
UC_CPU_M68K_M68000 = 1;
UC_CPU_M68K_M68020 = 2;
UC_CPU_M68K_M68030 = 3;
UC_CPU_M68K_M68040 = 4;
UC_CPU_M68K_M68060 = 5;
UC_CPU_M68K_M5208 = 6;
UC_CPU_M68K_CFV4E = 7;
UC_CPU_M68K_ANY = 8;
// M68K registers

259
bindings/pascal/unicorn/RiscvConst.pas
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@ -57,41 +57,168 @@ const
UC_RISCV_REG_X30 = 31;
UC_RISCV_REG_X31 = 32;
// RISCV CSR
UC_RISCV_REG_USTATUS = 33;
UC_RISCV_REG_UIE = 34;
UC_RISCV_REG_UTVEC = 35;
UC_RISCV_REG_USCRATCH = 36;
UC_RISCV_REG_UEPC = 37;
UC_RISCV_REG_UCAUSE = 38;
UC_RISCV_REG_UTVAL = 39;
UC_RISCV_REG_UIP = 40;
UC_RISCV_REG_FFLAGS = 41;
UC_RISCV_REG_FRM = 42;
UC_RISCV_REG_FCSR = 43;
UC_RISCV_REG_CYCLE = 44;
UC_RISCV_REG_TIME = 45;
UC_RISCV_REG_INSTRET = 46;
UC_RISCV_REG_HPMCOUNTER3 = 47;
UC_RISCV_REG_HPMCOUNTER4 = 48;
UC_RISCV_REG_HPMCOUNTER5 = 49;
UC_RISCV_REG_HPMCOUNTER6 = 50;
UC_RISCV_REG_HPMCOUNTER7 = 51;
UC_RISCV_REG_HPMCOUNTER8 = 52;
UC_RISCV_REG_HPMCOUNTER9 = 53;
UC_RISCV_REG_HPMCOUNTER10 = 54;
UC_RISCV_REG_HPMCOUNTER11 = 55;
UC_RISCV_REG_HPMCOUNTER12 = 56;
UC_RISCV_REG_HPMCOUNTER13 = 57;
UC_RISCV_REG_HPMCOUNTER14 = 58;
UC_RISCV_REG_HPMCOUNTER15 = 59;
UC_RISCV_REG_HPMCOUNTER16 = 60;
UC_RISCV_REG_HPMCOUNTER17 = 61;
UC_RISCV_REG_HPMCOUNTER18 = 62;
UC_RISCV_REG_HPMCOUNTER19 = 63;
UC_RISCV_REG_HPMCOUNTER20 = 64;
UC_RISCV_REG_HPMCOUNTER21 = 65;
UC_RISCV_REG_HPMCOUNTER22 = 66;
UC_RISCV_REG_HPMCOUNTER23 = 67;
UC_RISCV_REG_HPMCOUNTER24 = 68;
UC_RISCV_REG_HPMCOUNTER25 = 69;
UC_RISCV_REG_HPMCOUNTER26 = 70;
UC_RISCV_REG_HPMCOUNTER27 = 71;
UC_RISCV_REG_HPMCOUNTER28 = 72;
UC_RISCV_REG_HPMCOUNTER29 = 73;
UC_RISCV_REG_HPMCOUNTER30 = 74;
UC_RISCV_REG_HPMCOUNTER31 = 75;
UC_RISCV_REG_CYCLEH = 76;
UC_RISCV_REG_TIMEH = 77;
UC_RISCV_REG_INSTRETH = 78;
UC_RISCV_REG_HPMCOUNTER3H = 79;
UC_RISCV_REG_HPMCOUNTER4H = 80;
UC_RISCV_REG_HPMCOUNTER5H = 81;
UC_RISCV_REG_HPMCOUNTER6H = 82;
UC_RISCV_REG_HPMCOUNTER7H = 83;
UC_RISCV_REG_HPMCOUNTER8H = 84;
UC_RISCV_REG_HPMCOUNTER9H = 85;
UC_RISCV_REG_HPMCOUNTER10H = 86;
UC_RISCV_REG_HPMCOUNTER11H = 87;
UC_RISCV_REG_HPMCOUNTER12H = 88;
UC_RISCV_REG_HPMCOUNTER13H = 89;
UC_RISCV_REG_HPMCOUNTER14H = 90;
UC_RISCV_REG_HPMCOUNTER15H = 91;
UC_RISCV_REG_HPMCOUNTER16H = 92;
UC_RISCV_REG_HPMCOUNTER17H = 93;
UC_RISCV_REG_HPMCOUNTER18H = 94;
UC_RISCV_REG_HPMCOUNTER19H = 95;
UC_RISCV_REG_HPMCOUNTER20H = 96;
UC_RISCV_REG_HPMCOUNTER21H = 97;
UC_RISCV_REG_HPMCOUNTER22H = 98;
UC_RISCV_REG_HPMCOUNTER23H = 99;
UC_RISCV_REG_HPMCOUNTER24H = 100;
UC_RISCV_REG_HPMCOUNTER25H = 101;
UC_RISCV_REG_HPMCOUNTER26H = 102;
UC_RISCV_REG_HPMCOUNTER27H = 103;
UC_RISCV_REG_HPMCOUNTER28H = 104;
UC_RISCV_REG_HPMCOUNTER29H = 105;
UC_RISCV_REG_HPMCOUNTER30H = 106;
UC_RISCV_REG_HPMCOUNTER31H = 107;
UC_RISCV_REG_MCYCLE = 108;
UC_RISCV_REG_MINSTRET = 109;
UC_RISCV_REG_MCYCLEH = 110;
UC_RISCV_REG_MINSTRETH = 111;
UC_RISCV_REG_MVENDORID = 112;
UC_RISCV_REG_MARCHID = 113;
UC_RISCV_REG_MIMPID = 114;
UC_RISCV_REG_MHARTID = 115;
UC_RISCV_REG_MSTATUS = 116;
UC_RISCV_REG_MISA = 117;
UC_RISCV_REG_MEDELEG = 118;
UC_RISCV_REG_MIDELEG = 119;
UC_RISCV_REG_MIE = 120;
UC_RISCV_REG_MTVEC = 121;
UC_RISCV_REG_MCOUNTEREN = 122;
UC_RISCV_REG_MSTATUSH = 123;
UC_RISCV_REG_MUCOUNTEREN = 124;
UC_RISCV_REG_MSCOUNTEREN = 125;
UC_RISCV_REG_MHCOUNTEREN = 126;
UC_RISCV_REG_MSCRATCH = 127;
UC_RISCV_REG_MEPC = 128;
UC_RISCV_REG_MCAUSE = 129;
UC_RISCV_REG_MTVAL = 130;
UC_RISCV_REG_MIP = 131;
UC_RISCV_REG_MBADADDR = 132;
UC_RISCV_REG_SSTATUS = 133;
UC_RISCV_REG_SEDELEG = 134;
UC_RISCV_REG_SIDELEG = 135;
UC_RISCV_REG_SIE = 136;
UC_RISCV_REG_STVEC = 137;
UC_RISCV_REG_SCOUNTEREN = 138;
UC_RISCV_REG_SSCRATCH = 139;
UC_RISCV_REG_SEPC = 140;
UC_RISCV_REG_SCAUSE = 141;
UC_RISCV_REG_STVAL = 142;
UC_RISCV_REG_SIP = 143;
UC_RISCV_REG_SBADADDR = 144;
UC_RISCV_REG_SPTBR = 145;
UC_RISCV_REG_SATP = 146;
UC_RISCV_REG_HSTATUS = 147;
UC_RISCV_REG_HEDELEG = 148;
UC_RISCV_REG_HIDELEG = 149;
UC_RISCV_REG_HIE = 150;
UC_RISCV_REG_HCOUNTEREN = 151;
UC_RISCV_REG_HTVAL = 152;
UC_RISCV_REG_HIP = 153;
UC_RISCV_REG_HTINST = 154;
UC_RISCV_REG_HGATP = 155;
UC_RISCV_REG_HTIMEDELTA = 156;
UC_RISCV_REG_HTIMEDELTAH = 157;
// Floating-point registers
UC_RISCV_REG_F0 = 33;
UC_RISCV_REG_F1 = 34;
UC_RISCV_REG_F2 = 35;
UC_RISCV_REG_F3 = 36;
UC_RISCV_REG_F4 = 37;
UC_RISCV_REG_F5 = 38;
UC_RISCV_REG_F6 = 39;
UC_RISCV_REG_F7 = 40;
UC_RISCV_REG_F8 = 41;
UC_RISCV_REG_F9 = 42;
UC_RISCV_REG_F10 = 43;
UC_RISCV_REG_F11 = 44;
UC_RISCV_REG_F12 = 45;
UC_RISCV_REG_F13 = 46;
UC_RISCV_REG_F14 = 47;
UC_RISCV_REG_F15 = 48;
UC_RISCV_REG_F16 = 49;
UC_RISCV_REG_F17 = 50;
UC_RISCV_REG_F18 = 51;
UC_RISCV_REG_F19 = 52;
UC_RISCV_REG_F20 = 53;
UC_RISCV_REG_F21 = 54;
UC_RISCV_REG_F22 = 55;
UC_RISCV_REG_F23 = 56;
UC_RISCV_REG_F24 = 57;
UC_RISCV_REG_F25 = 58;
UC_RISCV_REG_F26 = 59;
UC_RISCV_REG_F27 = 60;
UC_RISCV_REG_F28 = 61;
UC_RISCV_REG_F29 = 62;
UC_RISCV_REG_F30 = 63;
UC_RISCV_REG_F31 = 64;
UC_RISCV_REG_PC = 65;
UC_RISCV_REG_ENDING = 66;
UC_RISCV_REG_F0 = 158;
UC_RISCV_REG_F1 = 159;
UC_RISCV_REG_F2 = 160;
UC_RISCV_REG_F3 = 161;
UC_RISCV_REG_F4 = 162;
UC_RISCV_REG_F5 = 163;
UC_RISCV_REG_F6 = 164;
UC_RISCV_REG_F7 = 165;
UC_RISCV_REG_F8 = 166;
UC_RISCV_REG_F9 = 167;
UC_RISCV_REG_F10 = 168;
UC_RISCV_REG_F11 = 169;
UC_RISCV_REG_F12 = 170;
UC_RISCV_REG_F13 = 171;
UC_RISCV_REG_F14 = 172;
UC_RISCV_REG_F15 = 173;
UC_RISCV_REG_F16 = 174;
UC_RISCV_REG_F17 = 175;
UC_RISCV_REG_F18 = 176;
UC_RISCV_REG_F19 = 177;
UC_RISCV_REG_F20 = 178;
UC_RISCV_REG_F21 = 179;
UC_RISCV_REG_F22 = 180;
UC_RISCV_REG_F23 = 181;
UC_RISCV_REG_F24 = 182;
UC_RISCV_REG_F25 = 183;
UC_RISCV_REG_F26 = 184;
UC_RISCV_REG_F27 = 185;
UC_RISCV_REG_F28 = 186;
UC_RISCV_REG_F29 = 187;
UC_RISCV_REG_F30 = 188;
UC_RISCV_REG_F31 = 189;
UC_RISCV_REG_PC = 190;
UC_RISCV_REG_ENDING = 191;
// Alias registers
UC_RISCV_REG_ZERO = 1;
@ -127,38 +254,38 @@ const
UC_RISCV_REG_T4 = 30;
UC_RISCV_REG_T5 = 31;
UC_RISCV_REG_T6 = 32;
UC_RISCV_REG_FT0 = 33;
UC_RISCV_REG_FT1 = 34;
UC_RISCV_REG_FT2 = 35;
UC_RISCV_REG_FT3 = 36;
UC_RISCV_REG_FT4 = 37;
UC_RISCV_REG_FT5 = 38;
UC_RISCV_REG_FT6 = 39;
UC_RISCV_REG_FT7 = 40;
UC_RISCV_REG_FS0 = 41;
UC_RISCV_REG_FS1 = 42;
UC_RISCV_REG_FA0 = 43;
UC_RISCV_REG_FA1 = 44;
UC_RISCV_REG_FA2 = 45;
UC_RISCV_REG_FA3 = 46;
UC_RISCV_REG_FA4 = 47;
UC_RISCV_REG_FA5 = 48;
UC_RISCV_REG_FA6 = 49;
UC_RISCV_REG_FA7 = 50;
UC_RISCV_REG_FS2 = 51;
UC_RISCV_REG_FS3 = 52;
UC_RISCV_REG_FS4 = 53;
UC_RISCV_REG_FS5 = 54;
UC_RISCV_REG_FS6 = 55;
UC_RISCV_REG_FS7 = 56;
UC_RISCV_REG_FS8 = 57;
UC_RISCV_REG_FS9 = 58;
UC_RISCV_REG_FS10 = 59;
UC_RISCV_REG_FS11 = 60;
UC_RISCV_REG_FT8 = 61;
UC_RISCV_REG_FT9 = 62;
UC_RISCV_REG_FT10 = 63;
UC_RISCV_REG_FT11 = 64;
UC_RISCV_REG_FT0 = 158;
UC_RISCV_REG_FT1 = 159;
UC_RISCV_REG_FT2 = 160;
UC_RISCV_REG_FT3 = 161;
UC_RISCV_REG_FT4 = 162;
UC_RISCV_REG_FT5 = 163;
UC_RISCV_REG_FT6 = 164;
UC_RISCV_REG_FT7 = 165;
UC_RISCV_REG_FS0 = 166;
UC_RISCV_REG_FS1 = 167;
UC_RISCV_REG_FA0 = 168;
UC_RISCV_REG_FA1 = 169;
UC_RISCV_REG_FA2 = 170;
UC_RISCV_REG_FA3 = 171;
UC_RISCV_REG_FA4 = 172;
UC_RISCV_REG_FA5 = 173;
UC_RISCV_REG_FA6 = 174;
UC_RISCV_REG_FA7 = 175;
UC_RISCV_REG_FS2 = 176;
UC_RISCV_REG_FS3 = 177;
UC_RISCV_REG_FS4 = 178;
UC_RISCV_REG_FS5 = 179;
UC_RISCV_REG_FS6 = 180;
UC_RISCV_REG_FS7 = 181;
UC_RISCV_REG_FS8 = 182;
UC_RISCV_REG_FS9 = 183;
UC_RISCV_REG_FS10 = 184;
UC_RISCV_REG_FS11 = 185;
UC_RISCV_REG_FT8 = 186;
UC_RISCV_REG_FT9 = 187;
UC_RISCV_REG_FT10 = 188;
UC_RISCV_REG_FT11 = 189;
implementation
end.

128
bindings/pascal/unicorn/S390xConst.pas Normal file
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@ -0,0 +1,128 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
unit S390xConst;
interface
const
// S390X CPU
UC_CPU_S390X_Z900 = 0;
UC_CPU_S390X_Z900_2 = 1;
UC_CPU_S390X_Z900_3 = 2;
UC_CPU_S390X_Z800 = 3;
UC_CPU_S390X_Z990 = 4;
UC_CPU_S390X_Z990_2 = 5;
UC_CPU_S390X_Z990_3 = 6;
UC_CPU_S390X_Z890 = 7;
UC_CPU_S390X_Z990_4 = 8;
UC_CPU_S390X_Z890_2 = 9;
UC_CPU_S390X_Z990_5 = 10;
UC_CPU_S390X_Z890_3 = 11;
UC_CPU_S390X_Z9EC = 12;
UC_CPU_S390X_Z9EC_2 = 13;
UC_CPU_S390X_Z9BC = 14;
UC_CPU_S390X_Z9EC_3 = 15;
UC_CPU_S390X_Z9BC_2 = 16;
UC_CPU_S390X_Z10EC = 17;
UC_CPU_S390X_Z10EC_2 = 18;
UC_CPU_S390X_Z10BC = 19;
UC_CPU_S390X_Z10EC_3 = 20;
UC_CPU_S390X_Z10BC_2 = 21;
UC_CPU_S390X_Z196 = 22;
UC_CPU_S390X_Z196_2 = 23;
UC_CPU_S390X_Z114 = 24;
UC_CPU_S390X_ZEC12 = 25;
UC_CPU_S390X_ZEC12_2 = 26;
UC_CPU_S390X_ZBC12 = 27;
UC_CPU_S390X_Z13 = 28;
UC_CPU_S390X_Z13_2 = 29;
UC_CPU_S390X_Z13S = 30;
UC_CPU_S390X_Z14 = 31;
UC_CPU_S390X_Z14_2 = 32;
UC_CPU_S390X_Z14ZR1 = 33;
UC_CPU_S390X_GEN15A = 34;
UC_CPU_S390X_GEN15B = 35;
UC_CPU_S390X_QEMU = 36;
UC_CPU_S390X_MAX = 37;
// S390X registers
UC_S390X_REG_INVALID = 0;
// General purpose registers
UC_S390X_REG_R0 = 1;
UC_S390X_REG_R1 = 2;
UC_S390X_REG_R2 = 3;
UC_S390X_REG_R3 = 4;
UC_S390X_REG_R4 = 5;
UC_S390X_REG_R5 = 6;
UC_S390X_REG_R6 = 7;
UC_S390X_REG_R7 = 8;
UC_S390X_REG_R8 = 9;
UC_S390X_REG_R9 = 10;
UC_S390X_REG_R10 = 11;
UC_S390X_REG_R11 = 12;
UC_S390X_REG_R12 = 13;
UC_S390X_REG_R13 = 14;
UC_S390X_REG_R14 = 15;
UC_S390X_REG_R15 = 16;
// Floating point registers
UC_S390X_REG_F0 = 17;
UC_S390X_REG_F1 = 18;
UC_S390X_REG_F2 = 19;
UC_S390X_REG_F3 = 20;
UC_S390X_REG_F4 = 21;
UC_S390X_REG_F5 = 22;
UC_S390X_REG_F6 = 23;
UC_S390X_REG_F7 = 24;
UC_S390X_REG_F8 = 25;
UC_S390X_REG_F9 = 26;
UC_S390X_REG_F10 = 27;
UC_S390X_REG_F11 = 28;
UC_S390X_REG_F12 = 29;
UC_S390X_REG_F13 = 30;
UC_S390X_REG_F14 = 31;
UC_S390X_REG_F15 = 32;
UC_S390X_REG_F16 = 33;
UC_S390X_REG_F17 = 34;
UC_S390X_REG_F18 = 35;
UC_S390X_REG_F19 = 36;
UC_S390X_REG_F20 = 37;
UC_S390X_REG_F21 = 38;
UC_S390X_REG_F22 = 39;
UC_S390X_REG_F23 = 40;
UC_S390X_REG_F24 = 41;
UC_S390X_REG_F25 = 42;
UC_S390X_REG_F26 = 43;
UC_S390X_REG_F27 = 44;
UC_S390X_REG_F28 = 45;
UC_S390X_REG_F29 = 46;
UC_S390X_REG_F30 = 47;
UC_S390X_REG_F31 = 48;
// Access registers
UC_S390X_REG_A0 = 49;
UC_S390X_REG_A1 = 50;
UC_S390X_REG_A2 = 51;
UC_S390X_REG_A3 = 52;
UC_S390X_REG_A4 = 53;
UC_S390X_REG_A5 = 54;
UC_S390X_REG_A6 = 55;
UC_S390X_REG_A7 = 56;
UC_S390X_REG_A8 = 57;
UC_S390X_REG_A9 = 58;
UC_S390X_REG_A10 = 59;
UC_S390X_REG_A11 = 60;
UC_S390X_REG_A12 = 61;
UC_S390X_REG_A13 = 62;
UC_S390X_REG_A14 = 63;
UC_S390X_REG_A15 = 64;
UC_S390X_REG_PC = 65;
UC_S390X_REG_ENDING = 66;
// Alias registers
implementation
end.

9
bindings/pascal/unicorn/UnicornConst.pas
View File

@ -7,11 +7,15 @@ interface
const UC_API_MAJOR = 2;
UC_API_MINOR = 0;
UC_API_PATCH = 0;
UC_API_EXTRA = 5;
UC_VERSION_MAJOR = 2;
UC_VERSION_MINOR = 0;
UC_VERSION_EXTRA = 0;
UC_VERSION_PATCH = 0;
UC_VERSION_EXTRA = 5;
UC_SECOND_SCALE = 1000000;
UC_MILISECOND_SCALE = 1000;
UC_ARCH_ARM = 1;
@ -22,7 +26,8 @@ const UC_API_MAJOR = 2;
UC_ARCH_SPARC = 6;
UC_ARCH_M68K = 7;
UC_ARCH_RISCV = 8;
UC_ARCH_MAX = 9;
UC_ARCH_S390X = 9;
UC_ARCH_MAX = 10;
UC_MODE_LITTLE_ENDIAN = 0;
UC_MODE_BIG_ENDIAN = 1073741824;