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bindings: update const_generator.py, and update all binding constants

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This commit is contained in:
Nguyen Anh Quynh
2022-01-01 09:24:28 +08:00
parent 57699b69bb
commit 6813e4a042
21 changed files with 1679 additions and 386 deletions
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7
bindings/const_generator.py
View File

@ -23,7 +23,7 @@ template = {
'm68k.h': 'm68k', 'm68k.h': 'm68k',
'ppc.h': 'ppc', 'ppc.h': 'ppc',
'riscv.h': 'riscv', 'riscv.h': 'riscv',
's390x.h' : "s390x", 's390x.h' : 's390x',
'unicorn.h': 'unicorn', 'unicorn.h': 'unicorn',
'comment_open': '#', 'comment_open': '#',
'comment_close': '', 'comment_close': '',
@ -42,6 +42,7 @@ template = {
'm68k.h': 'm68k', 'm68k.h': 'm68k',
'ppc.h': 'ppc', 'ppc.h': 'ppc',
'riscv.h': 'riscv', 'riscv.h': 'riscv',
's390x.h' : 's390x',
'unicorn.h': 'unicorn', 'unicorn.h': 'unicorn',
'comment_open': '#', 'comment_open': '#',
'comment_close': '', 'comment_close': '',
@ -60,6 +61,7 @@ template = {
'm68k.h': 'm68k', 'm68k.h': 'm68k',
'ppc.h': 'ppc', 'ppc.h': 'ppc',
'riscv.h': 'riscv', 'riscv.h': 'riscv',
's390x.h' : 's390x',
'unicorn.h': 'unicorn', 'unicorn.h': 'unicorn',
'comment_open': '//', 'comment_open': '//',
'comment_close': '', 'comment_close': '',
@ -78,6 +80,7 @@ template = {
'm68k.h': 'M68k', 'm68k.h': 'M68k',
'ppc.h': 'Ppc', 'ppc.h': 'Ppc',
'riscv.h': 'Riscv', 'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'unicorn.h': 'Unicorn', 'unicorn.h': 'Unicorn',
'comment_open': '//', 'comment_open': '//',
'comment_close': '', 'comment_close': '',
@ -96,6 +99,7 @@ template = {
'm68k.h': 'M68k', 'm68k.h': 'M68k',
'ppc.h': 'Ppc', 'ppc.h': 'Ppc',
'riscv.h': 'Riscv', 'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'unicorn.h': 'Common', 'unicorn.h': 'Common',
'comment_open': ' //', 'comment_open': ' //',
'comment_close': '', 'comment_close': '',
@ -114,6 +118,7 @@ template = {
'm68k.h': 'M68k', 'm68k.h': 'M68k',
'ppc.h': 'Ppc', 'ppc.h': 'Ppc',
'riscv.h': 'Riscv', 'riscv.h': 'Riscv',
's390x.h' : 'S390x',
'unicorn.h': 'Unicorn', 'unicorn.h': 'Unicorn',
'comment_open': '//', 'comment_open': '//',
'comment_close': '', 'comment_close': '',

9
bindings/dotnet/UnicornManaged/Const/Common.fs
View File

@ -9,11 +9,15 @@ module Common =
let UC_API_MAJOR = 2 let UC_API_MAJOR = 2
let UC_API_MINOR = 0 let UC_API_MINOR = 0
let UC_API_PATCH = 0
let UC_API_EXTRA = 5
let UC_VERSION_MAJOR = 2 let UC_VERSION_MAJOR = 2
let UC_VERSION_MINOR = 0 let UC_VERSION_MINOR = 0
let UC_VERSION_EXTRA = 0 let UC_VERSION_PATCH = 0
let UC_VERSION_EXTRA = 5
let UC_SECOND_SCALE = 1000000 let UC_SECOND_SCALE = 1000000
let UC_MILISECOND_SCALE = 1000 let UC_MILISECOND_SCALE = 1000
let UC_ARCH_ARM = 1 let UC_ARCH_ARM = 1
@ -24,7 +28,8 @@ module Common =
let UC_ARCH_SPARC = 6 let UC_ARCH_SPARC = 6
let UC_ARCH_M68K = 7 let UC_ARCH_M68K = 7
let UC_ARCH_RISCV = 8 let UC_ARCH_RISCV = 8
let UC_ARCH_MAX = 9 let UC_ARCH_S390X = 9
let UC_ARCH_MAX = 10
let UC_MODE_LITTLE_ENDIAN = 0 let UC_MODE_LITTLE_ENDIAN = 0
let UC_MODE_BIG_ENDIAN = 1073741824 let UC_MODE_BIG_ENDIAN = 1073741824

18
bindings/dotnet/UnicornManaged/Const/M68k.fs
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@ -9,15 +9,15 @@ module M68k =
// M68K CPU // M68K CPU
let UC_CPU_M5206_CPU = 0 let UC_CPU_M68K_M5206 = 0
let UC_CPU_M68000_CPU = 1 let UC_CPU_M68K_M68000 = 1
let UC_CPU_M68020_CPU = 2 let UC_CPU_M68K_M68020 = 2
let UC_CPU_M68030_CPU = 3 let UC_CPU_M68K_M68030 = 3
let UC_CPU_M68040_CPU = 4 let UC_CPU_M68K_M68040 = 4
let UC_CPU_M68060_CPU = 5 let UC_CPU_M68K_M68060 = 5
let UC_CPU_M5208_CPU = 6 let UC_CPU_M68K_M5208 = 6
let UC_CPU_CFV4E_CPU = 7 let UC_CPU_M68K_CFV4E = 7
let UC_CPU_ANY_CPU = 8 let UC_CPU_M68K_ANY = 8
// M68K registers // M68K registers

259
bindings/dotnet/UnicornManaged/Const/Riscv.fs
View File

@ -59,41 +59,168 @@ module Riscv =
let UC_RISCV_REG_X30 = 31 let UC_RISCV_REG_X30 = 31
let UC_RISCV_REG_X31 = 32 let UC_RISCV_REG_X31 = 32
// RISCV CSR
let UC_RISCV_REG_USTATUS = 33
let UC_RISCV_REG_UIE = 34
let UC_RISCV_REG_UTVEC = 35
let UC_RISCV_REG_USCRATCH = 36
let UC_RISCV_REG_UEPC = 37
let UC_RISCV_REG_UCAUSE = 38
let UC_RISCV_REG_UTVAL = 39
let UC_RISCV_REG_UIP = 40
let UC_RISCV_REG_FFLAGS = 41
let UC_RISCV_REG_FRM = 42
let UC_RISCV_REG_FCSR = 43
let UC_RISCV_REG_CYCLE = 44
let UC_RISCV_REG_TIME = 45
let UC_RISCV_REG_INSTRET = 46
let UC_RISCV_REG_HPMCOUNTER3 = 47
let UC_RISCV_REG_HPMCOUNTER4 = 48
let UC_RISCV_REG_HPMCOUNTER5 = 49
let UC_RISCV_REG_HPMCOUNTER6 = 50
let UC_RISCV_REG_HPMCOUNTER7 = 51
let UC_RISCV_REG_HPMCOUNTER8 = 52
let UC_RISCV_REG_HPMCOUNTER9 = 53
let UC_RISCV_REG_HPMCOUNTER10 = 54
let UC_RISCV_REG_HPMCOUNTER11 = 55
let UC_RISCV_REG_HPMCOUNTER12 = 56
let UC_RISCV_REG_HPMCOUNTER13 = 57
let UC_RISCV_REG_HPMCOUNTER14 = 58
let UC_RISCV_REG_HPMCOUNTER15 = 59
let UC_RISCV_REG_HPMCOUNTER16 = 60
let UC_RISCV_REG_HPMCOUNTER17 = 61
let UC_RISCV_REG_HPMCOUNTER18 = 62
let UC_RISCV_REG_HPMCOUNTER19 = 63
let UC_RISCV_REG_HPMCOUNTER20 = 64
let UC_RISCV_REG_HPMCOUNTER21 = 65
let UC_RISCV_REG_HPMCOUNTER22 = 66
let UC_RISCV_REG_HPMCOUNTER23 = 67
let UC_RISCV_REG_HPMCOUNTER24 = 68
let UC_RISCV_REG_HPMCOUNTER25 = 69
let UC_RISCV_REG_HPMCOUNTER26 = 70
let UC_RISCV_REG_HPMCOUNTER27 = 71
let UC_RISCV_REG_HPMCOUNTER28 = 72
let UC_RISCV_REG_HPMCOUNTER29 = 73
let UC_RISCV_REG_HPMCOUNTER30 = 74
let UC_RISCV_REG_HPMCOUNTER31 = 75
let UC_RISCV_REG_CYCLEH = 76
let UC_RISCV_REG_TIMEH = 77
let UC_RISCV_REG_INSTRETH = 78
let UC_RISCV_REG_HPMCOUNTER3H = 79
let UC_RISCV_REG_HPMCOUNTER4H = 80
let UC_RISCV_REG_HPMCOUNTER5H = 81
let UC_RISCV_REG_HPMCOUNTER6H = 82
let UC_RISCV_REG_HPMCOUNTER7H = 83
let UC_RISCV_REG_HPMCOUNTER8H = 84
let UC_RISCV_REG_HPMCOUNTER9H = 85
let UC_RISCV_REG_HPMCOUNTER10H = 86
let UC_RISCV_REG_HPMCOUNTER11H = 87
let UC_RISCV_REG_HPMCOUNTER12H = 88
let UC_RISCV_REG_HPMCOUNTER13H = 89
let UC_RISCV_REG_HPMCOUNTER14H = 90
let UC_RISCV_REG_HPMCOUNTER15H = 91
let UC_RISCV_REG_HPMCOUNTER16H = 92
let UC_RISCV_REG_HPMCOUNTER17H = 93
let UC_RISCV_REG_HPMCOUNTER18H = 94
let UC_RISCV_REG_HPMCOUNTER19H = 95
let UC_RISCV_REG_HPMCOUNTER20H = 96
let UC_RISCV_REG_HPMCOUNTER21H = 97
let UC_RISCV_REG_HPMCOUNTER22H = 98
let UC_RISCV_REG_HPMCOUNTER23H = 99
let UC_RISCV_REG_HPMCOUNTER24H = 100
let UC_RISCV_REG_HPMCOUNTER25H = 101
let UC_RISCV_REG_HPMCOUNTER26H = 102
let UC_RISCV_REG_HPMCOUNTER27H = 103
let UC_RISCV_REG_HPMCOUNTER28H = 104
let UC_RISCV_REG_HPMCOUNTER29H = 105
let UC_RISCV_REG_HPMCOUNTER30H = 106
let UC_RISCV_REG_HPMCOUNTER31H = 107
let UC_RISCV_REG_MCYCLE = 108
let UC_RISCV_REG_MINSTRET = 109
let UC_RISCV_REG_MCYCLEH = 110
let UC_RISCV_REG_MINSTRETH = 111
let UC_RISCV_REG_MVENDORID = 112
let UC_RISCV_REG_MARCHID = 113
let UC_RISCV_REG_MIMPID = 114
let UC_RISCV_REG_MHARTID = 115
let UC_RISCV_REG_MSTATUS = 116
let UC_RISCV_REG_MISA = 117
let UC_RISCV_REG_MEDELEG = 118
let UC_RISCV_REG_MIDELEG = 119
let UC_RISCV_REG_MIE = 120
let UC_RISCV_REG_MTVEC = 121
let UC_RISCV_REG_MCOUNTEREN = 122
let UC_RISCV_REG_MSTATUSH = 123
let UC_RISCV_REG_MUCOUNTEREN = 124
let UC_RISCV_REG_MSCOUNTEREN = 125
let UC_RISCV_REG_MHCOUNTEREN = 126
let UC_RISCV_REG_MSCRATCH = 127
let UC_RISCV_REG_MEPC = 128
let UC_RISCV_REG_MCAUSE = 129
let UC_RISCV_REG_MTVAL = 130
let UC_RISCV_REG_MIP = 131
let UC_RISCV_REG_MBADADDR = 132
let UC_RISCV_REG_SSTATUS = 133
let UC_RISCV_REG_SEDELEG = 134
let UC_RISCV_REG_SIDELEG = 135
let UC_RISCV_REG_SIE = 136
let UC_RISCV_REG_STVEC = 137
let UC_RISCV_REG_SCOUNTEREN = 138
let UC_RISCV_REG_SSCRATCH = 139
let UC_RISCV_REG_SEPC = 140
let UC_RISCV_REG_SCAUSE = 141
let UC_RISCV_REG_STVAL = 142
let UC_RISCV_REG_SIP = 143
let UC_RISCV_REG_SBADADDR = 144
let UC_RISCV_REG_SPTBR = 145
let UC_RISCV_REG_SATP = 146
let UC_RISCV_REG_HSTATUS = 147
let UC_RISCV_REG_HEDELEG = 148
let UC_RISCV_REG_HIDELEG = 149
let UC_RISCV_REG_HIE = 150
let UC_RISCV_REG_HCOUNTEREN = 151
let UC_RISCV_REG_HTVAL = 152
let UC_RISCV_REG_HIP = 153
let UC_RISCV_REG_HTINST = 154
let UC_RISCV_REG_HGATP = 155
let UC_RISCV_REG_HTIMEDELTA = 156
let UC_RISCV_REG_HTIMEDELTAH = 157
// Floating-point registers // Floating-point registers
let UC_RISCV_REG_F0 = 33 let UC_RISCV_REG_F0 = 158
let UC_RISCV_REG_F1 = 34 let UC_RISCV_REG_F1 = 159
let UC_RISCV_REG_F2 = 35 let UC_RISCV_REG_F2 = 160
let UC_RISCV_REG_F3 = 36 let UC_RISCV_REG_F3 = 161
let UC_RISCV_REG_F4 = 37 let UC_RISCV_REG_F4 = 162
let UC_RISCV_REG_F5 = 38 let UC_RISCV_REG_F5 = 163
let UC_RISCV_REG_F6 = 39 let UC_RISCV_REG_F6 = 164
let UC_RISCV_REG_F7 = 40 let UC_RISCV_REG_F7 = 165
let UC_RISCV_REG_F8 = 41 let UC_RISCV_REG_F8 = 166
let UC_RISCV_REG_F9 = 42 let UC_RISCV_REG_F9 = 167
let UC_RISCV_REG_F10 = 43 let UC_RISCV_REG_F10 = 168
let UC_RISCV_REG_F11 = 44 let UC_RISCV_REG_F11 = 169
let UC_RISCV_REG_F12 = 45 let UC_RISCV_REG_F12 = 170
let UC_RISCV_REG_F13 = 46 let UC_RISCV_REG_F13 = 171
let UC_RISCV_REG_F14 = 47 let UC_RISCV_REG_F14 = 172
let UC_RISCV_REG_F15 = 48 let UC_RISCV_REG_F15 = 173
let UC_RISCV_REG_F16 = 49 let UC_RISCV_REG_F16 = 174
let UC_RISCV_REG_F17 = 50 let UC_RISCV_REG_F17 = 175
let UC_RISCV_REG_F18 = 51 let UC_RISCV_REG_F18 = 176
let UC_RISCV_REG_F19 = 52 let UC_RISCV_REG_F19 = 177
let UC_RISCV_REG_F20 = 53 let UC_RISCV_REG_F20 = 178
let UC_RISCV_REG_F21 = 54 let UC_RISCV_REG_F21 = 179
let UC_RISCV_REG_F22 = 55 let UC_RISCV_REG_F22 = 180
let UC_RISCV_REG_F23 = 56 let UC_RISCV_REG_F23 = 181
let UC_RISCV_REG_F24 = 57 let UC_RISCV_REG_F24 = 182
let UC_RISCV_REG_F25 = 58 let UC_RISCV_REG_F25 = 183
let UC_RISCV_REG_F26 = 59 let UC_RISCV_REG_F26 = 184
let UC_RISCV_REG_F27 = 60 let UC_RISCV_REG_F27 = 185
let UC_RISCV_REG_F28 = 61 let UC_RISCV_REG_F28 = 186
let UC_RISCV_REG_F29 = 62 let UC_RISCV_REG_F29 = 187
let UC_RISCV_REG_F30 = 63 let UC_RISCV_REG_F30 = 188
let UC_RISCV_REG_F31 = 64 let UC_RISCV_REG_F31 = 189
let UC_RISCV_REG_PC = 65 let UC_RISCV_REG_PC = 190
let UC_RISCV_REG_ENDING = 66 let UC_RISCV_REG_ENDING = 191
// Alias registers // Alias registers
let UC_RISCV_REG_ZERO = 1 let UC_RISCV_REG_ZERO = 1
@ -129,36 +256,36 @@ module Riscv =
let UC_RISCV_REG_T4 = 30 let UC_RISCV_REG_T4 = 30
let UC_RISCV_REG_T5 = 31 let UC_RISCV_REG_T5 = 31
let UC_RISCV_REG_T6 = 32 let UC_RISCV_REG_T6 = 32
let UC_RISCV_REG_FT0 = 33 let UC_RISCV_REG_FT0 = 158
let UC_RISCV_REG_FT1 = 34 let UC_RISCV_REG_FT1 = 159
let UC_RISCV_REG_FT2 = 35 let UC_RISCV_REG_FT2 = 160
let UC_RISCV_REG_FT3 = 36 let UC_RISCV_REG_FT3 = 161
let UC_RISCV_REG_FT4 = 37 let UC_RISCV_REG_FT4 = 162
let UC_RISCV_REG_FT5 = 38 let UC_RISCV_REG_FT5 = 163
let UC_RISCV_REG_FT6 = 39 let UC_RISCV_REG_FT6 = 164
let UC_RISCV_REG_FT7 = 40 let UC_RISCV_REG_FT7 = 165
let UC_RISCV_REG_FS0 = 41 let UC_RISCV_REG_FS0 = 166
let UC_RISCV_REG_FS1 = 42 let UC_RISCV_REG_FS1 = 167
let UC_RISCV_REG_FA0 = 43 let UC_RISCV_REG_FA0 = 168
let UC_RISCV_REG_FA1 = 44 let UC_RISCV_REG_FA1 = 169
let UC_RISCV_REG_FA2 = 45 let UC_RISCV_REG_FA2 = 170
let UC_RISCV_REG_FA3 = 46 let UC_RISCV_REG_FA3 = 171
let UC_RISCV_REG_FA4 = 47 let UC_RISCV_REG_FA4 = 172
let UC_RISCV_REG_FA5 = 48 let UC_RISCV_REG_FA5 = 173
let UC_RISCV_REG_FA6 = 49 let UC_RISCV_REG_FA6 = 174
let UC_RISCV_REG_FA7 = 50 let UC_RISCV_REG_FA7 = 175
let UC_RISCV_REG_FS2 = 51 let UC_RISCV_REG_FS2 = 176
let UC_RISCV_REG_FS3 = 52 let UC_RISCV_REG_FS3 = 177
let UC_RISCV_REG_FS4 = 53 let UC_RISCV_REG_FS4 = 178
let UC_RISCV_REG_FS5 = 54 let UC_RISCV_REG_FS5 = 179
let UC_RISCV_REG_FS6 = 55 let UC_RISCV_REG_FS6 = 180
let UC_RISCV_REG_FS7 = 56 let UC_RISCV_REG_FS7 = 181
let UC_RISCV_REG_FS8 = 57 let UC_RISCV_REG_FS8 = 182
let UC_RISCV_REG_FS9 = 58 let UC_RISCV_REG_FS9 = 183
let UC_RISCV_REG_FS10 = 59 let UC_RISCV_REG_FS10 = 184
let UC_RISCV_REG_FS11 = 60 let UC_RISCV_REG_FS11 = 185
let UC_RISCV_REG_FT8 = 61 let UC_RISCV_REG_FT8 = 186
let UC_RISCV_REG_FT9 = 62 let UC_RISCV_REG_FT9 = 187
let UC_RISCV_REG_FT10 = 63 let UC_RISCV_REG_FT10 = 188
let UC_RISCV_REG_FT11 = 64 let UC_RISCV_REG_FT11 = 189

128
bindings/dotnet/UnicornManaged/Const/S390x.fs Normal file
View File

@ -0,0 +1,128 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
namespace UnicornManaged.Const
open System
[<AutoOpen>]
module S390x =
// S390X CPU
let UC_CPU_S390X_Z900 = 0
let UC_CPU_S390X_Z900_2 = 1
let UC_CPU_S390X_Z900_3 = 2
let UC_CPU_S390X_Z800 = 3
let UC_CPU_S390X_Z990 = 4
let UC_CPU_S390X_Z990_2 = 5
let UC_CPU_S390X_Z990_3 = 6
let UC_CPU_S390X_Z890 = 7
let UC_CPU_S390X_Z990_4 = 8
let UC_CPU_S390X_Z890_2 = 9
let UC_CPU_S390X_Z990_5 = 10
let UC_CPU_S390X_Z890_3 = 11
let UC_CPU_S390X_Z9EC = 12
let UC_CPU_S390X_Z9EC_2 = 13
let UC_CPU_S390X_Z9BC = 14
let UC_CPU_S390X_Z9EC_3 = 15
let UC_CPU_S390X_Z9BC_2 = 16
let UC_CPU_S390X_Z10EC = 17
let UC_CPU_S390X_Z10EC_2 = 18
let UC_CPU_S390X_Z10BC = 19
let UC_CPU_S390X_Z10EC_3 = 20
let UC_CPU_S390X_Z10BC_2 = 21
let UC_CPU_S390X_Z196 = 22
let UC_CPU_S390X_Z196_2 = 23
let UC_CPU_S390X_Z114 = 24
let UC_CPU_S390X_ZEC12 = 25
let UC_CPU_S390X_ZEC12_2 = 26
let UC_CPU_S390X_ZBC12 = 27
let UC_CPU_S390X_Z13 = 28
let UC_CPU_S390X_Z13_2 = 29
let UC_CPU_S390X_Z13S = 30
let UC_CPU_S390X_Z14 = 31
let UC_CPU_S390X_Z14_2 = 32
let UC_CPU_S390X_Z14ZR1 = 33
let UC_CPU_S390X_GEN15A = 34
let UC_CPU_S390X_GEN15B = 35
let UC_CPU_S390X_QEMU = 36
let UC_CPU_S390X_MAX = 37
// S390X registers
let UC_S390X_REG_INVALID = 0
// General purpose registers
let UC_S390X_REG_R0 = 1
let UC_S390X_REG_R1 = 2
let UC_S390X_REG_R2 = 3
let UC_S390X_REG_R3 = 4
let UC_S390X_REG_R4 = 5
let UC_S390X_REG_R5 = 6
let UC_S390X_REG_R6 = 7
let UC_S390X_REG_R7 = 8
let UC_S390X_REG_R8 = 9
let UC_S390X_REG_R9 = 10
let UC_S390X_REG_R10 = 11
let UC_S390X_REG_R11 = 12
let UC_S390X_REG_R12 = 13
let UC_S390X_REG_R13 = 14
let UC_S390X_REG_R14 = 15
let UC_S390X_REG_R15 = 16
// Floating point registers
let UC_S390X_REG_F0 = 17
let UC_S390X_REG_F1 = 18
let UC_S390X_REG_F2 = 19
let UC_S390X_REG_F3 = 20
let UC_S390X_REG_F4 = 21
let UC_S390X_REG_F5 = 22
let UC_S390X_REG_F6 = 23
let UC_S390X_REG_F7 = 24
let UC_S390X_REG_F8 = 25
let UC_S390X_REG_F9 = 26
let UC_S390X_REG_F10 = 27
let UC_S390X_REG_F11 = 28
let UC_S390X_REG_F12 = 29
let UC_S390X_REG_F13 = 30
let UC_S390X_REG_F14 = 31
let UC_S390X_REG_F15 = 32
let UC_S390X_REG_F16 = 33
let UC_S390X_REG_F17 = 34
let UC_S390X_REG_F18 = 35
let UC_S390X_REG_F19 = 36
let UC_S390X_REG_F20 = 37
let UC_S390X_REG_F21 = 38
let UC_S390X_REG_F22 = 39
let UC_S390X_REG_F23 = 40
let UC_S390X_REG_F24 = 41
let UC_S390X_REG_F25 = 42
let UC_S390X_REG_F26 = 43
let UC_S390X_REG_F27 = 44
let UC_S390X_REG_F28 = 45
let UC_S390X_REG_F29 = 46
let UC_S390X_REG_F30 = 47
let UC_S390X_REG_F31 = 48
// Access registers
let UC_S390X_REG_A0 = 49
let UC_S390X_REG_A1 = 50
let UC_S390X_REG_A2 = 51
let UC_S390X_REG_A3 = 52
let UC_S390X_REG_A4 = 53
let UC_S390X_REG_A5 = 54
let UC_S390X_REG_A6 = 55
let UC_S390X_REG_A7 = 56
let UC_S390X_REG_A8 = 57
let UC_S390X_REG_A9 = 58
let UC_S390X_REG_A10 = 59
let UC_S390X_REG_A11 = 60
let UC_S390X_REG_A12 = 61
let UC_S390X_REG_A13 = 62
let UC_S390X_REG_A14 = 63
let UC_S390X_REG_A15 = 64
let UC_S390X_REG_PC = 65
let UC_S390X_REG_ENDING = 66
// Alias registers

18
bindings/go/unicorn/m68k_const.go
View File

@ -4,15 +4,15 @@ const (
// M68K CPU // M68K CPU
CPU_M5206_CPU = 0 CPU_M68K_M5206 = 0
CPU_M68000_CPU = 1 CPU_M68K_M68000 = 1
CPU_M68020_CPU = 2 CPU_M68K_M68020 = 2
CPU_M68030_CPU = 3 CPU_M68K_M68030 = 3
CPU_M68040_CPU = 4 CPU_M68K_M68040 = 4
CPU_M68060_CPU = 5 CPU_M68K_M68060 = 5
CPU_M5208_CPU = 6 CPU_M68K_M5208 = 6
CPU_CFV4E_CPU = 7 CPU_M68K_CFV4E = 7
CPU_ANY_CPU = 8 CPU_M68K_ANY = 8
// M68K registers // M68K registers

259
bindings/go/unicorn/riscv_const.go
View File

@ -54,41 +54,168 @@ const (
RISCV_REG_X30 = 31 RISCV_REG_X30 = 31
RISCV_REG_X31 = 32 RISCV_REG_X31 = 32
// RISCV CSR
RISCV_REG_USTATUS = 33
RISCV_REG_UIE = 34
RISCV_REG_UTVEC = 35
RISCV_REG_USCRATCH = 36
RISCV_REG_UEPC = 37
RISCV_REG_UCAUSE = 38
RISCV_REG_UTVAL = 39
RISCV_REG_UIP = 40
RISCV_REG_FFLAGS = 41
RISCV_REG_FRM = 42
RISCV_REG_FCSR = 43
RISCV_REG_CYCLE = 44
RISCV_REG_TIME = 45
RISCV_REG_INSTRET = 46
RISCV_REG_HPMCOUNTER3 = 47
RISCV_REG_HPMCOUNTER4 = 48
RISCV_REG_HPMCOUNTER5 = 49
RISCV_REG_HPMCOUNTER6 = 50
RISCV_REG_HPMCOUNTER7 = 51
RISCV_REG_HPMCOUNTER8 = 52
RISCV_REG_HPMCOUNTER9 = 53
RISCV_REG_HPMCOUNTER10 = 54
RISCV_REG_HPMCOUNTER11 = 55
RISCV_REG_HPMCOUNTER12 = 56
RISCV_REG_HPMCOUNTER13 = 57
RISCV_REG_HPMCOUNTER14 = 58
RISCV_REG_HPMCOUNTER15 = 59
RISCV_REG_HPMCOUNTER16 = 60
RISCV_REG_HPMCOUNTER17 = 61
RISCV_REG_HPMCOUNTER18 = 62
RISCV_REG_HPMCOUNTER19 = 63
RISCV_REG_HPMCOUNTER20 = 64
RISCV_REG_HPMCOUNTER21 = 65
RISCV_REG_HPMCOUNTER22 = 66
RISCV_REG_HPMCOUNTER23 = 67
RISCV_REG_HPMCOUNTER24 = 68
RISCV_REG_HPMCOUNTER25 = 69
RISCV_REG_HPMCOUNTER26 = 70
RISCV_REG_HPMCOUNTER27 = 71
RISCV_REG_HPMCOUNTER28 = 72
RISCV_REG_HPMCOUNTER29 = 73
RISCV_REG_HPMCOUNTER30 = 74
RISCV_REG_HPMCOUNTER31 = 75
RISCV_REG_CYCLEH = 76
RISCV_REG_TIMEH = 77
RISCV_REG_INSTRETH = 78
RISCV_REG_HPMCOUNTER3H = 79
RISCV_REG_HPMCOUNTER4H = 80
RISCV_REG_HPMCOUNTER5H = 81
RISCV_REG_HPMCOUNTER6H = 82
RISCV_REG_HPMCOUNTER7H = 83
RISCV_REG_HPMCOUNTER8H = 84
RISCV_REG_HPMCOUNTER9H = 85
RISCV_REG_HPMCOUNTER10H = 86
RISCV_REG_HPMCOUNTER11H = 87
RISCV_REG_HPMCOUNTER12H = 88
RISCV_REG_HPMCOUNTER13H = 89
RISCV_REG_HPMCOUNTER14H = 90
RISCV_REG_HPMCOUNTER15H = 91
RISCV_REG_HPMCOUNTER16H = 92
RISCV_REG_HPMCOUNTER17H = 93
RISCV_REG_HPMCOUNTER18H = 94
RISCV_REG_HPMCOUNTER19H = 95
RISCV_REG_HPMCOUNTER20H = 96
RISCV_REG_HPMCOUNTER21H = 97
RISCV_REG_HPMCOUNTER22H = 98
RISCV_REG_HPMCOUNTER23H = 99
RISCV_REG_HPMCOUNTER24H = 100
RISCV_REG_HPMCOUNTER25H = 101
RISCV_REG_HPMCOUNTER26H = 102
RISCV_REG_HPMCOUNTER27H = 103
RISCV_REG_HPMCOUNTER28H = 104
RISCV_REG_HPMCOUNTER29H = 105
RISCV_REG_HPMCOUNTER30H = 106
RISCV_REG_HPMCOUNTER31H = 107
RISCV_REG_MCYCLE = 108
RISCV_REG_MINSTRET = 109
RISCV_REG_MCYCLEH = 110
RISCV_REG_MINSTRETH = 111
RISCV_REG_MVENDORID = 112
RISCV_REG_MARCHID = 113
RISCV_REG_MIMPID = 114
RISCV_REG_MHARTID = 115
RISCV_REG_MSTATUS = 116
RISCV_REG_MISA = 117
RISCV_REG_MEDELEG = 118
RISCV_REG_MIDELEG = 119
RISCV_REG_MIE = 120
RISCV_REG_MTVEC = 121
RISCV_REG_MCOUNTEREN = 122
RISCV_REG_MSTATUSH = 123
RISCV_REG_MUCOUNTEREN = 124
RISCV_REG_MSCOUNTEREN = 125
RISCV_REG_MHCOUNTEREN = 126
RISCV_REG_MSCRATCH = 127
RISCV_REG_MEPC = 128
RISCV_REG_MCAUSE = 129
RISCV_REG_MTVAL = 130
RISCV_REG_MIP = 131
RISCV_REG_MBADADDR = 132
RISCV_REG_SSTATUS = 133
RISCV_REG_SEDELEG = 134
RISCV_REG_SIDELEG = 135
RISCV_REG_SIE = 136
RISCV_REG_STVEC = 137
RISCV_REG_SCOUNTEREN = 138
RISCV_REG_SSCRATCH = 139
RISCV_REG_SEPC = 140
RISCV_REG_SCAUSE = 141
RISCV_REG_STVAL = 142
RISCV_REG_SIP = 143
RISCV_REG_SBADADDR = 144
RISCV_REG_SPTBR = 145
RISCV_REG_SATP = 146
RISCV_REG_HSTATUS = 147
RISCV_REG_HEDELEG = 148
RISCV_REG_HIDELEG = 149
RISCV_REG_HIE = 150
RISCV_REG_HCOUNTEREN = 151
RISCV_REG_HTVAL = 152
RISCV_REG_HIP = 153
RISCV_REG_HTINST = 154
RISCV_REG_HGATP = 155
RISCV_REG_HTIMEDELTA = 156
RISCV_REG_HTIMEDELTAH = 157
// Floating-point registers // Floating-point registers
RISCV_REG_F0 = 33 RISCV_REG_F0 = 158
RISCV_REG_F1 = 34 RISCV_REG_F1 = 159
RISCV_REG_F2 = 35 RISCV_REG_F2 = 160
RISCV_REG_F3 = 36 RISCV_REG_F3 = 161
RISCV_REG_F4 = 37 RISCV_REG_F4 = 162
RISCV_REG_F5 = 38 RISCV_REG_F5 = 163
RISCV_REG_F6 = 39 RISCV_REG_F6 = 164
RISCV_REG_F7 = 40 RISCV_REG_F7 = 165
RISCV_REG_F8 = 41 RISCV_REG_F8 = 166
RISCV_REG_F9 = 42 RISCV_REG_F9 = 167
RISCV_REG_F10 = 43 RISCV_REG_F10 = 168
RISCV_REG_F11 = 44 RISCV_REG_F11 = 169
RISCV_REG_F12 = 45 RISCV_REG_F12 = 170
RISCV_REG_F13 = 46 RISCV_REG_F13 = 171
RISCV_REG_F14 = 47 RISCV_REG_F14 = 172
RISCV_REG_F15 = 48 RISCV_REG_F15 = 173
RISCV_REG_F16 = 49 RISCV_REG_F16 = 174
RISCV_REG_F17 = 50 RISCV_REG_F17 = 175
RISCV_REG_F18 = 51 RISCV_REG_F18 = 176
RISCV_REG_F19 = 52 RISCV_REG_F19 = 177
RISCV_REG_F20 = 53 RISCV_REG_F20 = 178
RISCV_REG_F21 = 54 RISCV_REG_F21 = 179
RISCV_REG_F22 = 55 RISCV_REG_F22 = 180
RISCV_REG_F23 = 56 RISCV_REG_F23 = 181
RISCV_REG_F24 = 57 RISCV_REG_F24 = 182
RISCV_REG_F25 = 58 RISCV_REG_F25 = 183
RISCV_REG_F26 = 59 RISCV_REG_F26 = 184
RISCV_REG_F27 = 60 RISCV_REG_F27 = 185
RISCV_REG_F28 = 61 RISCV_REG_F28 = 186
RISCV_REG_F29 = 62 RISCV_REG_F29 = 187
RISCV_REG_F30 = 63 RISCV_REG_F30 = 188
RISCV_REG_F31 = 64 RISCV_REG_F31 = 189
RISCV_REG_PC = 65 RISCV_REG_PC = 190
RISCV_REG_ENDING = 66 RISCV_REG_ENDING = 191
// Alias registers // Alias registers
RISCV_REG_ZERO = 1 RISCV_REG_ZERO = 1
@ -124,36 +251,36 @@ const (
RISCV_REG_T4 = 30 RISCV_REG_T4 = 30
RISCV_REG_T5 = 31 RISCV_REG_T5 = 31
RISCV_REG_T6 = 32 RISCV_REG_T6 = 32
RISCV_REG_FT0 = 33 RISCV_REG_FT0 = 158
RISCV_REG_FT1 = 34 RISCV_REG_FT1 = 159
RISCV_REG_FT2 = 35 RISCV_REG_FT2 = 160
RISCV_REG_FT3 = 36 RISCV_REG_FT3 = 161
RISCV_REG_FT4 = 37 RISCV_REG_FT4 = 162
RISCV_REG_FT5 = 38 RISCV_REG_FT5 = 163
RISCV_REG_FT6 = 39 RISCV_REG_FT6 = 164
RISCV_REG_FT7 = 40 RISCV_REG_FT7 = 165
RISCV_REG_FS0 = 41 RISCV_REG_FS0 = 166
RISCV_REG_FS1 = 42 RISCV_REG_FS1 = 167
RISCV_REG_FA0 = 43 RISCV_REG_FA0 = 168
RISCV_REG_FA1 = 44 RISCV_REG_FA1 = 169
RISCV_REG_FA2 = 45 RISCV_REG_FA2 = 170
RISCV_REG_FA3 = 46 RISCV_REG_FA3 = 171
RISCV_REG_FA4 = 47 RISCV_REG_FA4 = 172
RISCV_REG_FA5 = 48 RISCV_REG_FA5 = 173
RISCV_REG_FA6 = 49 RISCV_REG_FA6 = 174
RISCV_REG_FA7 = 50 RISCV_REG_FA7 = 175
RISCV_REG_FS2 = 51 RISCV_REG_FS2 = 176
RISCV_REG_FS3 = 52 RISCV_REG_FS3 = 177
RISCV_REG_FS4 = 53 RISCV_REG_FS4 = 178
RISCV_REG_FS5 = 54 RISCV_REG_FS5 = 179
RISCV_REG_FS6 = 55 RISCV_REG_FS6 = 180
RISCV_REG_FS7 = 56 RISCV_REG_FS7 = 181
RISCV_REG_FS8 = 57 RISCV_REG_FS8 = 182
RISCV_REG_FS9 = 58 RISCV_REG_FS9 = 183
RISCV_REG_FS10 = 59 RISCV_REG_FS10 = 184
RISCV_REG_FS11 = 60 RISCV_REG_FS11 = 185
RISCV_REG_FT8 = 61 RISCV_REG_FT8 = 186
RISCV_REG_FT9 = 62 RISCV_REG_FT9 = 187
RISCV_REG_FT10 = 63 RISCV_REG_FT10 = 188
RISCV_REG_FT11 = 64 RISCV_REG_FT11 = 189
) )

123
bindings/go/unicorn/s390x_const.go Normal file
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@ -0,0 +1,123 @@
package unicorn
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [s390x_const.go]
const (
// S390X CPU
CPU_S390X_Z900 = 0
CPU_S390X_Z900_2 = 1
CPU_S390X_Z900_3 = 2
CPU_S390X_Z800 = 3
CPU_S390X_Z990 = 4
CPU_S390X_Z990_2 = 5
CPU_S390X_Z990_3 = 6
CPU_S390X_Z890 = 7
CPU_S390X_Z990_4 = 8
CPU_S390X_Z890_2 = 9
CPU_S390X_Z990_5 = 10
CPU_S390X_Z890_3 = 11
CPU_S390X_Z9EC = 12
CPU_S390X_Z9EC_2 = 13
CPU_S390X_Z9BC = 14
CPU_S390X_Z9EC_3 = 15
CPU_S390X_Z9BC_2 = 16
CPU_S390X_Z10EC = 17
CPU_S390X_Z10EC_2 = 18
CPU_S390X_Z10BC = 19
CPU_S390X_Z10EC_3 = 20
CPU_S390X_Z10BC_2 = 21
CPU_S390X_Z196 = 22
CPU_S390X_Z196_2 = 23
CPU_S390X_Z114 = 24
CPU_S390X_ZEC12 = 25
CPU_S390X_ZEC12_2 = 26
CPU_S390X_ZBC12 = 27
CPU_S390X_Z13 = 28
CPU_S390X_Z13_2 = 29
CPU_S390X_Z13S = 30
CPU_S390X_Z14 = 31
CPU_S390X_Z14_2 = 32
CPU_S390X_Z14ZR1 = 33
CPU_S390X_GEN15A = 34
CPU_S390X_GEN15B = 35
CPU_S390X_QEMU = 36
CPU_S390X_MAX = 37
// S390X registers
S390X_REG_INVALID = 0
// General purpose registers
S390X_REG_R0 = 1
S390X_REG_R1 = 2
S390X_REG_R2 = 3
S390X_REG_R3 = 4
S390X_REG_R4 = 5
S390X_REG_R5 = 6
S390X_REG_R6 = 7
S390X_REG_R7 = 8
S390X_REG_R8 = 9
S390X_REG_R9 = 10
S390X_REG_R10 = 11
S390X_REG_R11 = 12
S390X_REG_R12 = 13
S390X_REG_R13 = 14
S390X_REG_R14 = 15
S390X_REG_R15 = 16
// Floating point registers
S390X_REG_F0 = 17
S390X_REG_F1 = 18
S390X_REG_F2 = 19
S390X_REG_F3 = 20
S390X_REG_F4 = 21
S390X_REG_F5 = 22
S390X_REG_F6 = 23
S390X_REG_F7 = 24
S390X_REG_F8 = 25
S390X_REG_F9 = 26
S390X_REG_F10 = 27
S390X_REG_F11 = 28
S390X_REG_F12 = 29
S390X_REG_F13 = 30
S390X_REG_F14 = 31
S390X_REG_F15 = 32
S390X_REG_F16 = 33
S390X_REG_F17 = 34
S390X_REG_F18 = 35
S390X_REG_F19 = 36
S390X_REG_F20 = 37
S390X_REG_F21 = 38
S390X_REG_F22 = 39
S390X_REG_F23 = 40
S390X_REG_F24 = 41
S390X_REG_F25 = 42
S390X_REG_F26 = 43
S390X_REG_F27 = 44
S390X_REG_F28 = 45
S390X_REG_F29 = 46
S390X_REG_F30 = 47
S390X_REG_F31 = 48
// Access registers
S390X_REG_A0 = 49
S390X_REG_A1 = 50
S390X_REG_A2 = 51
S390X_REG_A3 = 52
S390X_REG_A4 = 53
S390X_REG_A5 = 54
S390X_REG_A6 = 55
S390X_REG_A7 = 56
S390X_REG_A8 = 57
S390X_REG_A9 = 58
S390X_REG_A10 = 59
S390X_REG_A11 = 60
S390X_REG_A12 = 61
S390X_REG_A13 = 62
S390X_REG_A14 = 63
S390X_REG_A15 = 64
S390X_REG_PC = 65
S390X_REG_ENDING = 66
// Alias registers
)

9
bindings/go/unicorn/unicorn_const.go
View File

@ -4,11 +4,15 @@ const (
API_MAJOR = 2 API_MAJOR = 2
API_MINOR = 0 API_MINOR = 0
API_PATCH = 0
API_EXTRA = 5
VERSION_MAJOR = 2 VERSION_MAJOR = 2
VERSION_MINOR = 0 VERSION_MINOR = 0
VERSION_EXTRA = 0 VERSION_PATCH = 0
VERSION_EXTRA = 5
SECOND_SCALE = 1000000 SECOND_SCALE = 1000000
MILISECOND_SCALE = 1000 MILISECOND_SCALE = 1000
ARCH_ARM = 1 ARCH_ARM = 1
@ -19,7 +23,8 @@ const (
ARCH_SPARC = 6 ARCH_SPARC = 6
ARCH_M68K = 7 ARCH_M68K = 7
ARCH_RISCV = 8 ARCH_RISCV = 8
ARCH_MAX = 9 ARCH_S390X = 9
ARCH_MAX = 10
MODE_LITTLE_ENDIAN = 0 MODE_LITTLE_ENDIAN = 0
MODE_BIG_ENDIAN = 1073741824 MODE_BIG_ENDIAN = 1073741824

18
bindings/java/unicorn/M68kConst.java
View File

@ -6,15 +6,15 @@ public interface M68kConst {
// M68K CPU // M68K CPU
public static final int UC_CPU_M5206_CPU = 0; public static final int UC_CPU_M68K_M5206 = 0;
public static final int UC_CPU_M68000_CPU = 1; public static final int UC_CPU_M68K_M68000 = 1;
public static final int UC_CPU_M68020_CPU = 2; public static final int UC_CPU_M68K_M68020 = 2;
public static final int UC_CPU_M68030_CPU = 3; public static final int UC_CPU_M68K_M68030 = 3;
public static final int UC_CPU_M68040_CPU = 4; public static final int UC_CPU_M68K_M68040 = 4;
public static final int UC_CPU_M68060_CPU = 5; public static final int UC_CPU_M68K_M68060 = 5;
public static final int UC_CPU_M5208_CPU = 6; public static final int UC_CPU_M68K_M5208 = 6;
public static final int UC_CPU_CFV4E_CPU = 7; public static final int UC_CPU_M68K_CFV4E = 7;
public static final int UC_CPU_ANY_CPU = 8; public static final int UC_CPU_M68K_ANY = 8;
// M68K registers // M68K registers

259
bindings/java/unicorn/RiscvConst.java
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@ -56,41 +56,168 @@ public interface RiscvConst {
public static final int UC_RISCV_REG_X30 = 31; public static final int UC_RISCV_REG_X30 = 31;
public static final int UC_RISCV_REG_X31 = 32; public static final int UC_RISCV_REG_X31 = 32;
// RISCV CSR
public static final int UC_RISCV_REG_USTATUS = 33;
public static final int UC_RISCV_REG_UIE = 34;
public static final int UC_RISCV_REG_UTVEC = 35;
public static final int UC_RISCV_REG_USCRATCH = 36;
public static final int UC_RISCV_REG_UEPC = 37;
public static final int UC_RISCV_REG_UCAUSE = 38;
public static final int UC_RISCV_REG_UTVAL = 39;
public static final int UC_RISCV_REG_UIP = 40;
public static final int UC_RISCV_REG_FFLAGS = 41;
public static final int UC_RISCV_REG_FRM = 42;
public static final int UC_RISCV_REG_FCSR = 43;
public static final int UC_RISCV_REG_CYCLE = 44;
public static final int UC_RISCV_REG_TIME = 45;
public static final int UC_RISCV_REG_INSTRET = 46;
public static final int UC_RISCV_REG_HPMCOUNTER3 = 47;
public static final int UC_RISCV_REG_HPMCOUNTER4 = 48;
public static final int UC_RISCV_REG_HPMCOUNTER5 = 49;
public static final int UC_RISCV_REG_HPMCOUNTER6 = 50;
public static final int UC_RISCV_REG_HPMCOUNTER7 = 51;
public static final int UC_RISCV_REG_HPMCOUNTER8 = 52;
public static final int UC_RISCV_REG_HPMCOUNTER9 = 53;
public static final int UC_RISCV_REG_HPMCOUNTER10 = 54;
public static final int UC_RISCV_REG_HPMCOUNTER11 = 55;
public static final int UC_RISCV_REG_HPMCOUNTER12 = 56;
public static final int UC_RISCV_REG_HPMCOUNTER13 = 57;
public static final int UC_RISCV_REG_HPMCOUNTER14 = 58;
public static final int UC_RISCV_REG_HPMCOUNTER15 = 59;
public static final int UC_RISCV_REG_HPMCOUNTER16 = 60;
public static final int UC_RISCV_REG_HPMCOUNTER17 = 61;
public static final int UC_RISCV_REG_HPMCOUNTER18 = 62;
public static final int UC_RISCV_REG_HPMCOUNTER19 = 63;
public static final int UC_RISCV_REG_HPMCOUNTER20 = 64;
public static final int UC_RISCV_REG_HPMCOUNTER21 = 65;
public static final int UC_RISCV_REG_HPMCOUNTER22 = 66;
public static final int UC_RISCV_REG_HPMCOUNTER23 = 67;
public static final int UC_RISCV_REG_HPMCOUNTER24 = 68;
public static final int UC_RISCV_REG_HPMCOUNTER25 = 69;
public static final int UC_RISCV_REG_HPMCOUNTER26 = 70;
public static final int UC_RISCV_REG_HPMCOUNTER27 = 71;
public static final int UC_RISCV_REG_HPMCOUNTER28 = 72;
public static final int UC_RISCV_REG_HPMCOUNTER29 = 73;
public static final int UC_RISCV_REG_HPMCOUNTER30 = 74;
public static final int UC_RISCV_REG_HPMCOUNTER31 = 75;
public static final int UC_RISCV_REG_CYCLEH = 76;
public static final int UC_RISCV_REG_TIMEH = 77;
public static final int UC_RISCV_REG_INSTRETH = 78;
public static final int UC_RISCV_REG_HPMCOUNTER3H = 79;
public static final int UC_RISCV_REG_HPMCOUNTER4H = 80;
public static final int UC_RISCV_REG_HPMCOUNTER5H = 81;
public static final int UC_RISCV_REG_HPMCOUNTER6H = 82;
public static final int UC_RISCV_REG_HPMCOUNTER7H = 83;
public static final int UC_RISCV_REG_HPMCOUNTER8H = 84;
public static final int UC_RISCV_REG_HPMCOUNTER9H = 85;
public static final int UC_RISCV_REG_HPMCOUNTER10H = 86;
public static final int UC_RISCV_REG_HPMCOUNTER11H = 87;
public static final int UC_RISCV_REG_HPMCOUNTER12H = 88;
public static final int UC_RISCV_REG_HPMCOUNTER13H = 89;
public static final int UC_RISCV_REG_HPMCOUNTER14H = 90;
public static final int UC_RISCV_REG_HPMCOUNTER15H = 91;
public static final int UC_RISCV_REG_HPMCOUNTER16H = 92;
public static final int UC_RISCV_REG_HPMCOUNTER17H = 93;
public static final int UC_RISCV_REG_HPMCOUNTER18H = 94;
public static final int UC_RISCV_REG_HPMCOUNTER19H = 95;
public static final int UC_RISCV_REG_HPMCOUNTER20H = 96;
public static final int UC_RISCV_REG_HPMCOUNTER21H = 97;
public static final int UC_RISCV_REG_HPMCOUNTER22H = 98;
public static final int UC_RISCV_REG_HPMCOUNTER23H = 99;
public static final int UC_RISCV_REG_HPMCOUNTER24H = 100;
public static final int UC_RISCV_REG_HPMCOUNTER25H = 101;
public static final int UC_RISCV_REG_HPMCOUNTER26H = 102;
public static final int UC_RISCV_REG_HPMCOUNTER27H = 103;
public static final int UC_RISCV_REG_HPMCOUNTER28H = 104;
public static final int UC_RISCV_REG_HPMCOUNTER29H = 105;
public static final int UC_RISCV_REG_HPMCOUNTER30H = 106;
public static final int UC_RISCV_REG_HPMCOUNTER31H = 107;
public static final int UC_RISCV_REG_MCYCLE = 108;
public static final int UC_RISCV_REG_MINSTRET = 109;
public static final int UC_RISCV_REG_MCYCLEH = 110;
public static final int UC_RISCV_REG_MINSTRETH = 111;
public static final int UC_RISCV_REG_MVENDORID = 112;
public static final int UC_RISCV_REG_MARCHID = 113;
public static final int UC_RISCV_REG_MIMPID = 114;
public static final int UC_RISCV_REG_MHARTID = 115;
public static final int UC_RISCV_REG_MSTATUS = 116;
public static final int UC_RISCV_REG_MISA = 117;
public static final int UC_RISCV_REG_MEDELEG = 118;
public static final int UC_RISCV_REG_MIDELEG = 119;
public static final int UC_RISCV_REG_MIE = 120;
public static final int UC_RISCV_REG_MTVEC = 121;
public static final int UC_RISCV_REG_MCOUNTEREN = 122;
public static final int UC_RISCV_REG_MSTATUSH = 123;
public static final int UC_RISCV_REG_MUCOUNTEREN = 124;
public static final int UC_RISCV_REG_MSCOUNTEREN = 125;
public static final int UC_RISCV_REG_MHCOUNTEREN = 126;
public static final int UC_RISCV_REG_MSCRATCH = 127;
public static final int UC_RISCV_REG_MEPC = 128;
public static final int UC_RISCV_REG_MCAUSE = 129;
public static final int UC_RISCV_REG_MTVAL = 130;
public static final int UC_RISCV_REG_MIP = 131;
public static final int UC_RISCV_REG_MBADADDR = 132;
public static final int UC_RISCV_REG_SSTATUS = 133;
public static final int UC_RISCV_REG_SEDELEG = 134;
public static final int UC_RISCV_REG_SIDELEG = 135;
public static final int UC_RISCV_REG_SIE = 136;
public static final int UC_RISCV_REG_STVEC = 137;
public static final int UC_RISCV_REG_SCOUNTEREN = 138;
public static final int UC_RISCV_REG_SSCRATCH = 139;
public static final int UC_RISCV_REG_SEPC = 140;
public static final int UC_RISCV_REG_SCAUSE = 141;
public static final int UC_RISCV_REG_STVAL = 142;
public static final int UC_RISCV_REG_SIP = 143;
public static final int UC_RISCV_REG_SBADADDR = 144;
public static final int UC_RISCV_REG_SPTBR = 145;
public static final int UC_RISCV_REG_SATP = 146;
public static final int UC_RISCV_REG_HSTATUS = 147;
public static final int UC_RISCV_REG_HEDELEG = 148;
public static final int UC_RISCV_REG_HIDELEG = 149;
public static final int UC_RISCV_REG_HIE = 150;
public static final int UC_RISCV_REG_HCOUNTEREN = 151;
public static final int UC_RISCV_REG_HTVAL = 152;
public static final int UC_RISCV_REG_HIP = 153;
public static final int UC_RISCV_REG_HTINST = 154;
public static final int UC_RISCV_REG_HGATP = 155;
public static final int UC_RISCV_REG_HTIMEDELTA = 156;
public static final int UC_RISCV_REG_HTIMEDELTAH = 157;
// Floating-point registers // Floating-point registers
public static final int UC_RISCV_REG_F0 = 33; public static final int UC_RISCV_REG_F0 = 158;
public static final int UC_RISCV_REG_F1 = 34; public static final int UC_RISCV_REG_F1 = 159;
public static final int UC_RISCV_REG_F2 = 35; public static final int UC_RISCV_REG_F2 = 160;
public static final int UC_RISCV_REG_F3 = 36; public static final int UC_RISCV_REG_F3 = 161;
public static final int UC_RISCV_REG_F4 = 37; public static final int UC_RISCV_REG_F4 = 162;
public static final int UC_RISCV_REG_F5 = 38; public static final int UC_RISCV_REG_F5 = 163;
public static final int UC_RISCV_REG_F6 = 39; public static final int UC_RISCV_REG_F6 = 164;
public static final int UC_RISCV_REG_F7 = 40; public static final int UC_RISCV_REG_F7 = 165;
public static final int UC_RISCV_REG_F8 = 41; public static final int UC_RISCV_REG_F8 = 166;
public static final int UC_RISCV_REG_F9 = 42; public static final int UC_RISCV_REG_F9 = 167;
public static final int UC_RISCV_REG_F10 = 43; public static final int UC_RISCV_REG_F10 = 168;
public static final int UC_RISCV_REG_F11 = 44; public static final int UC_RISCV_REG_F11 = 169;
public static final int UC_RISCV_REG_F12 = 45; public static final int UC_RISCV_REG_F12 = 170;
public static final int UC_RISCV_REG_F13 = 46; public static final int UC_RISCV_REG_F13 = 171;
public static final int UC_RISCV_REG_F14 = 47; public static final int UC_RISCV_REG_F14 = 172;
public static final int UC_RISCV_REG_F15 = 48; public static final int UC_RISCV_REG_F15 = 173;
public static final int UC_RISCV_REG_F16 = 49; public static final int UC_RISCV_REG_F16 = 174;
public static final int UC_RISCV_REG_F17 = 50; public static final int UC_RISCV_REG_F17 = 175;
public static final int UC_RISCV_REG_F18 = 51; public static final int UC_RISCV_REG_F18 = 176;
public static final int UC_RISCV_REG_F19 = 52; public static final int UC_RISCV_REG_F19 = 177;
public static final int UC_RISCV_REG_F20 = 53; public static final int UC_RISCV_REG_F20 = 178;
public static final int UC_RISCV_REG_F21 = 54; public static final int UC_RISCV_REG_F21 = 179;
public static final int UC_RISCV_REG_F22 = 55; public static final int UC_RISCV_REG_F22 = 180;
public static final int UC_RISCV_REG_F23 = 56; public static final int UC_RISCV_REG_F23 = 181;
public static final int UC_RISCV_REG_F24 = 57; public static final int UC_RISCV_REG_F24 = 182;
public static final int UC_RISCV_REG_F25 = 58; public static final int UC_RISCV_REG_F25 = 183;
public static final int UC_RISCV_REG_F26 = 59; public static final int UC_RISCV_REG_F26 = 184;
public static final int UC_RISCV_REG_F27 = 60; public static final int UC_RISCV_REG_F27 = 185;
public static final int UC_RISCV_REG_F28 = 61; public static final int UC_RISCV_REG_F28 = 186;
public static final int UC_RISCV_REG_F29 = 62; public static final int UC_RISCV_REG_F29 = 187;
public static final int UC_RISCV_REG_F30 = 63; public static final int UC_RISCV_REG_F30 = 188;
public static final int UC_RISCV_REG_F31 = 64; public static final int UC_RISCV_REG_F31 = 189;
public static final int UC_RISCV_REG_PC = 65; public static final int UC_RISCV_REG_PC = 190;
public static final int UC_RISCV_REG_ENDING = 66; public static final int UC_RISCV_REG_ENDING = 191;
// Alias registers // Alias registers
public static final int UC_RISCV_REG_ZERO = 1; public static final int UC_RISCV_REG_ZERO = 1;
@ -126,37 +253,37 @@ public interface RiscvConst {
public static final int UC_RISCV_REG_T4 = 30; public static final int UC_RISCV_REG_T4 = 30;
public static final int UC_RISCV_REG_T5 = 31; public static final int UC_RISCV_REG_T5 = 31;
public static final int UC_RISCV_REG_T6 = 32; public static final int UC_RISCV_REG_T6 = 32;
public static final int UC_RISCV_REG_FT0 = 33; public static final int UC_RISCV_REG_FT0 = 158;
public static final int UC_RISCV_REG_FT1 = 34; public static final int UC_RISCV_REG_FT1 = 159;
public static final int UC_RISCV_REG_FT2 = 35; public static final int UC_RISCV_REG_FT2 = 160;
public static final int UC_RISCV_REG_FT3 = 36; public static final int UC_RISCV_REG_FT3 = 161;
public static final int UC_RISCV_REG_FT4 = 37; public static final int UC_RISCV_REG_FT4 = 162;
public static final int UC_RISCV_REG_FT5 = 38; public static final int UC_RISCV_REG_FT5 = 163;
public static final int UC_RISCV_REG_FT6 = 39; public static final int UC_RISCV_REG_FT6 = 164;
public static final int UC_RISCV_REG_FT7 = 40; public static final int UC_RISCV_REG_FT7 = 165;
public static final int UC_RISCV_REG_FS0 = 41; public static final int UC_RISCV_REG_FS0 = 166;
public static final int UC_RISCV_REG_FS1 = 42; public static final int UC_RISCV_REG_FS1 = 167;
public static final int UC_RISCV_REG_FA0 = 43; public static final int UC_RISCV_REG_FA0 = 168;
public static final int UC_RISCV_REG_FA1 = 44; public static final int UC_RISCV_REG_FA1 = 169;
public static final int UC_RISCV_REG_FA2 = 45; public static final int UC_RISCV_REG_FA2 = 170;
public static final int UC_RISCV_REG_FA3 = 46; public static final int UC_RISCV_REG_FA3 = 171;
public static final int UC_RISCV_REG_FA4 = 47; public static final int UC_RISCV_REG_FA4 = 172;
public static final int UC_RISCV_REG_FA5 = 48; public static final int UC_RISCV_REG_FA5 = 173;
public static final int UC_RISCV_REG_FA6 = 49; public static final int UC_RISCV_REG_FA6 = 174;
public static final int UC_RISCV_REG_FA7 = 50; public static final int UC_RISCV_REG_FA7 = 175;
public static final int UC_RISCV_REG_FS2 = 51; public static final int UC_RISCV_REG_FS2 = 176;
public static final int UC_RISCV_REG_FS3 = 52; public static final int UC_RISCV_REG_FS3 = 177;
public static final int UC_RISCV_REG_FS4 = 53; public static final int UC_RISCV_REG_FS4 = 178;
public static final int UC_RISCV_REG_FS5 = 54; public static final int UC_RISCV_REG_FS5 = 179;
public static final int UC_RISCV_REG_FS6 = 55; public static final int UC_RISCV_REG_FS6 = 180;
public static final int UC_RISCV_REG_FS7 = 56; public static final int UC_RISCV_REG_FS7 = 181;
public static final int UC_RISCV_REG_FS8 = 57; public static final int UC_RISCV_REG_FS8 = 182;
public static final int UC_RISCV_REG_FS9 = 58; public static final int UC_RISCV_REG_FS9 = 183;
public static final int UC_RISCV_REG_FS10 = 59; public static final int UC_RISCV_REG_FS10 = 184;
public static final int UC_RISCV_REG_FS11 = 60; public static final int UC_RISCV_REG_FS11 = 185;
public static final int UC_RISCV_REG_FT8 = 61; public static final int UC_RISCV_REG_FT8 = 186;
public static final int UC_RISCV_REG_FT9 = 62; public static final int UC_RISCV_REG_FT9 = 187;
public static final int UC_RISCV_REG_FT10 = 63; public static final int UC_RISCV_REG_FT10 = 188;
public static final int UC_RISCV_REG_FT11 = 64; public static final int UC_RISCV_REG_FT11 = 189;
} }

126
bindings/java/unicorn/S390xConst.java Normal file
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@ -0,0 +1,126 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
package unicorn;
public interface S390xConst {
// S390X CPU
public static final int UC_CPU_S390X_Z900 = 0;
public static final int UC_CPU_S390X_Z900_2 = 1;
public static final int UC_CPU_S390X_Z900_3 = 2;
public static final int UC_CPU_S390X_Z800 = 3;
public static final int UC_CPU_S390X_Z990 = 4;
public static final int UC_CPU_S390X_Z990_2 = 5;
public static final int UC_CPU_S390X_Z990_3 = 6;
public static final int UC_CPU_S390X_Z890 = 7;
public static final int UC_CPU_S390X_Z990_4 = 8;
public static final int UC_CPU_S390X_Z890_2 = 9;
public static final int UC_CPU_S390X_Z990_5 = 10;
public static final int UC_CPU_S390X_Z890_3 = 11;
public static final int UC_CPU_S390X_Z9EC = 12;
public static final int UC_CPU_S390X_Z9EC_2 = 13;
public static final int UC_CPU_S390X_Z9BC = 14;
public static final int UC_CPU_S390X_Z9EC_3 = 15;
public static final int UC_CPU_S390X_Z9BC_2 = 16;
public static final int UC_CPU_S390X_Z10EC = 17;
public static final int UC_CPU_S390X_Z10EC_2 = 18;
public static final int UC_CPU_S390X_Z10BC = 19;
public static final int UC_CPU_S390X_Z10EC_3 = 20;
public static final int UC_CPU_S390X_Z10BC_2 = 21;
public static final int UC_CPU_S390X_Z196 = 22;
public static final int UC_CPU_S390X_Z196_2 = 23;
public static final int UC_CPU_S390X_Z114 = 24;
public static final int UC_CPU_S390X_ZEC12 = 25;
public static final int UC_CPU_S390X_ZEC12_2 = 26;
public static final int UC_CPU_S390X_ZBC12 = 27;
public static final int UC_CPU_S390X_Z13 = 28;
public static final int UC_CPU_S390X_Z13_2 = 29;
public static final int UC_CPU_S390X_Z13S = 30;
public static final int UC_CPU_S390X_Z14 = 31;
public static final int UC_CPU_S390X_Z14_2 = 32;
public static final int UC_CPU_S390X_Z14ZR1 = 33;
public static final int UC_CPU_S390X_GEN15A = 34;
public static final int UC_CPU_S390X_GEN15B = 35;
public static final int UC_CPU_S390X_QEMU = 36;
public static final int UC_CPU_S390X_MAX = 37;
// S390X registers
public static final int UC_S390X_REG_INVALID = 0;
// General purpose registers
public static final int UC_S390X_REG_R0 = 1;
public static final int UC_S390X_REG_R1 = 2;
public static final int UC_S390X_REG_R2 = 3;
public static final int UC_S390X_REG_R3 = 4;
public static final int UC_S390X_REG_R4 = 5;
public static final int UC_S390X_REG_R5 = 6;
public static final int UC_S390X_REG_R6 = 7;
public static final int UC_S390X_REG_R7 = 8;
public static final int UC_S390X_REG_R8 = 9;
public static final int UC_S390X_REG_R9 = 10;
public static final int UC_S390X_REG_R10 = 11;
public static final int UC_S390X_REG_R11 = 12;
public static final int UC_S390X_REG_R12 = 13;
public static final int UC_S390X_REG_R13 = 14;
public static final int UC_S390X_REG_R14 = 15;
public static final int UC_S390X_REG_R15 = 16;
// Floating point registers
public static final int UC_S390X_REG_F0 = 17;
public static final int UC_S390X_REG_F1 = 18;
public static final int UC_S390X_REG_F2 = 19;
public static final int UC_S390X_REG_F3 = 20;
public static final int UC_S390X_REG_F4 = 21;
public static final int UC_S390X_REG_F5 = 22;
public static final int UC_S390X_REG_F6 = 23;
public static final int UC_S390X_REG_F7 = 24;
public static final int UC_S390X_REG_F8 = 25;
public static final int UC_S390X_REG_F9 = 26;
public static final int UC_S390X_REG_F10 = 27;
public static final int UC_S390X_REG_F11 = 28;
public static final int UC_S390X_REG_F12 = 29;
public static final int UC_S390X_REG_F13 = 30;
public static final int UC_S390X_REG_F14 = 31;
public static final int UC_S390X_REG_F15 = 32;
public static final int UC_S390X_REG_F16 = 33;
public static final int UC_S390X_REG_F17 = 34;
public static final int UC_S390X_REG_F18 = 35;
public static final int UC_S390X_REG_F19 = 36;
public static final int UC_S390X_REG_F20 = 37;
public static final int UC_S390X_REG_F21 = 38;
public static final int UC_S390X_REG_F22 = 39;
public static final int UC_S390X_REG_F23 = 40;
public static final int UC_S390X_REG_F24 = 41;
public static final int UC_S390X_REG_F25 = 42;
public static final int UC_S390X_REG_F26 = 43;
public static final int UC_S390X_REG_F27 = 44;
public static final int UC_S390X_REG_F28 = 45;
public static final int UC_S390X_REG_F29 = 46;
public static final int UC_S390X_REG_F30 = 47;
public static final int UC_S390X_REG_F31 = 48;
// Access registers
public static final int UC_S390X_REG_A0 = 49;
public static final int UC_S390X_REG_A1 = 50;
public static final int UC_S390X_REG_A2 = 51;
public static final int UC_S390X_REG_A3 = 52;
public static final int UC_S390X_REG_A4 = 53;
public static final int UC_S390X_REG_A5 = 54;
public static final int UC_S390X_REG_A6 = 55;
public static final int UC_S390X_REG_A7 = 56;
public static final int UC_S390X_REG_A8 = 57;
public static final int UC_S390X_REG_A9 = 58;
public static final int UC_S390X_REG_A10 = 59;
public static final int UC_S390X_REG_A11 = 60;
public static final int UC_S390X_REG_A12 = 61;
public static final int UC_S390X_REG_A13 = 62;
public static final int UC_S390X_REG_A14 = 63;
public static final int UC_S390X_REG_A15 = 64;
public static final int UC_S390X_REG_PC = 65;
public static final int UC_S390X_REG_ENDING = 66;
// Alias registers
}

9
bindings/java/unicorn/UnicornConst.java
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@ -6,11 +6,15 @@ public interface UnicornConst {
public static final int UC_API_MAJOR = 2; public static final int UC_API_MAJOR = 2;
public static final int UC_API_MINOR = 0; public static final int UC_API_MINOR = 0;
public static final int UC_API_PATCH = 0;
public static final int UC_API_EXTRA = 5;
public static final int UC_VERSION_MAJOR = 2; public static final int UC_VERSION_MAJOR = 2;
public static final int UC_VERSION_MINOR = 0; public static final int UC_VERSION_MINOR = 0;
public static final int UC_VERSION_EXTRA = 0; public static final int UC_VERSION_PATCH = 0;
public static final int UC_VERSION_EXTRA = 5;
public static final int UC_SECOND_SCALE = 1000000; public static final int UC_SECOND_SCALE = 1000000;
public static final int UC_MILISECOND_SCALE = 1000; public static final int UC_MILISECOND_SCALE = 1000;
public static final int UC_ARCH_ARM = 1; public static final int UC_ARCH_ARM = 1;
@ -21,7 +25,8 @@ public interface UnicornConst {
public static final int UC_ARCH_SPARC = 6; public static final int UC_ARCH_SPARC = 6;
public static final int UC_ARCH_M68K = 7; public static final int UC_ARCH_M68K = 7;
public static final int UC_ARCH_RISCV = 8; public static final int UC_ARCH_RISCV = 8;
public static final int UC_ARCH_MAX = 9; public static final int UC_ARCH_S390X = 9;
public static final int UC_ARCH_MAX = 10;
public static final int UC_MODE_LITTLE_ENDIAN = 0; public static final int UC_MODE_LITTLE_ENDIAN = 0;
public static final int UC_MODE_BIG_ENDIAN = 1073741824; public static final int UC_MODE_BIG_ENDIAN = 1073741824;

18
bindings/pascal/unicorn/M68kConst.pas
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@ -7,15 +7,15 @@ interface
const const
// M68K CPU // M68K CPU
UC_CPU_M5206_CPU = 0; UC_CPU_M68K_M5206 = 0;
UC_CPU_M68000_CPU = 1; UC_CPU_M68K_M68000 = 1;
UC_CPU_M68020_CPU = 2; UC_CPU_M68K_M68020 = 2;
UC_CPU_M68030_CPU = 3; UC_CPU_M68K_M68030 = 3;
UC_CPU_M68040_CPU = 4; UC_CPU_M68K_M68040 = 4;
UC_CPU_M68060_CPU = 5; UC_CPU_M68K_M68060 = 5;
UC_CPU_M5208_CPU = 6; UC_CPU_M68K_M5208 = 6;
UC_CPU_CFV4E_CPU = 7; UC_CPU_M68K_CFV4E = 7;
UC_CPU_ANY_CPU = 8; UC_CPU_M68K_ANY = 8;
// M68K registers // M68K registers

259
bindings/pascal/unicorn/RiscvConst.pas
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@ -57,41 +57,168 @@ const
UC_RISCV_REG_X30 = 31; UC_RISCV_REG_X30 = 31;
UC_RISCV_REG_X31 = 32; UC_RISCV_REG_X31 = 32;
// RISCV CSR
UC_RISCV_REG_USTATUS = 33;
UC_RISCV_REG_UIE = 34;
UC_RISCV_REG_UTVEC = 35;
UC_RISCV_REG_USCRATCH = 36;
UC_RISCV_REG_UEPC = 37;
UC_RISCV_REG_UCAUSE = 38;
UC_RISCV_REG_UTVAL = 39;
UC_RISCV_REG_UIP = 40;
UC_RISCV_REG_FFLAGS = 41;
UC_RISCV_REG_FRM = 42;
UC_RISCV_REG_FCSR = 43;
UC_RISCV_REG_CYCLE = 44;
UC_RISCV_REG_TIME = 45;
UC_RISCV_REG_INSTRET = 46;
UC_RISCV_REG_HPMCOUNTER3 = 47;
UC_RISCV_REG_HPMCOUNTER4 = 48;
UC_RISCV_REG_HPMCOUNTER5 = 49;
UC_RISCV_REG_HPMCOUNTER6 = 50;
UC_RISCV_REG_HPMCOUNTER7 = 51;
UC_RISCV_REG_HPMCOUNTER8 = 52;
UC_RISCV_REG_HPMCOUNTER9 = 53;
UC_RISCV_REG_HPMCOUNTER10 = 54;
UC_RISCV_REG_HPMCOUNTER11 = 55;
UC_RISCV_REG_HPMCOUNTER12 = 56;
UC_RISCV_REG_HPMCOUNTER13 = 57;
UC_RISCV_REG_HPMCOUNTER14 = 58;
UC_RISCV_REG_HPMCOUNTER15 = 59;
UC_RISCV_REG_HPMCOUNTER16 = 60;
UC_RISCV_REG_HPMCOUNTER17 = 61;
UC_RISCV_REG_HPMCOUNTER18 = 62;
UC_RISCV_REG_HPMCOUNTER19 = 63;
UC_RISCV_REG_HPMCOUNTER20 = 64;
UC_RISCV_REG_HPMCOUNTER21 = 65;
UC_RISCV_REG_HPMCOUNTER22 = 66;
UC_RISCV_REG_HPMCOUNTER23 = 67;
UC_RISCV_REG_HPMCOUNTER24 = 68;
UC_RISCV_REG_HPMCOUNTER25 = 69;
UC_RISCV_REG_HPMCOUNTER26 = 70;
UC_RISCV_REG_HPMCOUNTER27 = 71;
UC_RISCV_REG_HPMCOUNTER28 = 72;
UC_RISCV_REG_HPMCOUNTER29 = 73;
UC_RISCV_REG_HPMCOUNTER30 = 74;
UC_RISCV_REG_HPMCOUNTER31 = 75;
UC_RISCV_REG_CYCLEH = 76;
UC_RISCV_REG_TIMEH = 77;
UC_RISCV_REG_INSTRETH = 78;
UC_RISCV_REG_HPMCOUNTER3H = 79;
UC_RISCV_REG_HPMCOUNTER4H = 80;
UC_RISCV_REG_HPMCOUNTER5H = 81;
UC_RISCV_REG_HPMCOUNTER6H = 82;
UC_RISCV_REG_HPMCOUNTER7H = 83;
UC_RISCV_REG_HPMCOUNTER8H = 84;
UC_RISCV_REG_HPMCOUNTER9H = 85;
UC_RISCV_REG_HPMCOUNTER10H = 86;
UC_RISCV_REG_HPMCOUNTER11H = 87;
UC_RISCV_REG_HPMCOUNTER12H = 88;
UC_RISCV_REG_HPMCOUNTER13H = 89;
UC_RISCV_REG_HPMCOUNTER14H = 90;
UC_RISCV_REG_HPMCOUNTER15H = 91;
UC_RISCV_REG_HPMCOUNTER16H = 92;
UC_RISCV_REG_HPMCOUNTER17H = 93;
UC_RISCV_REG_HPMCOUNTER18H = 94;
UC_RISCV_REG_HPMCOUNTER19H = 95;
UC_RISCV_REG_HPMCOUNTER20H = 96;
UC_RISCV_REG_HPMCOUNTER21H = 97;
UC_RISCV_REG_HPMCOUNTER22H = 98;
UC_RISCV_REG_HPMCOUNTER23H = 99;
UC_RISCV_REG_HPMCOUNTER24H = 100;
UC_RISCV_REG_HPMCOUNTER25H = 101;
UC_RISCV_REG_HPMCOUNTER26H = 102;
UC_RISCV_REG_HPMCOUNTER27H = 103;
UC_RISCV_REG_HPMCOUNTER28H = 104;
UC_RISCV_REG_HPMCOUNTER29H = 105;
UC_RISCV_REG_HPMCOUNTER30H = 106;
UC_RISCV_REG_HPMCOUNTER31H = 107;
UC_RISCV_REG_MCYCLE = 108;
UC_RISCV_REG_MINSTRET = 109;
UC_RISCV_REG_MCYCLEH = 110;
UC_RISCV_REG_MINSTRETH = 111;
UC_RISCV_REG_MVENDORID = 112;
UC_RISCV_REG_MARCHID = 113;
UC_RISCV_REG_MIMPID = 114;
UC_RISCV_REG_MHARTID = 115;
UC_RISCV_REG_MSTATUS = 116;
UC_RISCV_REG_MISA = 117;
UC_RISCV_REG_MEDELEG = 118;
UC_RISCV_REG_MIDELEG = 119;
UC_RISCV_REG_MIE = 120;
UC_RISCV_REG_MTVEC = 121;
UC_RISCV_REG_MCOUNTEREN = 122;
UC_RISCV_REG_MSTATUSH = 123;
UC_RISCV_REG_MUCOUNTEREN = 124;
UC_RISCV_REG_MSCOUNTEREN = 125;
UC_RISCV_REG_MHCOUNTEREN = 126;
UC_RISCV_REG_MSCRATCH = 127;
UC_RISCV_REG_MEPC = 128;
UC_RISCV_REG_MCAUSE = 129;
UC_RISCV_REG_MTVAL = 130;
UC_RISCV_REG_MIP = 131;
UC_RISCV_REG_MBADADDR = 132;
UC_RISCV_REG_SSTATUS = 133;
UC_RISCV_REG_SEDELEG = 134;
UC_RISCV_REG_SIDELEG = 135;
UC_RISCV_REG_SIE = 136;
UC_RISCV_REG_STVEC = 137;
UC_RISCV_REG_SCOUNTEREN = 138;
UC_RISCV_REG_SSCRATCH = 139;
UC_RISCV_REG_SEPC = 140;
UC_RISCV_REG_SCAUSE = 141;
UC_RISCV_REG_STVAL = 142;
UC_RISCV_REG_SIP = 143;
UC_RISCV_REG_SBADADDR = 144;
UC_RISCV_REG_SPTBR = 145;
UC_RISCV_REG_SATP = 146;
UC_RISCV_REG_HSTATUS = 147;
UC_RISCV_REG_HEDELEG = 148;
UC_RISCV_REG_HIDELEG = 149;
UC_RISCV_REG_HIE = 150;
UC_RISCV_REG_HCOUNTEREN = 151;
UC_RISCV_REG_HTVAL = 152;
UC_RISCV_REG_HIP = 153;
UC_RISCV_REG_HTINST = 154;
UC_RISCV_REG_HGATP = 155;
UC_RISCV_REG_HTIMEDELTA = 156;
UC_RISCV_REG_HTIMEDELTAH = 157;
// Floating-point registers // Floating-point registers
UC_RISCV_REG_F0 = 33; UC_RISCV_REG_F0 = 158;
UC_RISCV_REG_F1 = 34; UC_RISCV_REG_F1 = 159;
UC_RISCV_REG_F2 = 35; UC_RISCV_REG_F2 = 160;
UC_RISCV_REG_F3 = 36; UC_RISCV_REG_F3 = 161;
UC_RISCV_REG_F4 = 37; UC_RISCV_REG_F4 = 162;
UC_RISCV_REG_F5 = 38; UC_RISCV_REG_F5 = 163;
UC_RISCV_REG_F6 = 39; UC_RISCV_REG_F6 = 164;
UC_RISCV_REG_F7 = 40; UC_RISCV_REG_F7 = 165;
UC_RISCV_REG_F8 = 41; UC_RISCV_REG_F8 = 166;
UC_RISCV_REG_F9 = 42; UC_RISCV_REG_F9 = 167;
UC_RISCV_REG_F10 = 43; UC_RISCV_REG_F10 = 168;
UC_RISCV_REG_F11 = 44; UC_RISCV_REG_F11 = 169;
UC_RISCV_REG_F12 = 45; UC_RISCV_REG_F12 = 170;
UC_RISCV_REG_F13 = 46; UC_RISCV_REG_F13 = 171;
UC_RISCV_REG_F14 = 47; UC_RISCV_REG_F14 = 172;
UC_RISCV_REG_F15 = 48; UC_RISCV_REG_F15 = 173;
UC_RISCV_REG_F16 = 49; UC_RISCV_REG_F16 = 174;
UC_RISCV_REG_F17 = 50; UC_RISCV_REG_F17 = 175;
UC_RISCV_REG_F18 = 51; UC_RISCV_REG_F18 = 176;
UC_RISCV_REG_F19 = 52; UC_RISCV_REG_F19 = 177;
UC_RISCV_REG_F20 = 53; UC_RISCV_REG_F20 = 178;
UC_RISCV_REG_F21 = 54; UC_RISCV_REG_F21 = 179;
UC_RISCV_REG_F22 = 55; UC_RISCV_REG_F22 = 180;
UC_RISCV_REG_F23 = 56; UC_RISCV_REG_F23 = 181;
UC_RISCV_REG_F24 = 57; UC_RISCV_REG_F24 = 182;
UC_RISCV_REG_F25 = 58; UC_RISCV_REG_F25 = 183;
UC_RISCV_REG_F26 = 59; UC_RISCV_REG_F26 = 184;
UC_RISCV_REG_F27 = 60; UC_RISCV_REG_F27 = 185;
UC_RISCV_REG_F28 = 61; UC_RISCV_REG_F28 = 186;
UC_RISCV_REG_F29 = 62; UC_RISCV_REG_F29 = 187;
UC_RISCV_REG_F30 = 63; UC_RISCV_REG_F30 = 188;
UC_RISCV_REG_F31 = 64; UC_RISCV_REG_F31 = 189;
UC_RISCV_REG_PC = 65; UC_RISCV_REG_PC = 190;
UC_RISCV_REG_ENDING = 66; UC_RISCV_REG_ENDING = 191;
// Alias registers // Alias registers
UC_RISCV_REG_ZERO = 1; UC_RISCV_REG_ZERO = 1;
@ -127,38 +254,38 @@ const
UC_RISCV_REG_T4 = 30; UC_RISCV_REG_T4 = 30;
UC_RISCV_REG_T5 = 31; UC_RISCV_REG_T5 = 31;
UC_RISCV_REG_T6 = 32; UC_RISCV_REG_T6 = 32;
UC_RISCV_REG_FT0 = 33; UC_RISCV_REG_FT0 = 158;
UC_RISCV_REG_FT1 = 34; UC_RISCV_REG_FT1 = 159;
UC_RISCV_REG_FT2 = 35; UC_RISCV_REG_FT2 = 160;
UC_RISCV_REG_FT3 = 36; UC_RISCV_REG_FT3 = 161;
UC_RISCV_REG_FT4 = 37; UC_RISCV_REG_FT4 = 162;
UC_RISCV_REG_FT5 = 38; UC_RISCV_REG_FT5 = 163;
UC_RISCV_REG_FT6 = 39; UC_RISCV_REG_FT6 = 164;
UC_RISCV_REG_FT7 = 40; UC_RISCV_REG_FT7 = 165;
UC_RISCV_REG_FS0 = 41; UC_RISCV_REG_FS0 = 166;
UC_RISCV_REG_FS1 = 42; UC_RISCV_REG_FS1 = 167;
UC_RISCV_REG_FA0 = 43; UC_RISCV_REG_FA0 = 168;
UC_RISCV_REG_FA1 = 44; UC_RISCV_REG_FA1 = 169;
UC_RISCV_REG_FA2 = 45; UC_RISCV_REG_FA2 = 170;
UC_RISCV_REG_FA3 = 46; UC_RISCV_REG_FA3 = 171;
UC_RISCV_REG_FA4 = 47; UC_RISCV_REG_FA4 = 172;
UC_RISCV_REG_FA5 = 48; UC_RISCV_REG_FA5 = 173;
UC_RISCV_REG_FA6 = 49; UC_RISCV_REG_FA6 = 174;
UC_RISCV_REG_FA7 = 50; UC_RISCV_REG_FA7 = 175;
UC_RISCV_REG_FS2 = 51; UC_RISCV_REG_FS2 = 176;
UC_RISCV_REG_FS3 = 52; UC_RISCV_REG_FS3 = 177;
UC_RISCV_REG_FS4 = 53; UC_RISCV_REG_FS4 = 178;
UC_RISCV_REG_FS5 = 54; UC_RISCV_REG_FS5 = 179;
UC_RISCV_REG_FS6 = 55; UC_RISCV_REG_FS6 = 180;
UC_RISCV_REG_FS7 = 56; UC_RISCV_REG_FS7 = 181;
UC_RISCV_REG_FS8 = 57; UC_RISCV_REG_FS8 = 182;
UC_RISCV_REG_FS9 = 58; UC_RISCV_REG_FS9 = 183;
UC_RISCV_REG_FS10 = 59; UC_RISCV_REG_FS10 = 184;
UC_RISCV_REG_FS11 = 60; UC_RISCV_REG_FS11 = 185;
UC_RISCV_REG_FT8 = 61; UC_RISCV_REG_FT8 = 186;
UC_RISCV_REG_FT9 = 62; UC_RISCV_REG_FT9 = 187;
UC_RISCV_REG_FT10 = 63; UC_RISCV_REG_FT10 = 188;
UC_RISCV_REG_FT11 = 64; UC_RISCV_REG_FT11 = 189;
implementation implementation
end. end.

128
bindings/pascal/unicorn/S390xConst.pas Normal file
View File

@ -0,0 +1,128 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
unit S390xConst;
interface
const
// S390X CPU
UC_CPU_S390X_Z900 = 0;
UC_CPU_S390X_Z900_2 = 1;
UC_CPU_S390X_Z900_3 = 2;
UC_CPU_S390X_Z800 = 3;
UC_CPU_S390X_Z990 = 4;
UC_CPU_S390X_Z990_2 = 5;
UC_CPU_S390X_Z990_3 = 6;
UC_CPU_S390X_Z890 = 7;
UC_CPU_S390X_Z990_4 = 8;
UC_CPU_S390X_Z890_2 = 9;
UC_CPU_S390X_Z990_5 = 10;
UC_CPU_S390X_Z890_3 = 11;
UC_CPU_S390X_Z9EC = 12;
UC_CPU_S390X_Z9EC_2 = 13;
UC_CPU_S390X_Z9BC = 14;
UC_CPU_S390X_Z9EC_3 = 15;
UC_CPU_S390X_Z9BC_2 = 16;
UC_CPU_S390X_Z10EC = 17;
UC_CPU_S390X_Z10EC_2 = 18;
UC_CPU_S390X_Z10BC = 19;
UC_CPU_S390X_Z10EC_3 = 20;
UC_CPU_S390X_Z10BC_2 = 21;
UC_CPU_S390X_Z196 = 22;
UC_CPU_S390X_Z196_2 = 23;
UC_CPU_S390X_Z114 = 24;
UC_CPU_S390X_ZEC12 = 25;
UC_CPU_S390X_ZEC12_2 = 26;
UC_CPU_S390X_ZBC12 = 27;
UC_CPU_S390X_Z13 = 28;
UC_CPU_S390X_Z13_2 = 29;
UC_CPU_S390X_Z13S = 30;
UC_CPU_S390X_Z14 = 31;
UC_CPU_S390X_Z14_2 = 32;
UC_CPU_S390X_Z14ZR1 = 33;
UC_CPU_S390X_GEN15A = 34;
UC_CPU_S390X_GEN15B = 35;
UC_CPU_S390X_QEMU = 36;
UC_CPU_S390X_MAX = 37;
// S390X registers
UC_S390X_REG_INVALID = 0;
// General purpose registers
UC_S390X_REG_R0 = 1;
UC_S390X_REG_R1 = 2;
UC_S390X_REG_R2 = 3;
UC_S390X_REG_R3 = 4;
UC_S390X_REG_R4 = 5;
UC_S390X_REG_R5 = 6;
UC_S390X_REG_R6 = 7;
UC_S390X_REG_R7 = 8;
UC_S390X_REG_R8 = 9;
UC_S390X_REG_R9 = 10;
UC_S390X_REG_R10 = 11;
UC_S390X_REG_R11 = 12;
UC_S390X_REG_R12 = 13;
UC_S390X_REG_R13 = 14;
UC_S390X_REG_R14 = 15;
UC_S390X_REG_R15 = 16;
// Floating point registers
UC_S390X_REG_F0 = 17;
UC_S390X_REG_F1 = 18;
UC_S390X_REG_F2 = 19;
UC_S390X_REG_F3 = 20;
UC_S390X_REG_F4 = 21;
UC_S390X_REG_F5 = 22;
UC_S390X_REG_F6 = 23;
UC_S390X_REG_F7 = 24;
UC_S390X_REG_F8 = 25;
UC_S390X_REG_F9 = 26;
UC_S390X_REG_F10 = 27;
UC_S390X_REG_F11 = 28;
UC_S390X_REG_F12 = 29;
UC_S390X_REG_F13 = 30;
UC_S390X_REG_F14 = 31;
UC_S390X_REG_F15 = 32;
UC_S390X_REG_F16 = 33;
UC_S390X_REG_F17 = 34;
UC_S390X_REG_F18 = 35;
UC_S390X_REG_F19 = 36;
UC_S390X_REG_F20 = 37;
UC_S390X_REG_F21 = 38;
UC_S390X_REG_F22 = 39;
UC_S390X_REG_F23 = 40;
UC_S390X_REG_F24 = 41;
UC_S390X_REG_F25 = 42;
UC_S390X_REG_F26 = 43;
UC_S390X_REG_F27 = 44;
UC_S390X_REG_F28 = 45;
UC_S390X_REG_F29 = 46;
UC_S390X_REG_F30 = 47;
UC_S390X_REG_F31 = 48;
// Access registers
UC_S390X_REG_A0 = 49;
UC_S390X_REG_A1 = 50;
UC_S390X_REG_A2 = 51;
UC_S390X_REG_A3 = 52;
UC_S390X_REG_A4 = 53;
UC_S390X_REG_A5 = 54;
UC_S390X_REG_A6 = 55;
UC_S390X_REG_A7 = 56;
UC_S390X_REG_A8 = 57;
UC_S390X_REG_A9 = 58;
UC_S390X_REG_A10 = 59;
UC_S390X_REG_A11 = 60;
UC_S390X_REG_A12 = 61;
UC_S390X_REG_A13 = 62;
UC_S390X_REG_A14 = 63;
UC_S390X_REG_A15 = 64;
UC_S390X_REG_PC = 65;
UC_S390X_REG_ENDING = 66;
// Alias registers
implementation
end.

9
bindings/pascal/unicorn/UnicornConst.pas
View File

@ -7,11 +7,15 @@ interface
const UC_API_MAJOR = 2; const UC_API_MAJOR = 2;
UC_API_MINOR = 0; UC_API_MINOR = 0;
UC_API_PATCH = 0;
UC_API_EXTRA = 5;
UC_VERSION_MAJOR = 2; UC_VERSION_MAJOR = 2;
UC_VERSION_MINOR = 0; UC_VERSION_MINOR = 0;
UC_VERSION_EXTRA = 0; UC_VERSION_PATCH = 0;
UC_VERSION_EXTRA = 5;
UC_SECOND_SCALE = 1000000; UC_SECOND_SCALE = 1000000;
UC_MILISECOND_SCALE = 1000; UC_MILISECOND_SCALE = 1000;
UC_ARCH_ARM = 1; UC_ARCH_ARM = 1;
@ -22,7 +26,8 @@ const UC_API_MAJOR = 2;
UC_ARCH_SPARC = 6; UC_ARCH_SPARC = 6;
UC_ARCH_M68K = 7; UC_ARCH_M68K = 7;
UC_ARCH_RISCV = 8; UC_ARCH_RISCV = 8;
UC_ARCH_MAX = 9; UC_ARCH_S390X = 9;
UC_ARCH_MAX = 10;
UC_MODE_LITTLE_ENDIAN = 0; UC_MODE_LITTLE_ENDIAN = 0;
UC_MODE_BIG_ENDIAN = 1073741824; UC_MODE_BIG_ENDIAN = 1073741824;

18
bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb
View File

@ -4,15 +4,15 @@ module UnicornEngine
# M68K CPU # M68K CPU
UC_CPU_M5206_CPU = 0 UC_CPU_M68K_M5206 = 0
UC_CPU_M68000_CPU = 1 UC_CPU_M68K_M68000 = 1
UC_CPU_M68020_CPU = 2 UC_CPU_M68K_M68020 = 2
UC_CPU_M68030_CPU = 3 UC_CPU_M68K_M68030 = 3
UC_CPU_M68040_CPU = 4 UC_CPU_M68K_M68040 = 4
UC_CPU_M68060_CPU = 5 UC_CPU_M68K_M68060 = 5
UC_CPU_M5208_CPU = 6 UC_CPU_M68K_M5208 = 6
UC_CPU_CFV4E_CPU = 7 UC_CPU_M68K_CFV4E = 7
UC_CPU_ANY_CPU = 8 UC_CPU_M68K_ANY = 8
# M68K registers # M68K registers

259
bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb
View File

@ -54,41 +54,168 @@ module UnicornEngine
UC_RISCV_REG_X30 = 31 UC_RISCV_REG_X30 = 31
UC_RISCV_REG_X31 = 32 UC_RISCV_REG_X31 = 32
# RISCV CSR
UC_RISCV_REG_USTATUS = 33
UC_RISCV_REG_UIE = 34
UC_RISCV_REG_UTVEC = 35
UC_RISCV_REG_USCRATCH = 36
UC_RISCV_REG_UEPC = 37
UC_RISCV_REG_UCAUSE = 38
UC_RISCV_REG_UTVAL = 39
UC_RISCV_REG_UIP = 40
UC_RISCV_REG_FFLAGS = 41
UC_RISCV_REG_FRM = 42
UC_RISCV_REG_FCSR = 43
UC_RISCV_REG_CYCLE = 44
UC_RISCV_REG_TIME = 45
UC_RISCV_REG_INSTRET = 46
UC_RISCV_REG_HPMCOUNTER3 = 47
UC_RISCV_REG_HPMCOUNTER4 = 48
UC_RISCV_REG_HPMCOUNTER5 = 49
UC_RISCV_REG_HPMCOUNTER6 = 50
UC_RISCV_REG_HPMCOUNTER7 = 51
UC_RISCV_REG_HPMCOUNTER8 = 52
UC_RISCV_REG_HPMCOUNTER9 = 53
UC_RISCV_REG_HPMCOUNTER10 = 54
UC_RISCV_REG_HPMCOUNTER11 = 55
UC_RISCV_REG_HPMCOUNTER12 = 56
UC_RISCV_REG_HPMCOUNTER13 = 57
UC_RISCV_REG_HPMCOUNTER14 = 58
UC_RISCV_REG_HPMCOUNTER15 = 59
UC_RISCV_REG_HPMCOUNTER16 = 60
UC_RISCV_REG_HPMCOUNTER17 = 61
UC_RISCV_REG_HPMCOUNTER18 = 62
UC_RISCV_REG_HPMCOUNTER19 = 63
UC_RISCV_REG_HPMCOUNTER20 = 64
UC_RISCV_REG_HPMCOUNTER21 = 65
UC_RISCV_REG_HPMCOUNTER22 = 66
UC_RISCV_REG_HPMCOUNTER23 = 67
UC_RISCV_REG_HPMCOUNTER24 = 68
UC_RISCV_REG_HPMCOUNTER25 = 69
UC_RISCV_REG_HPMCOUNTER26 = 70
UC_RISCV_REG_HPMCOUNTER27 = 71
UC_RISCV_REG_HPMCOUNTER28 = 72
UC_RISCV_REG_HPMCOUNTER29 = 73
UC_RISCV_REG_HPMCOUNTER30 = 74
UC_RISCV_REG_HPMCOUNTER31 = 75
UC_RISCV_REG_CYCLEH = 76
UC_RISCV_REG_TIMEH = 77
UC_RISCV_REG_INSTRETH = 78
UC_RISCV_REG_HPMCOUNTER3H = 79
UC_RISCV_REG_HPMCOUNTER4H = 80
UC_RISCV_REG_HPMCOUNTER5H = 81
UC_RISCV_REG_HPMCOUNTER6H = 82
UC_RISCV_REG_HPMCOUNTER7H = 83
UC_RISCV_REG_HPMCOUNTER8H = 84
UC_RISCV_REG_HPMCOUNTER9H = 85
UC_RISCV_REG_HPMCOUNTER10H = 86
UC_RISCV_REG_HPMCOUNTER11H = 87
UC_RISCV_REG_HPMCOUNTER12H = 88
UC_RISCV_REG_HPMCOUNTER13H = 89
UC_RISCV_REG_HPMCOUNTER14H = 90
UC_RISCV_REG_HPMCOUNTER15H = 91
UC_RISCV_REG_HPMCOUNTER16H = 92
UC_RISCV_REG_HPMCOUNTER17H = 93
UC_RISCV_REG_HPMCOUNTER18H = 94
UC_RISCV_REG_HPMCOUNTER19H = 95
UC_RISCV_REG_HPMCOUNTER20H = 96
UC_RISCV_REG_HPMCOUNTER21H = 97
UC_RISCV_REG_HPMCOUNTER22H = 98
UC_RISCV_REG_HPMCOUNTER23H = 99
UC_RISCV_REG_HPMCOUNTER24H = 100
UC_RISCV_REG_HPMCOUNTER25H = 101
UC_RISCV_REG_HPMCOUNTER26H = 102
UC_RISCV_REG_HPMCOUNTER27H = 103
UC_RISCV_REG_HPMCOUNTER28H = 104
UC_RISCV_REG_HPMCOUNTER29H = 105
UC_RISCV_REG_HPMCOUNTER30H = 106
UC_RISCV_REG_HPMCOUNTER31H = 107
UC_RISCV_REG_MCYCLE = 108
UC_RISCV_REG_MINSTRET = 109
UC_RISCV_REG_MCYCLEH = 110
UC_RISCV_REG_MINSTRETH = 111
UC_RISCV_REG_MVENDORID = 112
UC_RISCV_REG_MARCHID = 113
UC_RISCV_REG_MIMPID = 114
UC_RISCV_REG_MHARTID = 115
UC_RISCV_REG_MSTATUS = 116
UC_RISCV_REG_MISA = 117
UC_RISCV_REG_MEDELEG = 118
UC_RISCV_REG_MIDELEG = 119
UC_RISCV_REG_MIE = 120
UC_RISCV_REG_MTVEC = 121
UC_RISCV_REG_MCOUNTEREN = 122
UC_RISCV_REG_MSTATUSH = 123
UC_RISCV_REG_MUCOUNTEREN = 124
UC_RISCV_REG_MSCOUNTEREN = 125
UC_RISCV_REG_MHCOUNTEREN = 126
UC_RISCV_REG_MSCRATCH = 127
UC_RISCV_REG_MEPC = 128
UC_RISCV_REG_MCAUSE = 129
UC_RISCV_REG_MTVAL = 130
UC_RISCV_REG_MIP = 131
UC_RISCV_REG_MBADADDR = 132
UC_RISCV_REG_SSTATUS = 133
UC_RISCV_REG_SEDELEG = 134
UC_RISCV_REG_SIDELEG = 135
UC_RISCV_REG_SIE = 136
UC_RISCV_REG_STVEC = 137
UC_RISCV_REG_SCOUNTEREN = 138
UC_RISCV_REG_SSCRATCH = 139
UC_RISCV_REG_SEPC = 140
UC_RISCV_REG_SCAUSE = 141
UC_RISCV_REG_STVAL = 142
UC_RISCV_REG_SIP = 143
UC_RISCV_REG_SBADADDR = 144
UC_RISCV_REG_SPTBR = 145
UC_RISCV_REG_SATP = 146
UC_RISCV_REG_HSTATUS = 147
UC_RISCV_REG_HEDELEG = 148
UC_RISCV_REG_HIDELEG = 149
UC_RISCV_REG_HIE = 150
UC_RISCV_REG_HCOUNTEREN = 151
UC_RISCV_REG_HTVAL = 152
UC_RISCV_REG_HIP = 153
UC_RISCV_REG_HTINST = 154
UC_RISCV_REG_HGATP = 155
UC_RISCV_REG_HTIMEDELTA = 156
UC_RISCV_REG_HTIMEDELTAH = 157
# Floating-point registers # Floating-point registers
UC_RISCV_REG_F0 = 33 UC_RISCV_REG_F0 = 158
UC_RISCV_REG_F1 = 34 UC_RISCV_REG_F1 = 159
UC_RISCV_REG_F2 = 35 UC_RISCV_REG_F2 = 160
UC_RISCV_REG_F3 = 36 UC_RISCV_REG_F3 = 161
UC_RISCV_REG_F4 = 37 UC_RISCV_REG_F4 = 162
UC_RISCV_REG_F5 = 38 UC_RISCV_REG_F5 = 163
UC_RISCV_REG_F6 = 39 UC_RISCV_REG_F6 = 164
UC_RISCV_REG_F7 = 40 UC_RISCV_REG_F7 = 165
UC_RISCV_REG_F8 = 41 UC_RISCV_REG_F8 = 166
UC_RISCV_REG_F9 = 42 UC_RISCV_REG_F9 = 167
UC_RISCV_REG_F10 = 43 UC_RISCV_REG_F10 = 168
UC_RISCV_REG_F11 = 44 UC_RISCV_REG_F11 = 169
UC_RISCV_REG_F12 = 45 UC_RISCV_REG_F12 = 170
UC_RISCV_REG_F13 = 46 UC_RISCV_REG_F13 = 171
UC_RISCV_REG_F14 = 47 UC_RISCV_REG_F14 = 172
UC_RISCV_REG_F15 = 48 UC_RISCV_REG_F15 = 173
UC_RISCV_REG_F16 = 49 UC_RISCV_REG_F16 = 174
UC_RISCV_REG_F17 = 50 UC_RISCV_REG_F17 = 175
UC_RISCV_REG_F18 = 51 UC_RISCV_REG_F18 = 176
UC_RISCV_REG_F19 = 52 UC_RISCV_REG_F19 = 177
UC_RISCV_REG_F20 = 53 UC_RISCV_REG_F20 = 178
UC_RISCV_REG_F21 = 54 UC_RISCV_REG_F21 = 179
UC_RISCV_REG_F22 = 55 UC_RISCV_REG_F22 = 180
UC_RISCV_REG_F23 = 56 UC_RISCV_REG_F23 = 181
UC_RISCV_REG_F24 = 57 UC_RISCV_REG_F24 = 182
UC_RISCV_REG_F25 = 58 UC_RISCV_REG_F25 = 183
UC_RISCV_REG_F26 = 59 UC_RISCV_REG_F26 = 184
UC_RISCV_REG_F27 = 60 UC_RISCV_REG_F27 = 185
UC_RISCV_REG_F28 = 61 UC_RISCV_REG_F28 = 186
UC_RISCV_REG_F29 = 62 UC_RISCV_REG_F29 = 187
UC_RISCV_REG_F30 = 63 UC_RISCV_REG_F30 = 188
UC_RISCV_REG_F31 = 64 UC_RISCV_REG_F31 = 189
UC_RISCV_REG_PC = 65 UC_RISCV_REG_PC = 190
UC_RISCV_REG_ENDING = 66 UC_RISCV_REG_ENDING = 191
# Alias registers # Alias registers
UC_RISCV_REG_ZERO = 1 UC_RISCV_REG_ZERO = 1
@ -124,36 +251,36 @@ module UnicornEngine
UC_RISCV_REG_T4 = 30 UC_RISCV_REG_T4 = 30
UC_RISCV_REG_T5 = 31 UC_RISCV_REG_T5 = 31
UC_RISCV_REG_T6 = 32 UC_RISCV_REG_T6 = 32
UC_RISCV_REG_FT0 = 33 UC_RISCV_REG_FT0 = 158
UC_RISCV_REG_FT1 = 34 UC_RISCV_REG_FT1 = 159
UC_RISCV_REG_FT2 = 35 UC_RISCV_REG_FT2 = 160
UC_RISCV_REG_FT3 = 36 UC_RISCV_REG_FT3 = 161
UC_RISCV_REG_FT4 = 37 UC_RISCV_REG_FT4 = 162
UC_RISCV_REG_FT5 = 38 UC_RISCV_REG_FT5 = 163
UC_RISCV_REG_FT6 = 39 UC_RISCV_REG_FT6 = 164
UC_RISCV_REG_FT7 = 40 UC_RISCV_REG_FT7 = 165
UC_RISCV_REG_FS0 = 41 UC_RISCV_REG_FS0 = 166
UC_RISCV_REG_FS1 = 42 UC_RISCV_REG_FS1 = 167
UC_RISCV_REG_FA0 = 43 UC_RISCV_REG_FA0 = 168
UC_RISCV_REG_FA1 = 44 UC_RISCV_REG_FA1 = 169
UC_RISCV_REG_FA2 = 45 UC_RISCV_REG_FA2 = 170
UC_RISCV_REG_FA3 = 46 UC_RISCV_REG_FA3 = 171
UC_RISCV_REG_FA4 = 47 UC_RISCV_REG_FA4 = 172
UC_RISCV_REG_FA5 = 48 UC_RISCV_REG_FA5 = 173
UC_RISCV_REG_FA6 = 49 UC_RISCV_REG_FA6 = 174
UC_RISCV_REG_FA7 = 50 UC_RISCV_REG_FA7 = 175
UC_RISCV_REG_FS2 = 51 UC_RISCV_REG_FS2 = 176
UC_RISCV_REG_FS3 = 52 UC_RISCV_REG_FS3 = 177
UC_RISCV_REG_FS4 = 53 UC_RISCV_REG_FS4 = 178
UC_RISCV_REG_FS5 = 54 UC_RISCV_REG_FS5 = 179
UC_RISCV_REG_FS6 = 55 UC_RISCV_REG_FS6 = 180
UC_RISCV_REG_FS7 = 56 UC_RISCV_REG_FS7 = 181
UC_RISCV_REG_FS8 = 57 UC_RISCV_REG_FS8 = 182
UC_RISCV_REG_FS9 = 58 UC_RISCV_REG_FS9 = 183
UC_RISCV_REG_FS10 = 59 UC_RISCV_REG_FS10 = 184
UC_RISCV_REG_FS11 = 60 UC_RISCV_REG_FS11 = 185
UC_RISCV_REG_FT8 = 61 UC_RISCV_REG_FT8 = 186
UC_RISCV_REG_FT9 = 62 UC_RISCV_REG_FT9 = 187
UC_RISCV_REG_FT10 = 63 UC_RISCV_REG_FT10 = 188
UC_RISCV_REG_FT11 = 64 UC_RISCV_REG_FT11 = 189
end end

123
bindings/ruby/unicorn_gem/lib/unicorn_engine/s390x_const.rb Normal file
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@ -0,0 +1,123 @@
# For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [s390x_const.rb]
module UnicornEngine
# S390X CPU
UC_CPU_S390X_Z900 = 0
UC_CPU_S390X_Z900_2 = 1
UC_CPU_S390X_Z900_3 = 2
UC_CPU_S390X_Z800 = 3
UC_CPU_S390X_Z990 = 4
UC_CPU_S390X_Z990_2 = 5
UC_CPU_S390X_Z990_3 = 6
UC_CPU_S390X_Z890 = 7
UC_CPU_S390X_Z990_4 = 8
UC_CPU_S390X_Z890_2 = 9
UC_CPU_S390X_Z990_5 = 10
UC_CPU_S390X_Z890_3 = 11
UC_CPU_S390X_Z9EC = 12
UC_CPU_S390X_Z9EC_2 = 13
UC_CPU_S390X_Z9BC = 14
UC_CPU_S390X_Z9EC_3 = 15
UC_CPU_S390X_Z9BC_2 = 16
UC_CPU_S390X_Z10EC = 17
UC_CPU_S390X_Z10EC_2 = 18
UC_CPU_S390X_Z10BC = 19
UC_CPU_S390X_Z10EC_3 = 20
UC_CPU_S390X_Z10BC_2 = 21
UC_CPU_S390X_Z196 = 22
UC_CPU_S390X_Z196_2 = 23
UC_CPU_S390X_Z114 = 24
UC_CPU_S390X_ZEC12 = 25
UC_CPU_S390X_ZEC12_2 = 26
UC_CPU_S390X_ZBC12 = 27
UC_CPU_S390X_Z13 = 28
UC_CPU_S390X_Z13_2 = 29
UC_CPU_S390X_Z13S = 30
UC_CPU_S390X_Z14 = 31
UC_CPU_S390X_Z14_2 = 32
UC_CPU_S390X_Z14ZR1 = 33
UC_CPU_S390X_GEN15A = 34
UC_CPU_S390X_GEN15B = 35
UC_CPU_S390X_QEMU = 36
UC_CPU_S390X_MAX = 37
# S390X registers
UC_S390X_REG_INVALID = 0
# General purpose registers
UC_S390X_REG_R0 = 1
UC_S390X_REG_R1 = 2
UC_S390X_REG_R2 = 3
UC_S390X_REG_R3 = 4
UC_S390X_REG_R4 = 5
UC_S390X_REG_R5 = 6
UC_S390X_REG_R6 = 7
UC_S390X_REG_R7 = 8
UC_S390X_REG_R8 = 9
UC_S390X_REG_R9 = 10
UC_S390X_REG_R10 = 11
UC_S390X_REG_R11 = 12
UC_S390X_REG_R12 = 13
UC_S390X_REG_R13 = 14
UC_S390X_REG_R14 = 15
UC_S390X_REG_R15 = 16
# Floating point registers
UC_S390X_REG_F0 = 17
UC_S390X_REG_F1 = 18
UC_S390X_REG_F2 = 19
UC_S390X_REG_F3 = 20
UC_S390X_REG_F4 = 21
UC_S390X_REG_F5 = 22
UC_S390X_REG_F6 = 23
UC_S390X_REG_F7 = 24
UC_S390X_REG_F8 = 25
UC_S390X_REG_F9 = 26
UC_S390X_REG_F10 = 27
UC_S390X_REG_F11 = 28
UC_S390X_REG_F12 = 29
UC_S390X_REG_F13 = 30
UC_S390X_REG_F14 = 31
UC_S390X_REG_F15 = 32
UC_S390X_REG_F16 = 33
UC_S390X_REG_F17 = 34
UC_S390X_REG_F18 = 35
UC_S390X_REG_F19 = 36
UC_S390X_REG_F20 = 37
UC_S390X_REG_F21 = 38
UC_S390X_REG_F22 = 39
UC_S390X_REG_F23 = 40
UC_S390X_REG_F24 = 41
UC_S390X_REG_F25 = 42
UC_S390X_REG_F26 = 43
UC_S390X_REG_F27 = 44
UC_S390X_REG_F28 = 45
UC_S390X_REG_F29 = 46
UC_S390X_REG_F30 = 47
UC_S390X_REG_F31 = 48
# Access registers
UC_S390X_REG_A0 = 49
UC_S390X_REG_A1 = 50
UC_S390X_REG_A2 = 51
UC_S390X_REG_A3 = 52
UC_S390X_REG_A4 = 53
UC_S390X_REG_A5 = 54
UC_S390X_REG_A6 = 55
UC_S390X_REG_A7 = 56
UC_S390X_REG_A8 = 57
UC_S390X_REG_A9 = 58
UC_S390X_REG_A10 = 59
UC_S390X_REG_A11 = 60
UC_S390X_REG_A12 = 61
UC_S390X_REG_A13 = 62
UC_S390X_REG_A14 = 63
UC_S390X_REG_A15 = 64
UC_S390X_REG_PC = 65
UC_S390X_REG_ENDING = 66
# Alias registers
end

9
bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb
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@ -4,11 +4,15 @@ module UnicornEngine
UC_API_MAJOR = 2 UC_API_MAJOR = 2
UC_API_MINOR = 0 UC_API_MINOR = 0
UC_API_PATCH = 0
UC_API_EXTRA = 5
UC_VERSION_MAJOR = 2 UC_VERSION_MAJOR = 2
UC_VERSION_MINOR = 0 UC_VERSION_MINOR = 0
UC_VERSION_EXTRA = 0 UC_VERSION_PATCH = 0
UC_VERSION_EXTRA = 5
UC_SECOND_SCALE = 1000000 UC_SECOND_SCALE = 1000000
UC_MILISECOND_SCALE = 1000 UC_MILISECOND_SCALE = 1000
UC_ARCH_ARM = 1 UC_ARCH_ARM = 1
@ -19,7 +23,8 @@ module UnicornEngine
UC_ARCH_SPARC = 6 UC_ARCH_SPARC = 6
UC_ARCH_M68K = 7 UC_ARCH_M68K = 7
UC_ARCH_RISCV = 8 UC_ARCH_RISCV = 8
UC_ARCH_MAX = 9 UC_ARCH_S390X = 9
UC_ARCH_MAX = 10
UC_MODE_LITTLE_ENDIAN = 0 UC_MODE_LITTLE_ENDIAN = 0
UC_MODE_BIG_ENDIAN = 1073741824 UC_MODE_BIG_ENDIAN = 1073741824