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Fix for MIPS issue. (#733)

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This commit is contained in:
xorstream
2017-01-23 15:39:34 +11:00
committed by Nguyen Anh Quynh
parent 2ecbe89cc1
commit 69ae8f7987
9 changed files with 229 additions and 227 deletions
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56
qemu/target-mips/translate.c
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@ -5458,7 +5458,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 27:
switch (sel) {
case 0: case 1: case 2: case 3:
case 0: case 1: case 2: case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr";
break;
@ -5524,7 +5524,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE";
break;
case 2: case 3: case 4: case 5: case 6: case 7:
case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -5947,7 +5947,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case 18:
switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -16274,7 +16274,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception(ctx, EXCP_RI);
}
break;
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU:
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU:
op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) {
case R6_OPC_DMUL:
@ -16422,7 +16422,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU:
case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt);
break;
case OPC_SLLV: /* Shifts */
@ -16458,7 +16458,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break;
case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ:
case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ:
case OPC_TNE:
gen_trap(ctx, op1, rs, rt, -1);
break;
@ -16533,7 +16533,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU:
case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt);
@ -16591,8 +16591,8 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) {
case OPC_MADD: case OPC_MADDU:
case OPC_MSUB: case OPC_MSUBU:
case OPC_MADD: case OPC_MADDU:
case OPC_MSUB: case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt);
break;
@ -16684,7 +16684,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL:
{
TCGv t0;
if (rd == 0) {
if (rd == 0) {
/* Treat as NOP. */
break;
}
@ -16693,7 +16693,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode);
switch (op2) {
case OPC_ALIGN: case OPC_ALIGN_END:
case OPC_ALIGN: case OPC_ALIGN_END:
sa &= 3;
if (sa == 0) {
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
@ -16730,7 +16730,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx);
{
TCGv t0;
if (rd == 0) {
if (rd == 0) {
/* Treat as NOP. */
break;
}
@ -16780,9 +16780,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) {
case OPC_DIV_G_2E: case OPC_DIVU_G_2E:
case OPC_MOD_G_2E: case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULTU_G_2E:
case OPC_DIV_G_2E: case OPC_DIVU_G_2E:
case OPC_MOD_G_2E: case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@ -17047,9 +17047,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E: case OPC_DMODU_G_2E:
case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E: case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt);
break;
@ -17324,9 +17324,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
}
break;
#if defined(TARGET_MIPS64)
case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT:
case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT:
case OPC_DINSM: case OPC_DINSU: case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2);
check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
@ -18587,7 +18587,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
}
break;
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */
case OPC_TNEI:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm);
@ -18645,7 +18645,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_C0_FIRST: case OPC_C0_LAST:
case OPC_C0_FIRST: case OPC_C0_LAST:
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */
@ -18740,7 +18740,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm);
break;
case OPC_J: case OPC_JAL: /* Jump */
case OPC_J: case OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break;
@ -18802,14 +18802,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_LWR:
case OPC_LL:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LB: case OPC_LH:
case OPC_LW: case OPC_LBU: case OPC_LHU:
case OPC_LB: case OPC_LH:
case OPC_LW: case OPC_LBU: case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SWL:
case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SB: case OPC_SH:
case OPC_SB: case OPC_SH:
case OPC_SW:
gen_st(ctx, op, rt, rs, imm);
break;
@ -19067,7 +19067,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
#if defined(TARGET_MIPS64)
/* MIPS64 opcodes */
case OPC_LDL: case OPC_LDR:
case OPC_LDL: case OPC_LDR:
case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LWU:
@ -19076,7 +19076,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm);
break;
case OPC_SDL: case OPC_SDR:
case OPC_SDL: case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SD:
check_insn(ctx, ISA_MIPS3);