Fix for MIPS issue. (#733)

This commit is contained in:
xorstream
2017-01-23 15:39:34 +11:00
committed by Nguyen Anh Quynh
parent 2ecbe89cc1
commit 69ae8f7987
9 changed files with 229 additions and 227 deletions

View File

@ -118,22 +118,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1278FF17,
0,
0,
0,
0,
32,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32,
CPU_MIPS32,
MMU_TYPE_R4000,
},
{
@ -149,24 +149,24 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1258FF17,
0,
0,
0,
0,
32,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32 | ASE_MIPS16,
CPU_MIPS32 | ASE_MIPS16,
MMU_TYPE_FMT,
},
{
@ -180,22 +180,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1278FF17,
0,
0,
0,
0,
0,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32,
CPU_MIPS32,
MMU_TYPE_R4000,
},
{
@ -209,22 +209,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1258FF17,
0,
0,
0,
0,
0,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32 | ASE_MIPS16,
CPU_MIPS32 | ASE_MIPS16,
MMU_TYPE_FMT,
},
{
@ -239,22 +239,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1278FF17,
0,
0,
0,
0,
32,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2,
CPU_MIPS32R2,
MMU_TYPE_R4000,
},
{
@ -269,22 +269,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x1258FF17,
0,
0,
0,
0,
32,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16,
CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_FMT,
},
{
@ -299,22 +299,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
/* No DSP implemented. */
0x1278FF1F,
0,
0,
0,
32,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16,
CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_R4000,
},
{
@ -329,24 +329,24 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
/* No DSP implemented. */
0x3678FF1F,
0,
0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
0,
32,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16,
CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_R4000,
},
{
@ -376,7 +376,7 @@ static const mips_def_t mips_defs[] =
0,
32,
32,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
0x3fffffff,
(1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@ -394,7 +394,7 @@ static const mips_def_t mips_defs[] =
(0x3fe << CP0SRSC4_SRS15) |
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
0,0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
MMU_TYPE_R4000,
},
{
@ -410,23 +410,23 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
(0 << CP0C3_VInt),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x3778FF1F,
0,
0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
0,
32,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
MMU_TYPE_R4000,
},
{
@ -450,22 +450,22 @@ static const mips_def_t mips_defs[] =
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
(0 << CP0C5_NFExists),
0,
0,
0,
0,
0,
4,
32,
2,
0x3778FF1F,
0,
0,
(1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
0,
(1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x93 << FCR0_PRID),
0,
32,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
@ -477,25 +477,25 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, the R4000 has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU),
0,
0,
0,0,
0,0,
0,
0,
0xFFFFFFFF,
0,
0,0,
0,0,
0,
0,
0xFFFFFFFF,
4,
16,
2,
0x3678FFFF,
0,
0,
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
0,
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
(0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
40,
40,
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS3,
CPU_MIPS3,
MMU_TYPE_R4000,
},
{
@ -505,25 +505,25 @@ static const mips_def_t mips_defs[] =
(1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
(1 << CP0C1_FP) | (47 << CP0C1_MMU),
0,
0,
0,0,
0,0,
0,
0,
0xFFFFFFFFL,
0,
0,0,
0,0,
0,
0,
0xFFFFFFFFL,
4,
16,
2,
0x3678FFFF,
0,
0,
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
0,
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
(0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
40,
40,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_VR54XX,
CPU_VR54XX,
MMU_TYPE_R4000,
},
{
@ -538,22 +538,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x32F8FFFF,
0,
0,
0,
0,
42,
0,
0,
0,
42,
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64,
CPU_MIPS64,
MMU_TYPE_R4000,
},
{
@ -568,25 +568,25 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
4,
32,
2,
0x36F8FFFF,
0,
0,
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
0,
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
(1 << FCR0_D) | (1 << FCR0_S) |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
42,
42,
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64,
CPU_MIPS64,
MMU_TYPE_R4000,
},
{
@ -603,25 +603,25 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3,
0,.0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
0,
32,
1,
0x36FBFFFF,
0,
0,
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
0,
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
(1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_D) | (1 << FCR0_S) |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
40,
40,
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64 | ASE_MIPS3D,
CPU_MIPS64 | ASE_MIPS3D,
MMU_TYPE_R4000,
},
{
@ -638,27 +638,27 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2,
MIPS_CONFIG3 | (1 << CP0C3_LPA),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
0,
32,
2,
0x36FBFFFF,
0,
0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
42,
42,
/* The architectural limit is 59, but we have hardcoded 36 bit
in some places...
59, */ /* the architectural limit */
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64R2 | ASE_MIPS3D,
CPU_MIPS64R2 | ASE_MIPS3D,
MMU_TYPE_R4000,
},
{
@ -678,32 +678,32 @@ static const mips_def_t mips_defs[] =
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1 << CP0C4_M),
0,
0,
(1 << CP0C5_SBRI),
0,
0,
0,
(1 << CP0C5_SBRI),
0,
0,
0,
0,
32,
2,
0x30D8FFFF,
0,
0,
0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
(0x0 << FCR0_REV),
0,
0,
42,
/* The architectural limit is 59, but we have hardcoded 36 bit
in some places...
59, */ /* the architectural limit */
36,
0,0, 0,0, 0,0, 0,0, 0,0,
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1U << CP0PG_RIE),
0,
CPU_MIPS64R6,
CPU_MIPS64R6,
MMU_TYPE_R4000,
},
{
@ -715,24 +715,24 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, Loongson-2E has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU),
0,
0,
0,0,
0,0,
0,
0,
0,
0,
16,
0,
0,0,
0,0,
0,
0,
0,
0,
16,
2,
0x35D0FFFF,
0,
0,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
40,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_LOONGSON2E,
CPU_LOONGSON2E,
MMU_TYPE_R4000,
},
{
@ -744,24 +744,24 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, Loongson-2F has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU),
0,
0,
0,0,
0,0,
0,
0,
0,
0,
16,
0,
0,0,
0,0,
0,
0,
0,
0,
16,
2,
0xF5D0FF1F, /*bit5:7 not writable*/
0,
0,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
40,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_LOONGSON2F,
CPU_LOONGSON2F,
MMU_TYPE_R4000,
},
{
@ -779,30 +779,30 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
(1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
0,0,
0,0,
0,
0,
0,
0,0,
0,
0,
0,
0,
32,
2,
0x37FBFFFF,
0,
0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
0,
42,
42,
/* The architectural limit is 59, but we have hardcoded 36 bit
in some places...
59, */ /* the architectural limit */
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
MMU_TYPE_R4000,
},
#endif
};