From 085ee07c73bfe1eeb806453ce03a576ed0baaf16 Mon Sep 17 00:00:00 2001 From: mio Date: Thu, 30 Dec 2021 01:05:10 +0100 Subject: [PATCH 01/18] No more hard-coded cpu models --- qemu/target/arm/cpu.c | 10 +++++----- qemu/target/i386/cpu.c | 4 ++-- qemu/target/m68k/cpu.c | 2 +- qemu/target/mips/cpu.c | 4 ++-- qemu/target/ppc/translate_init.inc.c | 4 ++-- qemu/target/riscv/cpu.c | 4 ++-- qemu/target/sparc/cpu.c | 4 ++-- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index ff8fb705..e034192c 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -2056,15 +2056,15 @@ ARMCPU *cpu_arm_init(struct uc_struct *uc) #if !defined(TARGET_AARCH64) if (uc->mode & UC_MODE_MCLASS) { - uc->cpu_model = 11; + uc->cpu_model = UC_CPU_ARM_CORTEX_M33; } else if (uc->mode & UC_MODE_ARM926) { - uc->cpu_model = 0; + uc->cpu_model = UC_CPU_ARM_926; } else if (uc->mode & UC_MODE_ARM946) { - uc->cpu_model = 1; + uc->cpu_model = UC_CPU_ARM_946; } else if (uc->mode & UC_MODE_ARM1176) { - uc->cpu_model = 5; + uc->cpu_model = UC_CPU_ARM_1176; } else if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 17; // cortex-a15 + uc->cpu_model = UC_CPU_ARM_CORTEX_A15; // cortex-a15 } else if (uc->cpu_model >= ARR_SIZE(arm_cpus)) { free(cpu); return NULL; diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index 3f1756e5..12953daa 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -5083,9 +5083,9 @@ X86CPU *cpu_x86_init(struct uc_struct *uc) if (uc->cpu_model == INT_MAX) { #ifdef TARGET_X86_64 - uc->cpu_model = 0; // qemu64 + uc->cpu_model = UC_CPU_X86_QEMU64; // qemu64 #else - uc->cpu_model = 4; // qemu32 + uc->cpu_model = UC_CPU_X86_QEMU32; // qemu32 #endif } else if (uc->cpu_model >= ARRAY_SIZE(builtin_x86_defs)) { free(cpu); diff --git a/qemu/target/m68k/cpu.c b/qemu/target/m68k/cpu.c index 8afc0c19..915b82ac 100644 --- a/qemu/target/m68k/cpu.c +++ b/qemu/target/m68k/cpu.c @@ -271,7 +271,7 @@ M68kCPU *cpu_m68k_init(struct uc_struct *uc) } if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 7; // cfv4e + uc->cpu_model = UC_CPU_M68K_CFV4E; // cfv4e } else if (uc->cpu_model >= ARRAY_SIZE(m68k_cpus_type_infos)) { free(cpu); return NULL; diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c index 60fd1b93..4ddf65e0 100644 --- a/qemu/target/mips/cpu.c +++ b/qemu/target/mips/cpu.c @@ -164,14 +164,14 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc) #ifdef TARGET_MIPS64 if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 17; // R4000 + uc->cpu_model = UC_CPU_MIPS64_R4000; // R4000 } else if (uc->cpu_model + UC_CPU_MIPS32_I7200 + 1 >= mips_defs_number ) { free(cpu); return NULL; } #else if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 10; // 74kf + uc->cpu_model = UC_CPU_MIPS32_74KF; // 74kf } else if (uc->cpu_model >= mips_defs_number) { free(cpu); return NULL; diff --git a/qemu/target/ppc/translate_init.inc.c b/qemu/target/ppc/translate_init.inc.c index 3f40bd60..65956ad1 100644 --- a/qemu/target/ppc/translate_init.inc.c +++ b/qemu/target/ppc/translate_init.inc.c @@ -11149,14 +11149,14 @@ PowerPCCPU *cpu_ppc_init(struct uc_struct *uc) memset(cpu, 0, sizeof(*cpu)); #ifdef TARGET_PPC64 if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 18 + UC_CPU_PPC_7457A_V1_2 + 1; // power10_v1.0 + uc->cpu_model = UC_CPU_PPC_POWER10_V1_0 + UC_CPU_PPC_7457A_V1_2 + 1; // power10_v1.0 } else if (uc->cpu_model + UC_CPU_PPC_7457A_V1_2 + 1 >= ARRAY_SIZE(ppc_cpus)) { free(cpu); return NULL; } #else if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 289; // 7457a_v1.2 + uc->cpu_model = UC_CPU_PPC_7457A_V1_2; // 7457a_v1.2 } else if (uc->cpu_model >= ARRAY_SIZE(ppc_cpus)) { free(cpu); return NULL; diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index 15d9349e..d58204ad 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -342,12 +342,12 @@ RISCVCPU *cpu_riscv_init(struct uc_struct *uc) #ifdef TARGET_RISCV32 if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 3; + uc->cpu_model = UC_CPU_RISCV32_SIFIVE_U34; } #else /* TARGET_RISCV64 */ if (uc->cpu_model == INT_MAX) { - uc->cpu_model = 3; + uc->cpu_model = UC_CPU_RISCV64_SIFIVE_U54; } #endif diff --git a/qemu/target/sparc/cpu.c b/qemu/target/sparc/cpu.c index 461d7687..489819bc 100644 --- a/qemu/target/sparc/cpu.c +++ b/qemu/target/sparc/cpu.c @@ -525,9 +525,9 @@ SPARCCPU *cpu_sparc_init(struct uc_struct *uc) if (uc->cpu_model == INT_MAX) { #ifdef TARGET_SPARC64 - uc->cpu_model = 11; // Sun UltraSparc IV + uc->cpu_model = UC_CPU_SPARC64_SUN_ULTRASPARC_IV; // Sun UltraSparc IV #else - uc->cpu_model = 12; // Leon 3 + uc->cpu_model = UC_CPU_SPARC32_LEON3; // Leon 3 #endif } else if (uc->cpu_model >= ARRAY_SIZE(sparc_defs)) { free(cpu); From 7dc858d03d48827619978cbc7ac18855208097a8 Mon Sep 17 00:00:00 2001 From: lazymio Date: Tue, 4 Jan 2022 20:30:07 +0100 Subject: [PATCH 02/18] Add a test for arm privilege escalation --- tests/unit/test_arm.c | 48 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/tests/unit/test_arm.c b/tests/unit/test_arm.c index b148b204..a4e8072c 100644 --- a/tests/unit/test_arm.c +++ b/tests/unit/test_arm.c @@ -398,6 +398,52 @@ static void test_arm_thumb_smlabb() OK(uc_close(uc)); } +static void test_arm_not_allow_privilege_escalation() +{ + uc_engine *uc; + int r_cpsr, r_sp, r_spsr, r_lr; + // E3C6601F : BIC r6, r6, #&1F + // E3866013 : ORR r6, r6, #&13 + // E121F006 : MSR cpsr_c, r6 ; switch to SVC32 (should be ineffective + // from USR32) E1A00000 : MOV r0,r0 EF000011 : SWI OS_Exit + char code[] = "\x1f\x60\xc6\xe3\x13\x60\x86\xe3\x06\xf0\x21\xe1\x00\x00\xa0" + "\xe1\x11\x00\x00\xef"; + + uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_ARM_CORTEX_A9); + + // https://www.keil.com/pack/doc/CMSIS/Core_A/html/group__CMSIS__CPSR.html + r_cpsr = 0x40000013; // SVC32 + OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); + r_spsr = 0x40000013; + OK(uc_reg_write(uc, UC_ARM_REG_SPSR, &r_spsr)); + r_sp = 0x12345678; + OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp)); + r_lr = 0x00102220; + OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr)); + + r_cpsr = 0x40000010; // USR32 + OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); + r_sp = 0x0010000; + OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp)); + r_lr = 0x0001234; + OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr)); + + uc_assert_err( + UC_ERR_EXCEPTION, + uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); + + OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); + OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp)); + OK(uc_reg_read(uc, UC_ARM_REG_LR, &r_lr)); + + OK((r_cpsr & ((1 << 4) - 1)) == 0); // Stay in USR32 + OK(r_lr == 0x1234); + OK(r_sp == 0x10000); + + OK(uc_close(uc)); +} + TEST_LIST = {{"test_arm_nop", test_arm_nop}, {"test_arm_thumb_sub", test_arm_thumb_sub}, {"test_armeb_sub", test_armeb_sub}, @@ -410,4 +456,6 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop}, {"test_arm_usr32_to_svc32", test_arm_usr32_to_svc32}, {"test_arm_v8", test_arm_v8}, {"test_arm_thumb_smlabb", test_arm_thumb_smlabb}, + {"test_arm_not_allow_privilege_escalation", + test_arm_not_allow_privilege_escalation}, {NULL, NULL}}; \ No newline at end of file From 73149f36168021c4134c6bc591df3e725ae64fb6 Mon Sep 17 00:00:00 2001 From: lazymio Date: Tue, 4 Jan 2022 20:54:52 +0100 Subject: [PATCH 03/18] Fix test case --- tests/unit/test_arm.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tests/unit/test_arm.c b/tests/unit/test_arm.c index a4e8072c..80c07443 100644 --- a/tests/unit/test_arm.c +++ b/tests/unit/test_arm.c @@ -405,12 +405,13 @@ static void test_arm_not_allow_privilege_escalation() // E3C6601F : BIC r6, r6, #&1F // E3866013 : ORR r6, r6, #&13 // E121F006 : MSR cpsr_c, r6 ; switch to SVC32 (should be ineffective - // from USR32) E1A00000 : MOV r0,r0 EF000011 : SWI OS_Exit + // from USR32) + // E1A00000 : MOV r0,r0 EF000011 : SWI OS_Exit char code[] = "\x1f\x60\xc6\xe3\x13\x60\x86\xe3\x06\xf0\x21\xe1\x00\x00\xa0" "\xe1\x11\x00\x00\xef"; uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code, sizeof(code) - 1, - UC_CPU_ARM_CORTEX_A9); + UC_CPU_ARM_CORTEX_A15); // https://www.keil.com/pack/doc/CMSIS/Core_A/html/group__CMSIS__CPSR.html r_cpsr = 0x40000013; // SVC32 @@ -433,13 +434,13 @@ static void test_arm_not_allow_privilege_escalation() UC_ERR_EXCEPTION, uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); - OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp)); OK(uc_reg_read(uc, UC_ARM_REG_LR, &r_lr)); + OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); - OK((r_cpsr & ((1 << 4) - 1)) == 0); // Stay in USR32 - OK(r_lr == 0x1234); - OK(r_sp == 0x10000); + TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 0); // Stay in USR32 + TEST_CHECK(r_lr == 0x1234); + TEST_CHECK(r_sp == 0x10000); OK(uc_close(uc)); } From 47097b55b79492c75f27ffb85f93aea2a3191dd7 Mon Sep 17 00:00:00 2001 From: lazymio Date: Tue, 4 Jan 2022 21:01:20 +0100 Subject: [PATCH 04/18] Fix #1520 --- qemu/target/arm/cpu.h | 1 + qemu/target/arm/helper.c | 9 ++++++--- qemu/target/arm/unicorn_arm.c | 6 +++--- 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index 2e734a62..3ddb1da6 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -1264,6 +1264,7 @@ typedef enum CPSRWriteType { CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ CPSRWriteByGDBStub = 3, /* from the GDB stub */ + CPSRWriteByUnicorn = 4 /* from uc_reg_write */ } CPSRWriteType; /* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 48c9b013..0ee137f9 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -7983,9 +7983,12 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, * to switch mode. (Those are caught by translate.c for writes * triggered by guest instructions.) */ - // mask &= ~CPSR_M; - // Unicorn: No, it can also be uc_reg_write - switch_mode(env, val & CPSR_M); + mask &= ~CPSR_M; + + // Unicorn: No, it can also be uc_reg_write, let user switch registers banks. + if (write_type == CPSRWriteByUnicorn) { + switch_mode(env, val & CPSR_M); + } } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in * v7, and has defined behaviour in v8: diff --git a/qemu/target/arm/unicorn_arm.c b/qemu/target/arm/unicorn_arm.c index 95bd93b5..f98a61bb 100644 --- a/qemu/target/arm/unicorn_arm.c +++ b/qemu/target/arm/unicorn_arm.c @@ -251,17 +251,17 @@ static void reg_write(CPUARMState *env, unsigned int regid, const void *value) case UC_ARM_REG_APSR: if (!arm_feature(env, ARM_FEATURE_M)) { cpsr_write(env, *(uint32_t *)value, - (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteByInstr); + (CPSR_NZCV | CPSR_Q | CPSR_GE), CPSRWriteByUnicorn); } else { // Same with UC_ARM_REG_APSR_NZCVQ v7m_msr_xpsr(env, 0b1000, 0, *(uint32_t *)value); } break; case UC_ARM_REG_APSR_NZCV: - cpsr_write(env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteByInstr); + cpsr_write(env, *(uint32_t *)value, CPSR_NZCV, CPSRWriteByUnicorn); break; case UC_ARM_REG_CPSR: - cpsr_write(env, *(uint32_t *)value, ~0, CPSRWriteByInstr); + cpsr_write(env, *(uint32_t *)value, ~0, CPSRWriteByUnicorn); break; case UC_ARM_REG_SPSR: env->spsr = *(uint32_t *)value; From d854e22301a3250d425100ac114e526b838a01ca Mon Sep 17 00:00:00 2001 From: lazymio Date: Tue, 4 Jan 2022 21:12:12 +0100 Subject: [PATCH 05/18] Add x87 FPU registers #1524 --- include/unicorn/x86.h | 5 +++++ qemu/target/i386/unicorn.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h index a4afcd9c..861844f8 100644 --- a/include/unicorn/x86.h +++ b/include/unicorn/x86.h @@ -319,6 +319,11 @@ typedef enum uc_x86_reg { UC_X86_REG_GS_BASE, UC_X86_REG_FLAGS, UC_X86_REG_RFLAGS, + UC_X86_REG_FIP, + UC_X86_REG_FCS, + UC_X86_REG_FDP, + UC_X86_REG_FDS, + UC_X86_REG_FOP, UC_X86_REG_ENDING // <-- mark the end of the list of registers } uc_x86_reg; diff --git a/qemu/target/i386/unicorn.c b/qemu/target/i386/unicorn.c index d6d74d92..ded937fe 100644 --- a/qemu/target/i386/unicorn.c +++ b/qemu/target/i386/unicorn.c @@ -321,6 +321,22 @@ static void reg_read(CPUX86State *env, unsigned int regid, void *value, dst[3] = hi_reg->_d[1]; return; } + + case UC_X86_REG_FIP: + *(uint64_t *)value = env->fpip; + return; + case UC_X86_REG_FCS: + *(uint16_t *)value = env->fpcs; + return; + case UC_X86_REG_FDP: + *(uint64_t *)value = env->fpdp; + return; + case UC_X86_REG_FDS: + *(uint16_t *)value = env->fpds; + return; + case UC_X86_REG_FOP: + *(uint16_t *)value = env->fpop; + return; } switch (mode) { @@ -912,6 +928,22 @@ static int reg_write(CPUX86State *env, unsigned int regid, const void *value, hi_reg->_d[1] = src[3]; return 0; } + + case UC_X86_REG_FIP: + env->fpip = *(uint64_t *)value; + return 0; + case UC_X86_REG_FCS: + env->fpcs = *(uint16_t *)value; + return 0; + case UC_X86_REG_FDP: + env->fpdp = *(uint64_t *)value; + return 0; + case UC_X86_REG_FDS: + env->fpds = *(uint16_t *)value; + return 0; + case UC_X86_REG_FOP: + env->fpop = *(uint16_t *)value; + return 0; } switch (mode) { From c4b418985773bdb74b1cbcd78722d0e74cb7bcfa Mon Sep 17 00:00:00 2001 From: lazymio Date: Tue, 4 Jan 2022 21:12:52 +0100 Subject: [PATCH 06/18] Update bindings --- .../dotnet/UnicornManaged/Const/Common.fs | 6 +- bindings/dotnet/UnicornManaged/Const/M68k.fs | 18 +- bindings/dotnet/UnicornManaged/Const/Riscv.fs | 259 +++++++++++++----- bindings/dotnet/UnicornManaged/Const/X86.fs | 7 +- bindings/go/unicorn/m68k_const.go | 18 +- bindings/go/unicorn/riscv_const.go | 259 +++++++++++++----- bindings/go/unicorn/unicorn_const.go | 6 +- bindings/go/unicorn/x86_const.go | 7 +- bindings/java/unicorn/M68kConst.java | 18 +- bindings/java/unicorn/RiscvConst.java | 259 +++++++++++++----- bindings/java/unicorn/UnicornConst.java | 6 +- bindings/java/unicorn/X86Const.java | 7 +- bindings/pascal/unicorn/M68kConst.pas | 18 +- bindings/pascal/unicorn/RiscvConst.pas | 259 +++++++++++++----- bindings/pascal/unicorn/UnicornConst.pas | 6 +- bindings/pascal/unicorn/X86Const.pas | 7 +- bindings/python/unicorn/x86_const.py | 7 +- .../lib/unicorn_engine/m68k_const.rb | 18 +- .../lib/unicorn_engine/riscv_const.rb | 259 +++++++++++++----- .../lib/unicorn_engine/unicorn_const.rb | 6 +- .../lib/unicorn_engine/x86_const.rb | 7 +- 21 files changed, 1071 insertions(+), 386 deletions(-) diff --git a/bindings/dotnet/UnicornManaged/Const/Common.fs b/bindings/dotnet/UnicornManaged/Const/Common.fs index 0eebf1ec..b74b5286 100644 --- a/bindings/dotnet/UnicornManaged/Const/Common.fs +++ b/bindings/dotnet/UnicornManaged/Const/Common.fs @@ -9,11 +9,15 @@ module Common = let UC_API_MAJOR = 2 let UC_API_MINOR = 0 + + let UC_API_PATCH = 0 + let UC_API_EXTRA = 5 let UC_VERSION_MAJOR = 2 let UC_VERSION_MINOR = 0 - let UC_VERSION_EXTRA = 0 + let UC_VERSION_PATCH = 0 + let UC_VERSION_EXTRA = 5 let UC_SECOND_SCALE = 1000000 let UC_MILISECOND_SCALE = 1000 let UC_ARCH_ARM = 1 diff --git a/bindings/dotnet/UnicornManaged/Const/M68k.fs b/bindings/dotnet/UnicornManaged/Const/M68k.fs index 8d55516e..7639d240 100644 --- a/bindings/dotnet/UnicornManaged/Const/M68k.fs +++ b/bindings/dotnet/UnicornManaged/Const/M68k.fs @@ -9,15 +9,15 @@ module M68k = // M68K CPU - let UC_CPU_M5206_CPU = 0 - let UC_CPU_M68000_CPU = 1 - let UC_CPU_M68020_CPU = 2 - let UC_CPU_M68030_CPU = 3 - let UC_CPU_M68040_CPU = 4 - let UC_CPU_M68060_CPU = 5 - let UC_CPU_M5208_CPU = 6 - let UC_CPU_CFV4E_CPU = 7 - let UC_CPU_ANY_CPU = 8 + let UC_CPU_M68K_M5206 = 0 + let UC_CPU_M68K_M68000 = 1 + let UC_CPU_M68K_M68020 = 2 + let UC_CPU_M68K_M68030 = 3 + let UC_CPU_M68K_M68040 = 4 + let UC_CPU_M68K_M68060 = 5 + let UC_CPU_M68K_M5208 = 6 + let UC_CPU_M68K_CFV4E = 7 + let UC_CPU_M68K_ANY = 8 // M68K registers diff --git a/bindings/dotnet/UnicornManaged/Const/Riscv.fs b/bindings/dotnet/UnicornManaged/Const/Riscv.fs index fa765e73..4d141e85 100644 --- a/bindings/dotnet/UnicornManaged/Const/Riscv.fs +++ b/bindings/dotnet/UnicornManaged/Const/Riscv.fs @@ -59,41 +59,168 @@ module Riscv = let UC_RISCV_REG_X30 = 31 let UC_RISCV_REG_X31 = 32 + // RISCV CSR + let UC_RISCV_REG_USTATUS = 33 + let UC_RISCV_REG_UIE = 34 + let UC_RISCV_REG_UTVEC = 35 + let UC_RISCV_REG_USCRATCH = 36 + let UC_RISCV_REG_UEPC = 37 + let UC_RISCV_REG_UCAUSE = 38 + let UC_RISCV_REG_UTVAL = 39 + let UC_RISCV_REG_UIP = 40 + let UC_RISCV_REG_FFLAGS = 41 + let UC_RISCV_REG_FRM = 42 + let UC_RISCV_REG_FCSR = 43 + let UC_RISCV_REG_CYCLE = 44 + let UC_RISCV_REG_TIME = 45 + let UC_RISCV_REG_INSTRET = 46 + let UC_RISCV_REG_HPMCOUNTER3 = 47 + let UC_RISCV_REG_HPMCOUNTER4 = 48 + let UC_RISCV_REG_HPMCOUNTER5 = 49 + let UC_RISCV_REG_HPMCOUNTER6 = 50 + let UC_RISCV_REG_HPMCOUNTER7 = 51 + let UC_RISCV_REG_HPMCOUNTER8 = 52 + let UC_RISCV_REG_HPMCOUNTER9 = 53 + let UC_RISCV_REG_HPMCOUNTER10 = 54 + let UC_RISCV_REG_HPMCOUNTER11 = 55 + let UC_RISCV_REG_HPMCOUNTER12 = 56 + let UC_RISCV_REG_HPMCOUNTER13 = 57 + let UC_RISCV_REG_HPMCOUNTER14 = 58 + let UC_RISCV_REG_HPMCOUNTER15 = 59 + let UC_RISCV_REG_HPMCOUNTER16 = 60 + let UC_RISCV_REG_HPMCOUNTER17 = 61 + let UC_RISCV_REG_HPMCOUNTER18 = 62 + let UC_RISCV_REG_HPMCOUNTER19 = 63 + let UC_RISCV_REG_HPMCOUNTER20 = 64 + let UC_RISCV_REG_HPMCOUNTER21 = 65 + let UC_RISCV_REG_HPMCOUNTER22 = 66 + let UC_RISCV_REG_HPMCOUNTER23 = 67 + let UC_RISCV_REG_HPMCOUNTER24 = 68 + let UC_RISCV_REG_HPMCOUNTER25 = 69 + let UC_RISCV_REG_HPMCOUNTER26 = 70 + let UC_RISCV_REG_HPMCOUNTER27 = 71 + let UC_RISCV_REG_HPMCOUNTER28 = 72 + let UC_RISCV_REG_HPMCOUNTER29 = 73 + let UC_RISCV_REG_HPMCOUNTER30 = 74 + let UC_RISCV_REG_HPMCOUNTER31 = 75 + let UC_RISCV_REG_CYCLEH = 76 + let UC_RISCV_REG_TIMEH = 77 + let UC_RISCV_REG_INSTRETH = 78 + let UC_RISCV_REG_HPMCOUNTER3H = 79 + let UC_RISCV_REG_HPMCOUNTER4H = 80 + let UC_RISCV_REG_HPMCOUNTER5H = 81 + let UC_RISCV_REG_HPMCOUNTER6H = 82 + let UC_RISCV_REG_HPMCOUNTER7H = 83 + let UC_RISCV_REG_HPMCOUNTER8H = 84 + let UC_RISCV_REG_HPMCOUNTER9H = 85 + let UC_RISCV_REG_HPMCOUNTER10H = 86 + let UC_RISCV_REG_HPMCOUNTER11H = 87 + let UC_RISCV_REG_HPMCOUNTER12H = 88 + let UC_RISCV_REG_HPMCOUNTER13H = 89 + let UC_RISCV_REG_HPMCOUNTER14H = 90 + let UC_RISCV_REG_HPMCOUNTER15H = 91 + let UC_RISCV_REG_HPMCOUNTER16H = 92 + let UC_RISCV_REG_HPMCOUNTER17H = 93 + let UC_RISCV_REG_HPMCOUNTER18H = 94 + let UC_RISCV_REG_HPMCOUNTER19H = 95 + let UC_RISCV_REG_HPMCOUNTER20H = 96 + let UC_RISCV_REG_HPMCOUNTER21H = 97 + let UC_RISCV_REG_HPMCOUNTER22H = 98 + let UC_RISCV_REG_HPMCOUNTER23H = 99 + let UC_RISCV_REG_HPMCOUNTER24H = 100 + let UC_RISCV_REG_HPMCOUNTER25H = 101 + let UC_RISCV_REG_HPMCOUNTER26H = 102 + let UC_RISCV_REG_HPMCOUNTER27H = 103 + let UC_RISCV_REG_HPMCOUNTER28H = 104 + let UC_RISCV_REG_HPMCOUNTER29H = 105 + let UC_RISCV_REG_HPMCOUNTER30H = 106 + let UC_RISCV_REG_HPMCOUNTER31H = 107 + let UC_RISCV_REG_MCYCLE = 108 + let UC_RISCV_REG_MINSTRET = 109 + let UC_RISCV_REG_MCYCLEH = 110 + let UC_RISCV_REG_MINSTRETH = 111 + let UC_RISCV_REG_MVENDORID = 112 + let UC_RISCV_REG_MARCHID = 113 + let UC_RISCV_REG_MIMPID = 114 + let UC_RISCV_REG_MHARTID = 115 + let UC_RISCV_REG_MSTATUS = 116 + let UC_RISCV_REG_MISA = 117 + let UC_RISCV_REG_MEDELEG = 118 + let UC_RISCV_REG_MIDELEG = 119 + let UC_RISCV_REG_MIE = 120 + let UC_RISCV_REG_MTVEC = 121 + let UC_RISCV_REG_MCOUNTEREN = 122 + let UC_RISCV_REG_MSTATUSH = 123 + let UC_RISCV_REG_MUCOUNTEREN = 124 + let UC_RISCV_REG_MSCOUNTEREN = 125 + let UC_RISCV_REG_MHCOUNTEREN = 126 + let UC_RISCV_REG_MSCRATCH = 127 + let UC_RISCV_REG_MEPC = 128 + let UC_RISCV_REG_MCAUSE = 129 + let UC_RISCV_REG_MTVAL = 130 + let UC_RISCV_REG_MIP = 131 + let UC_RISCV_REG_MBADADDR = 132 + let UC_RISCV_REG_SSTATUS = 133 + let UC_RISCV_REG_SEDELEG = 134 + let UC_RISCV_REG_SIDELEG = 135 + let UC_RISCV_REG_SIE = 136 + let UC_RISCV_REG_STVEC = 137 + let UC_RISCV_REG_SCOUNTEREN = 138 + let UC_RISCV_REG_SSCRATCH = 139 + let UC_RISCV_REG_SEPC = 140 + let UC_RISCV_REG_SCAUSE = 141 + let UC_RISCV_REG_STVAL = 142 + let UC_RISCV_REG_SIP = 143 + let UC_RISCV_REG_SBADADDR = 144 + let UC_RISCV_REG_SPTBR = 145 + let UC_RISCV_REG_SATP = 146 + let UC_RISCV_REG_HSTATUS = 147 + let UC_RISCV_REG_HEDELEG = 148 + let UC_RISCV_REG_HIDELEG = 149 + let UC_RISCV_REG_HIE = 150 + let UC_RISCV_REG_HCOUNTEREN = 151 + let UC_RISCV_REG_HTVAL = 152 + let UC_RISCV_REG_HIP = 153 + let UC_RISCV_REG_HTINST = 154 + let UC_RISCV_REG_HGATP = 155 + let UC_RISCV_REG_HTIMEDELTA = 156 + let UC_RISCV_REG_HTIMEDELTAH = 157 + // Floating-point registers - let UC_RISCV_REG_F0 = 33 - let UC_RISCV_REG_F1 = 34 - let UC_RISCV_REG_F2 = 35 - let UC_RISCV_REG_F3 = 36 - let UC_RISCV_REG_F4 = 37 - let UC_RISCV_REG_F5 = 38 - let UC_RISCV_REG_F6 = 39 - let UC_RISCV_REG_F7 = 40 - let UC_RISCV_REG_F8 = 41 - let UC_RISCV_REG_F9 = 42 - let UC_RISCV_REG_F10 = 43 - let UC_RISCV_REG_F11 = 44 - let UC_RISCV_REG_F12 = 45 - let UC_RISCV_REG_F13 = 46 - let UC_RISCV_REG_F14 = 47 - let UC_RISCV_REG_F15 = 48 - let UC_RISCV_REG_F16 = 49 - let UC_RISCV_REG_F17 = 50 - let UC_RISCV_REG_F18 = 51 - let UC_RISCV_REG_F19 = 52 - let UC_RISCV_REG_F20 = 53 - let UC_RISCV_REG_F21 = 54 - let UC_RISCV_REG_F22 = 55 - let UC_RISCV_REG_F23 = 56 - let UC_RISCV_REG_F24 = 57 - let UC_RISCV_REG_F25 = 58 - let UC_RISCV_REG_F26 = 59 - let UC_RISCV_REG_F27 = 60 - let UC_RISCV_REG_F28 = 61 - let UC_RISCV_REG_F29 = 62 - let UC_RISCV_REG_F30 = 63 - let UC_RISCV_REG_F31 = 64 - let UC_RISCV_REG_PC = 65 - let UC_RISCV_REG_ENDING = 66 + let UC_RISCV_REG_F0 = 158 + let UC_RISCV_REG_F1 = 159 + let UC_RISCV_REG_F2 = 160 + let UC_RISCV_REG_F3 = 161 + let UC_RISCV_REG_F4 = 162 + let UC_RISCV_REG_F5 = 163 + let UC_RISCV_REG_F6 = 164 + let UC_RISCV_REG_F7 = 165 + let UC_RISCV_REG_F8 = 166 + let UC_RISCV_REG_F9 = 167 + let UC_RISCV_REG_F10 = 168 + let UC_RISCV_REG_F11 = 169 + let UC_RISCV_REG_F12 = 170 + let UC_RISCV_REG_F13 = 171 + let UC_RISCV_REG_F14 = 172 + let UC_RISCV_REG_F15 = 173 + let UC_RISCV_REG_F16 = 174 + let UC_RISCV_REG_F17 = 175 + let UC_RISCV_REG_F18 = 176 + let UC_RISCV_REG_F19 = 177 + let UC_RISCV_REG_F20 = 178 + let UC_RISCV_REG_F21 = 179 + let UC_RISCV_REG_F22 = 180 + let UC_RISCV_REG_F23 = 181 + let UC_RISCV_REG_F24 = 182 + let UC_RISCV_REG_F25 = 183 + let UC_RISCV_REG_F26 = 184 + let UC_RISCV_REG_F27 = 185 + let UC_RISCV_REG_F28 = 186 + let UC_RISCV_REG_F29 = 187 + let UC_RISCV_REG_F30 = 188 + let UC_RISCV_REG_F31 = 189 + let UC_RISCV_REG_PC = 190 + let UC_RISCV_REG_ENDING = 191 // Alias registers let UC_RISCV_REG_ZERO = 1 @@ -129,36 +256,36 @@ module Riscv = let UC_RISCV_REG_T4 = 30 let UC_RISCV_REG_T5 = 31 let UC_RISCV_REG_T6 = 32 - let UC_RISCV_REG_FT0 = 33 - let UC_RISCV_REG_FT1 = 34 - let UC_RISCV_REG_FT2 = 35 - let UC_RISCV_REG_FT3 = 36 - let UC_RISCV_REG_FT4 = 37 - let UC_RISCV_REG_FT5 = 38 - let UC_RISCV_REG_FT6 = 39 - let UC_RISCV_REG_FT7 = 40 - let UC_RISCV_REG_FS0 = 41 - let UC_RISCV_REG_FS1 = 42 - let UC_RISCV_REG_FA0 = 43 - let UC_RISCV_REG_FA1 = 44 - let UC_RISCV_REG_FA2 = 45 - let UC_RISCV_REG_FA3 = 46 - let UC_RISCV_REG_FA4 = 47 - let UC_RISCV_REG_FA5 = 48 - let UC_RISCV_REG_FA6 = 49 - let UC_RISCV_REG_FA7 = 50 - let UC_RISCV_REG_FS2 = 51 - let UC_RISCV_REG_FS3 = 52 - let UC_RISCV_REG_FS4 = 53 - let UC_RISCV_REG_FS5 = 54 - let UC_RISCV_REG_FS6 = 55 - let UC_RISCV_REG_FS7 = 56 - let UC_RISCV_REG_FS8 = 57 - let UC_RISCV_REG_FS9 = 58 - let UC_RISCV_REG_FS10 = 59 - let UC_RISCV_REG_FS11 = 60 - let UC_RISCV_REG_FT8 = 61 - let UC_RISCV_REG_FT9 = 62 - let UC_RISCV_REG_FT10 = 63 - let UC_RISCV_REG_FT11 = 64 + let UC_RISCV_REG_FT0 = 158 + let UC_RISCV_REG_FT1 = 159 + let UC_RISCV_REG_FT2 = 160 + let UC_RISCV_REG_FT3 = 161 + let UC_RISCV_REG_FT4 = 162 + let UC_RISCV_REG_FT5 = 163 + let UC_RISCV_REG_FT6 = 164 + let UC_RISCV_REG_FT7 = 165 + let UC_RISCV_REG_FS0 = 166 + let UC_RISCV_REG_FS1 = 167 + let UC_RISCV_REG_FA0 = 168 + let UC_RISCV_REG_FA1 = 169 + let UC_RISCV_REG_FA2 = 170 + let UC_RISCV_REG_FA3 = 171 + let UC_RISCV_REG_FA4 = 172 + let UC_RISCV_REG_FA5 = 173 + let UC_RISCV_REG_FA6 = 174 + let UC_RISCV_REG_FA7 = 175 + let UC_RISCV_REG_FS2 = 176 + let UC_RISCV_REG_FS3 = 177 + let UC_RISCV_REG_FS4 = 178 + let UC_RISCV_REG_FS5 = 179 + let UC_RISCV_REG_FS6 = 180 + let UC_RISCV_REG_FS7 = 181 + let UC_RISCV_REG_FS8 = 182 + let UC_RISCV_REG_FS9 = 183 + let UC_RISCV_REG_FS10 = 184 + let UC_RISCV_REG_FS11 = 185 + let UC_RISCV_REG_FT8 = 186 + let UC_RISCV_REG_FT9 = 187 + let UC_RISCV_REG_FT10 = 188 + let UC_RISCV_REG_FT11 = 189 diff --git a/bindings/dotnet/UnicornManaged/Const/X86.fs b/bindings/dotnet/UnicornManaged/Const/X86.fs index 81c727b2..10973a05 100644 --- a/bindings/dotnet/UnicornManaged/Const/X86.fs +++ b/bindings/dotnet/UnicornManaged/Const/X86.fs @@ -284,7 +284,12 @@ module X86 = let UC_X86_REG_GS_BASE = 231 let UC_X86_REG_FLAGS = 232 let UC_X86_REG_RFLAGS = 233 - let UC_X86_REG_ENDING = 234 + let UC_X86_REG_FIP = 234 + let UC_X86_REG_FCS = 235 + let UC_X86_REG_FDP = 236 + let UC_X86_REG_FDS = 237 + let UC_X86_REG_FOP = 238 + let UC_X86_REG_ENDING = 239 // X86 instructions diff --git a/bindings/go/unicorn/m68k_const.go b/bindings/go/unicorn/m68k_const.go index 9b91860b..cdc5019a 100644 --- a/bindings/go/unicorn/m68k_const.go +++ b/bindings/go/unicorn/m68k_const.go @@ -4,15 +4,15 @@ const ( // M68K CPU - CPU_M5206_CPU = 0 - CPU_M68000_CPU = 1 - CPU_M68020_CPU = 2 - CPU_M68030_CPU = 3 - CPU_M68040_CPU = 4 - CPU_M68060_CPU = 5 - CPU_M5208_CPU = 6 - CPU_CFV4E_CPU = 7 - CPU_ANY_CPU = 8 + CPU_M68K_M5206 = 0 + CPU_M68K_M68000 = 1 + CPU_M68K_M68020 = 2 + CPU_M68K_M68030 = 3 + CPU_M68K_M68040 = 4 + CPU_M68K_M68060 = 5 + CPU_M68K_M5208 = 6 + CPU_M68K_CFV4E = 7 + CPU_M68K_ANY = 8 // M68K registers diff --git a/bindings/go/unicorn/riscv_const.go b/bindings/go/unicorn/riscv_const.go index 70741ebc..42927d39 100644 --- a/bindings/go/unicorn/riscv_const.go +++ b/bindings/go/unicorn/riscv_const.go @@ -54,41 +54,168 @@ const ( RISCV_REG_X30 = 31 RISCV_REG_X31 = 32 +// RISCV CSR + RISCV_REG_USTATUS = 33 + RISCV_REG_UIE = 34 + RISCV_REG_UTVEC = 35 + RISCV_REG_USCRATCH = 36 + RISCV_REG_UEPC = 37 + RISCV_REG_UCAUSE = 38 + RISCV_REG_UTVAL = 39 + RISCV_REG_UIP = 40 + RISCV_REG_FFLAGS = 41 + RISCV_REG_FRM = 42 + RISCV_REG_FCSR = 43 + RISCV_REG_CYCLE = 44 + RISCV_REG_TIME = 45 + RISCV_REG_INSTRET = 46 + RISCV_REG_HPMCOUNTER3 = 47 + RISCV_REG_HPMCOUNTER4 = 48 + RISCV_REG_HPMCOUNTER5 = 49 + RISCV_REG_HPMCOUNTER6 = 50 + RISCV_REG_HPMCOUNTER7 = 51 + RISCV_REG_HPMCOUNTER8 = 52 + RISCV_REG_HPMCOUNTER9 = 53 + RISCV_REG_HPMCOUNTER10 = 54 + RISCV_REG_HPMCOUNTER11 = 55 + RISCV_REG_HPMCOUNTER12 = 56 + RISCV_REG_HPMCOUNTER13 = 57 + RISCV_REG_HPMCOUNTER14 = 58 + RISCV_REG_HPMCOUNTER15 = 59 + RISCV_REG_HPMCOUNTER16 = 60 + RISCV_REG_HPMCOUNTER17 = 61 + RISCV_REG_HPMCOUNTER18 = 62 + RISCV_REG_HPMCOUNTER19 = 63 + RISCV_REG_HPMCOUNTER20 = 64 + RISCV_REG_HPMCOUNTER21 = 65 + RISCV_REG_HPMCOUNTER22 = 66 + RISCV_REG_HPMCOUNTER23 = 67 + RISCV_REG_HPMCOUNTER24 = 68 + RISCV_REG_HPMCOUNTER25 = 69 + RISCV_REG_HPMCOUNTER26 = 70 + RISCV_REG_HPMCOUNTER27 = 71 + RISCV_REG_HPMCOUNTER28 = 72 + RISCV_REG_HPMCOUNTER29 = 73 + RISCV_REG_HPMCOUNTER30 = 74 + RISCV_REG_HPMCOUNTER31 = 75 + RISCV_REG_CYCLEH = 76 + RISCV_REG_TIMEH = 77 + RISCV_REG_INSTRETH = 78 + RISCV_REG_HPMCOUNTER3H = 79 + RISCV_REG_HPMCOUNTER4H = 80 + RISCV_REG_HPMCOUNTER5H = 81 + RISCV_REG_HPMCOUNTER6H = 82 + RISCV_REG_HPMCOUNTER7H = 83 + RISCV_REG_HPMCOUNTER8H = 84 + RISCV_REG_HPMCOUNTER9H = 85 + RISCV_REG_HPMCOUNTER10H = 86 + RISCV_REG_HPMCOUNTER11H = 87 + RISCV_REG_HPMCOUNTER12H = 88 + RISCV_REG_HPMCOUNTER13H = 89 + RISCV_REG_HPMCOUNTER14H = 90 + RISCV_REG_HPMCOUNTER15H = 91 + RISCV_REG_HPMCOUNTER16H = 92 + RISCV_REG_HPMCOUNTER17H = 93 + RISCV_REG_HPMCOUNTER18H = 94 + RISCV_REG_HPMCOUNTER19H = 95 + RISCV_REG_HPMCOUNTER20H = 96 + RISCV_REG_HPMCOUNTER21H = 97 + RISCV_REG_HPMCOUNTER22H = 98 + RISCV_REG_HPMCOUNTER23H = 99 + RISCV_REG_HPMCOUNTER24H = 100 + RISCV_REG_HPMCOUNTER25H = 101 + RISCV_REG_HPMCOUNTER26H = 102 + RISCV_REG_HPMCOUNTER27H = 103 + RISCV_REG_HPMCOUNTER28H = 104 + RISCV_REG_HPMCOUNTER29H = 105 + RISCV_REG_HPMCOUNTER30H = 106 + RISCV_REG_HPMCOUNTER31H = 107 + RISCV_REG_MCYCLE = 108 + RISCV_REG_MINSTRET = 109 + RISCV_REG_MCYCLEH = 110 + RISCV_REG_MINSTRETH = 111 + RISCV_REG_MVENDORID = 112 + RISCV_REG_MARCHID = 113 + RISCV_REG_MIMPID = 114 + RISCV_REG_MHARTID = 115 + RISCV_REG_MSTATUS = 116 + RISCV_REG_MISA = 117 + RISCV_REG_MEDELEG = 118 + RISCV_REG_MIDELEG = 119 + RISCV_REG_MIE = 120 + RISCV_REG_MTVEC = 121 + RISCV_REG_MCOUNTEREN = 122 + RISCV_REG_MSTATUSH = 123 + RISCV_REG_MUCOUNTEREN = 124 + RISCV_REG_MSCOUNTEREN = 125 + RISCV_REG_MHCOUNTEREN = 126 + RISCV_REG_MSCRATCH = 127 + RISCV_REG_MEPC = 128 + RISCV_REG_MCAUSE = 129 + RISCV_REG_MTVAL = 130 + RISCV_REG_MIP = 131 + RISCV_REG_MBADADDR = 132 + RISCV_REG_SSTATUS = 133 + RISCV_REG_SEDELEG = 134 + RISCV_REG_SIDELEG = 135 + RISCV_REG_SIE = 136 + RISCV_REG_STVEC = 137 + RISCV_REG_SCOUNTEREN = 138 + RISCV_REG_SSCRATCH = 139 + RISCV_REG_SEPC = 140 + RISCV_REG_SCAUSE = 141 + RISCV_REG_STVAL = 142 + RISCV_REG_SIP = 143 + RISCV_REG_SBADADDR = 144 + RISCV_REG_SPTBR = 145 + RISCV_REG_SATP = 146 + RISCV_REG_HSTATUS = 147 + RISCV_REG_HEDELEG = 148 + RISCV_REG_HIDELEG = 149 + RISCV_REG_HIE = 150 + RISCV_REG_HCOUNTEREN = 151 + RISCV_REG_HTVAL = 152 + RISCV_REG_HIP = 153 + RISCV_REG_HTINST = 154 + RISCV_REG_HGATP = 155 + RISCV_REG_HTIMEDELTA = 156 + RISCV_REG_HTIMEDELTAH = 157 + // Floating-point registers - RISCV_REG_F0 = 33 - RISCV_REG_F1 = 34 - RISCV_REG_F2 = 35 - RISCV_REG_F3 = 36 - RISCV_REG_F4 = 37 - RISCV_REG_F5 = 38 - RISCV_REG_F6 = 39 - RISCV_REG_F7 = 40 - RISCV_REG_F8 = 41 - RISCV_REG_F9 = 42 - RISCV_REG_F10 = 43 - RISCV_REG_F11 = 44 - RISCV_REG_F12 = 45 - RISCV_REG_F13 = 46 - RISCV_REG_F14 = 47 - RISCV_REG_F15 = 48 - RISCV_REG_F16 = 49 - RISCV_REG_F17 = 50 - RISCV_REG_F18 = 51 - RISCV_REG_F19 = 52 - RISCV_REG_F20 = 53 - RISCV_REG_F21 = 54 - RISCV_REG_F22 = 55 - RISCV_REG_F23 = 56 - RISCV_REG_F24 = 57 - RISCV_REG_F25 = 58 - RISCV_REG_F26 = 59 - RISCV_REG_F27 = 60 - RISCV_REG_F28 = 61 - RISCV_REG_F29 = 62 - RISCV_REG_F30 = 63 - RISCV_REG_F31 = 64 - RISCV_REG_PC = 65 - RISCV_REG_ENDING = 66 + RISCV_REG_F0 = 158 + RISCV_REG_F1 = 159 + RISCV_REG_F2 = 160 + RISCV_REG_F3 = 161 + RISCV_REG_F4 = 162 + RISCV_REG_F5 = 163 + RISCV_REG_F6 = 164 + RISCV_REG_F7 = 165 + RISCV_REG_F8 = 166 + RISCV_REG_F9 = 167 + RISCV_REG_F10 = 168 + RISCV_REG_F11 = 169 + RISCV_REG_F12 = 170 + RISCV_REG_F13 = 171 + RISCV_REG_F14 = 172 + RISCV_REG_F15 = 173 + RISCV_REG_F16 = 174 + RISCV_REG_F17 = 175 + RISCV_REG_F18 = 176 + RISCV_REG_F19 = 177 + RISCV_REG_F20 = 178 + RISCV_REG_F21 = 179 + RISCV_REG_F22 = 180 + RISCV_REG_F23 = 181 + RISCV_REG_F24 = 182 + RISCV_REG_F25 = 183 + RISCV_REG_F26 = 184 + RISCV_REG_F27 = 185 + RISCV_REG_F28 = 186 + RISCV_REG_F29 = 187 + RISCV_REG_F30 = 188 + RISCV_REG_F31 = 189 + RISCV_REG_PC = 190 + RISCV_REG_ENDING = 191 // Alias registers RISCV_REG_ZERO = 1 @@ -124,36 +251,36 @@ const ( RISCV_REG_T4 = 30 RISCV_REG_T5 = 31 RISCV_REG_T6 = 32 - RISCV_REG_FT0 = 33 - RISCV_REG_FT1 = 34 - RISCV_REG_FT2 = 35 - RISCV_REG_FT3 = 36 - RISCV_REG_FT4 = 37 - RISCV_REG_FT5 = 38 - RISCV_REG_FT6 = 39 - RISCV_REG_FT7 = 40 - RISCV_REG_FS0 = 41 - RISCV_REG_FS1 = 42 - RISCV_REG_FA0 = 43 - RISCV_REG_FA1 = 44 - RISCV_REG_FA2 = 45 - RISCV_REG_FA3 = 46 - RISCV_REG_FA4 = 47 - RISCV_REG_FA5 = 48 - RISCV_REG_FA6 = 49 - RISCV_REG_FA7 = 50 - RISCV_REG_FS2 = 51 - RISCV_REG_FS3 = 52 - RISCV_REG_FS4 = 53 - RISCV_REG_FS5 = 54 - RISCV_REG_FS6 = 55 - RISCV_REG_FS7 = 56 - RISCV_REG_FS8 = 57 - RISCV_REG_FS9 = 58 - RISCV_REG_FS10 = 59 - RISCV_REG_FS11 = 60 - RISCV_REG_FT8 = 61 - RISCV_REG_FT9 = 62 - RISCV_REG_FT10 = 63 - RISCV_REG_FT11 = 64 + RISCV_REG_FT0 = 158 + RISCV_REG_FT1 = 159 + RISCV_REG_FT2 = 160 + RISCV_REG_FT3 = 161 + RISCV_REG_FT4 = 162 + RISCV_REG_FT5 = 163 + RISCV_REG_FT6 = 164 + RISCV_REG_FT7 = 165 + RISCV_REG_FS0 = 166 + RISCV_REG_FS1 = 167 + RISCV_REG_FA0 = 168 + RISCV_REG_FA1 = 169 + RISCV_REG_FA2 = 170 + RISCV_REG_FA3 = 171 + RISCV_REG_FA4 = 172 + RISCV_REG_FA5 = 173 + RISCV_REG_FA6 = 174 + RISCV_REG_FA7 = 175 + RISCV_REG_FS2 = 176 + RISCV_REG_FS3 = 177 + RISCV_REG_FS4 = 178 + RISCV_REG_FS5 = 179 + RISCV_REG_FS6 = 180 + RISCV_REG_FS7 = 181 + RISCV_REG_FS8 = 182 + RISCV_REG_FS9 = 183 + RISCV_REG_FS10 = 184 + RISCV_REG_FS11 = 185 + RISCV_REG_FT8 = 186 + RISCV_REG_FT9 = 187 + RISCV_REG_FT10 = 188 + RISCV_REG_FT11 = 189 ) \ No newline at end of file diff --git a/bindings/go/unicorn/unicorn_const.go b/bindings/go/unicorn/unicorn_const.go index 0da008ae..2dd52c29 100644 --- a/bindings/go/unicorn/unicorn_const.go +++ b/bindings/go/unicorn/unicorn_const.go @@ -4,11 +4,15 @@ const ( API_MAJOR = 2 API_MINOR = 0 + + API_PATCH = 0 + API_EXTRA = 5 VERSION_MAJOR = 2 VERSION_MINOR = 0 - VERSION_EXTRA = 0 + VERSION_PATCH = 0 + VERSION_EXTRA = 5 SECOND_SCALE = 1000000 MILISECOND_SCALE = 1000 ARCH_ARM = 1 diff --git a/bindings/go/unicorn/x86_const.go b/bindings/go/unicorn/x86_const.go index 30157482..f7e97791 100644 --- a/bindings/go/unicorn/x86_const.go +++ b/bindings/go/unicorn/x86_const.go @@ -279,7 +279,12 @@ const ( X86_REG_GS_BASE = 231 X86_REG_FLAGS = 232 X86_REG_RFLAGS = 233 - X86_REG_ENDING = 234 + X86_REG_FIP = 234 + X86_REG_FCS = 235 + X86_REG_FDP = 236 + X86_REG_FDS = 237 + X86_REG_FOP = 238 + X86_REG_ENDING = 239 // X86 instructions diff --git a/bindings/java/unicorn/M68kConst.java b/bindings/java/unicorn/M68kConst.java index 1be8cd3f..e16210f3 100644 --- a/bindings/java/unicorn/M68kConst.java +++ b/bindings/java/unicorn/M68kConst.java @@ -6,15 +6,15 @@ public interface M68kConst { // M68K CPU - public static final int UC_CPU_M5206_CPU = 0; - public static final int UC_CPU_M68000_CPU = 1; - public static final int UC_CPU_M68020_CPU = 2; - public static final int UC_CPU_M68030_CPU = 3; - public static final int UC_CPU_M68040_CPU = 4; - public static final int UC_CPU_M68060_CPU = 5; - public static final int UC_CPU_M5208_CPU = 6; - public static final int UC_CPU_CFV4E_CPU = 7; - public static final int UC_CPU_ANY_CPU = 8; + public static final int UC_CPU_M68K_M5206 = 0; + public static final int UC_CPU_M68K_M68000 = 1; + public static final int UC_CPU_M68K_M68020 = 2; + public static final int UC_CPU_M68K_M68030 = 3; + public static final int UC_CPU_M68K_M68040 = 4; + public static final int UC_CPU_M68K_M68060 = 5; + public static final int UC_CPU_M68K_M5208 = 6; + public static final int UC_CPU_M68K_CFV4E = 7; + public static final int UC_CPU_M68K_ANY = 8; // M68K registers diff --git a/bindings/java/unicorn/RiscvConst.java b/bindings/java/unicorn/RiscvConst.java index 39f0b2b6..f56315de 100644 --- a/bindings/java/unicorn/RiscvConst.java +++ b/bindings/java/unicorn/RiscvConst.java @@ -56,41 +56,168 @@ public interface RiscvConst { public static final int UC_RISCV_REG_X30 = 31; public static final int UC_RISCV_REG_X31 = 32; +// RISCV CSR + public static final int UC_RISCV_REG_USTATUS = 33; + public static final int UC_RISCV_REG_UIE = 34; + public static final int UC_RISCV_REG_UTVEC = 35; + public static final int UC_RISCV_REG_USCRATCH = 36; + public static final int UC_RISCV_REG_UEPC = 37; + public static final int UC_RISCV_REG_UCAUSE = 38; + public static final int UC_RISCV_REG_UTVAL = 39; + public static final int UC_RISCV_REG_UIP = 40; + public static final int UC_RISCV_REG_FFLAGS = 41; + public static final int UC_RISCV_REG_FRM = 42; + public static final int UC_RISCV_REG_FCSR = 43; + public static final int UC_RISCV_REG_CYCLE = 44; + public static final int UC_RISCV_REG_TIME = 45; + public static final int UC_RISCV_REG_INSTRET = 46; + public static final int UC_RISCV_REG_HPMCOUNTER3 = 47; + public static final int UC_RISCV_REG_HPMCOUNTER4 = 48; + public static final int UC_RISCV_REG_HPMCOUNTER5 = 49; + public static final int UC_RISCV_REG_HPMCOUNTER6 = 50; + public static final int UC_RISCV_REG_HPMCOUNTER7 = 51; + public static final int UC_RISCV_REG_HPMCOUNTER8 = 52; + public static final int UC_RISCV_REG_HPMCOUNTER9 = 53; + public static final int UC_RISCV_REG_HPMCOUNTER10 = 54; + public static final int UC_RISCV_REG_HPMCOUNTER11 = 55; + public static final int UC_RISCV_REG_HPMCOUNTER12 = 56; + public static final int UC_RISCV_REG_HPMCOUNTER13 = 57; + public static final int UC_RISCV_REG_HPMCOUNTER14 = 58; + public static final int UC_RISCV_REG_HPMCOUNTER15 = 59; + public static final int UC_RISCV_REG_HPMCOUNTER16 = 60; + public static final int UC_RISCV_REG_HPMCOUNTER17 = 61; + public static final int UC_RISCV_REG_HPMCOUNTER18 = 62; + public static final int UC_RISCV_REG_HPMCOUNTER19 = 63; + public static final int UC_RISCV_REG_HPMCOUNTER20 = 64; + public static final int UC_RISCV_REG_HPMCOUNTER21 = 65; + public static final int UC_RISCV_REG_HPMCOUNTER22 = 66; + public static final int UC_RISCV_REG_HPMCOUNTER23 = 67; + public static final int UC_RISCV_REG_HPMCOUNTER24 = 68; + public static final int UC_RISCV_REG_HPMCOUNTER25 = 69; + public static final int UC_RISCV_REG_HPMCOUNTER26 = 70; + public static final int UC_RISCV_REG_HPMCOUNTER27 = 71; + public static final int UC_RISCV_REG_HPMCOUNTER28 = 72; + public static final int UC_RISCV_REG_HPMCOUNTER29 = 73; + public static final int UC_RISCV_REG_HPMCOUNTER30 = 74; + public static final int UC_RISCV_REG_HPMCOUNTER31 = 75; + public static final int UC_RISCV_REG_CYCLEH = 76; + public static final int UC_RISCV_REG_TIMEH = 77; + public static final int UC_RISCV_REG_INSTRETH = 78; + public static final int UC_RISCV_REG_HPMCOUNTER3H = 79; + public static final int UC_RISCV_REG_HPMCOUNTER4H = 80; + public static final int UC_RISCV_REG_HPMCOUNTER5H = 81; + public static final int UC_RISCV_REG_HPMCOUNTER6H = 82; + public static final int UC_RISCV_REG_HPMCOUNTER7H = 83; + public static final int UC_RISCV_REG_HPMCOUNTER8H = 84; + public static final int UC_RISCV_REG_HPMCOUNTER9H = 85; + public static final int UC_RISCV_REG_HPMCOUNTER10H = 86; + public static final int UC_RISCV_REG_HPMCOUNTER11H = 87; + public static final int UC_RISCV_REG_HPMCOUNTER12H = 88; + public static final int UC_RISCV_REG_HPMCOUNTER13H = 89; + public static final int UC_RISCV_REG_HPMCOUNTER14H = 90; + public static final int UC_RISCV_REG_HPMCOUNTER15H = 91; + public static final int UC_RISCV_REG_HPMCOUNTER16H = 92; + public static final int UC_RISCV_REG_HPMCOUNTER17H = 93; + public static final int UC_RISCV_REG_HPMCOUNTER18H = 94; + public static final int UC_RISCV_REG_HPMCOUNTER19H = 95; + public static final int UC_RISCV_REG_HPMCOUNTER20H = 96; + public static final int UC_RISCV_REG_HPMCOUNTER21H = 97; + public static final int UC_RISCV_REG_HPMCOUNTER22H = 98; + public static final int UC_RISCV_REG_HPMCOUNTER23H = 99; + public static final int UC_RISCV_REG_HPMCOUNTER24H = 100; + public static final int UC_RISCV_REG_HPMCOUNTER25H = 101; + public static final int UC_RISCV_REG_HPMCOUNTER26H = 102; + public static final int UC_RISCV_REG_HPMCOUNTER27H = 103; + public static final int UC_RISCV_REG_HPMCOUNTER28H = 104; + public static final int UC_RISCV_REG_HPMCOUNTER29H = 105; + public static final int UC_RISCV_REG_HPMCOUNTER30H = 106; + public static final int UC_RISCV_REG_HPMCOUNTER31H = 107; + public static final int UC_RISCV_REG_MCYCLE = 108; + public static final int UC_RISCV_REG_MINSTRET = 109; + public static final int UC_RISCV_REG_MCYCLEH = 110; + public static final int UC_RISCV_REG_MINSTRETH = 111; + public static final int UC_RISCV_REG_MVENDORID = 112; + public static final int UC_RISCV_REG_MARCHID = 113; + public static final int UC_RISCV_REG_MIMPID = 114; + public static final int UC_RISCV_REG_MHARTID = 115; + public static final int UC_RISCV_REG_MSTATUS = 116; + public static final int UC_RISCV_REG_MISA = 117; + public static final int UC_RISCV_REG_MEDELEG = 118; + public static final int UC_RISCV_REG_MIDELEG = 119; + public static final int UC_RISCV_REG_MIE = 120; + public static final int UC_RISCV_REG_MTVEC = 121; + public static final int UC_RISCV_REG_MCOUNTEREN = 122; + public static final int UC_RISCV_REG_MSTATUSH = 123; + public static final int UC_RISCV_REG_MUCOUNTEREN = 124; + public static final int UC_RISCV_REG_MSCOUNTEREN = 125; + public static final int UC_RISCV_REG_MHCOUNTEREN = 126; + public static final int UC_RISCV_REG_MSCRATCH = 127; + public static final int UC_RISCV_REG_MEPC = 128; + public static final int UC_RISCV_REG_MCAUSE = 129; + public static final int UC_RISCV_REG_MTVAL = 130; + public static final int UC_RISCV_REG_MIP = 131; + public static final int UC_RISCV_REG_MBADADDR = 132; + public static final int UC_RISCV_REG_SSTATUS = 133; + public static final int UC_RISCV_REG_SEDELEG = 134; + public static final int UC_RISCV_REG_SIDELEG = 135; + public static final int UC_RISCV_REG_SIE = 136; + public static final int UC_RISCV_REG_STVEC = 137; + public static final int UC_RISCV_REG_SCOUNTEREN = 138; + public static final int UC_RISCV_REG_SSCRATCH = 139; + public static final int UC_RISCV_REG_SEPC = 140; + public static final int UC_RISCV_REG_SCAUSE = 141; + public static final int UC_RISCV_REG_STVAL = 142; + public static final int UC_RISCV_REG_SIP = 143; + public static final int UC_RISCV_REG_SBADADDR = 144; + public static final int UC_RISCV_REG_SPTBR = 145; + public static final int UC_RISCV_REG_SATP = 146; + public static final int UC_RISCV_REG_HSTATUS = 147; + public static final int UC_RISCV_REG_HEDELEG = 148; + public static final int UC_RISCV_REG_HIDELEG = 149; + public static final int UC_RISCV_REG_HIE = 150; + public static final int UC_RISCV_REG_HCOUNTEREN = 151; + public static final int UC_RISCV_REG_HTVAL = 152; + public static final int UC_RISCV_REG_HIP = 153; + public static final int UC_RISCV_REG_HTINST = 154; + public static final int UC_RISCV_REG_HGATP = 155; + public static final int UC_RISCV_REG_HTIMEDELTA = 156; + public static final int UC_RISCV_REG_HTIMEDELTAH = 157; + // Floating-point registers - public static final int UC_RISCV_REG_F0 = 33; - public static final int UC_RISCV_REG_F1 = 34; - public static final int UC_RISCV_REG_F2 = 35; - public static final int UC_RISCV_REG_F3 = 36; - public static final int UC_RISCV_REG_F4 = 37; - public static final int UC_RISCV_REG_F5 = 38; - public static final int UC_RISCV_REG_F6 = 39; - public static final int UC_RISCV_REG_F7 = 40; - public static final int UC_RISCV_REG_F8 = 41; - public static final int UC_RISCV_REG_F9 = 42; - public static final int UC_RISCV_REG_F10 = 43; - public static final int UC_RISCV_REG_F11 = 44; - public static final int UC_RISCV_REG_F12 = 45; - public static final int UC_RISCV_REG_F13 = 46; - public static final int UC_RISCV_REG_F14 = 47; - public static final int UC_RISCV_REG_F15 = 48; - public static final int UC_RISCV_REG_F16 = 49; - public static final int UC_RISCV_REG_F17 = 50; - public static final int UC_RISCV_REG_F18 = 51; - public static final int UC_RISCV_REG_F19 = 52; - public static final int UC_RISCV_REG_F20 = 53; - public static final int UC_RISCV_REG_F21 = 54; - public static final int UC_RISCV_REG_F22 = 55; - public static final int UC_RISCV_REG_F23 = 56; - public static final int UC_RISCV_REG_F24 = 57; - public static final int UC_RISCV_REG_F25 = 58; - public static final int UC_RISCV_REG_F26 = 59; - public static final int UC_RISCV_REG_F27 = 60; - public static final int UC_RISCV_REG_F28 = 61; - public static final int UC_RISCV_REG_F29 = 62; - public static final int UC_RISCV_REG_F30 = 63; - public static final int UC_RISCV_REG_F31 = 64; - public static final int UC_RISCV_REG_PC = 65; - public static final int UC_RISCV_REG_ENDING = 66; + public static final int UC_RISCV_REG_F0 = 158; + public static final int UC_RISCV_REG_F1 = 159; + public static final int UC_RISCV_REG_F2 = 160; + public static final int UC_RISCV_REG_F3 = 161; + public static final int UC_RISCV_REG_F4 = 162; + public static final int UC_RISCV_REG_F5 = 163; + public static final int UC_RISCV_REG_F6 = 164; + public static final int UC_RISCV_REG_F7 = 165; + public static final int UC_RISCV_REG_F8 = 166; + public static final int UC_RISCV_REG_F9 = 167; + public static final int UC_RISCV_REG_F10 = 168; + public static final int UC_RISCV_REG_F11 = 169; + public static final int UC_RISCV_REG_F12 = 170; + public static final int UC_RISCV_REG_F13 = 171; + public static final int UC_RISCV_REG_F14 = 172; + public static final int UC_RISCV_REG_F15 = 173; + public static final int UC_RISCV_REG_F16 = 174; + public static final int UC_RISCV_REG_F17 = 175; + public static final int UC_RISCV_REG_F18 = 176; + public static final int UC_RISCV_REG_F19 = 177; + public static final int UC_RISCV_REG_F20 = 178; + public static final int UC_RISCV_REG_F21 = 179; + public static final int UC_RISCV_REG_F22 = 180; + public static final int UC_RISCV_REG_F23 = 181; + public static final int UC_RISCV_REG_F24 = 182; + public static final int UC_RISCV_REG_F25 = 183; + public static final int UC_RISCV_REG_F26 = 184; + public static final int UC_RISCV_REG_F27 = 185; + public static final int UC_RISCV_REG_F28 = 186; + public static final int UC_RISCV_REG_F29 = 187; + public static final int UC_RISCV_REG_F30 = 188; + public static final int UC_RISCV_REG_F31 = 189; + public static final int UC_RISCV_REG_PC = 190; + public static final int UC_RISCV_REG_ENDING = 191; // Alias registers public static final int UC_RISCV_REG_ZERO = 1; @@ -126,37 +253,37 @@ public interface RiscvConst { public static final int UC_RISCV_REG_T4 = 30; public static final int UC_RISCV_REG_T5 = 31; public static final int UC_RISCV_REG_T6 = 32; - public static final int UC_RISCV_REG_FT0 = 33; - public static final int UC_RISCV_REG_FT1 = 34; - public static final int UC_RISCV_REG_FT2 = 35; - public static final int UC_RISCV_REG_FT3 = 36; - public static final int UC_RISCV_REG_FT4 = 37; - public static final int UC_RISCV_REG_FT5 = 38; - public static final int UC_RISCV_REG_FT6 = 39; - public static final int UC_RISCV_REG_FT7 = 40; - public static final int UC_RISCV_REG_FS0 = 41; - public static final int UC_RISCV_REG_FS1 = 42; - public static final int UC_RISCV_REG_FA0 = 43; - public static final int UC_RISCV_REG_FA1 = 44; - public static final int UC_RISCV_REG_FA2 = 45; - public static final int UC_RISCV_REG_FA3 = 46; - public static final int UC_RISCV_REG_FA4 = 47; - public static final int UC_RISCV_REG_FA5 = 48; - public static final int UC_RISCV_REG_FA6 = 49; - public static final int UC_RISCV_REG_FA7 = 50; - public static final int UC_RISCV_REG_FS2 = 51; - public static final int UC_RISCV_REG_FS3 = 52; - public static final int UC_RISCV_REG_FS4 = 53; - public static final int UC_RISCV_REG_FS5 = 54; - public static final int UC_RISCV_REG_FS6 = 55; - public static final int UC_RISCV_REG_FS7 = 56; - public static final int UC_RISCV_REG_FS8 = 57; - public static final int UC_RISCV_REG_FS9 = 58; - public static final int UC_RISCV_REG_FS10 = 59; - public static final int UC_RISCV_REG_FS11 = 60; - public static final int UC_RISCV_REG_FT8 = 61; - public static final int UC_RISCV_REG_FT9 = 62; - public static final int UC_RISCV_REG_FT10 = 63; - public static final int UC_RISCV_REG_FT11 = 64; + public static final int UC_RISCV_REG_FT0 = 158; + public static final int UC_RISCV_REG_FT1 = 159; + public static final int UC_RISCV_REG_FT2 = 160; + public static final int UC_RISCV_REG_FT3 = 161; + public static final int UC_RISCV_REG_FT4 = 162; + public static final int UC_RISCV_REG_FT5 = 163; + public static final int UC_RISCV_REG_FT6 = 164; + public static final int UC_RISCV_REG_FT7 = 165; + public static final int UC_RISCV_REG_FS0 = 166; + public static final int UC_RISCV_REG_FS1 = 167; + public static final int UC_RISCV_REG_FA0 = 168; + public static final int UC_RISCV_REG_FA1 = 169; + public static final int UC_RISCV_REG_FA2 = 170; + public static final int UC_RISCV_REG_FA3 = 171; + public static final int UC_RISCV_REG_FA4 = 172; + public static final int UC_RISCV_REG_FA5 = 173; + public static final int UC_RISCV_REG_FA6 = 174; + public static final int UC_RISCV_REG_FA7 = 175; + public static final int UC_RISCV_REG_FS2 = 176; + public static final int UC_RISCV_REG_FS3 = 177; + public static final int UC_RISCV_REG_FS4 = 178; + public static final int UC_RISCV_REG_FS5 = 179; + public static final int UC_RISCV_REG_FS6 = 180; + public static final int UC_RISCV_REG_FS7 = 181; + public static final int UC_RISCV_REG_FS8 = 182; + public static final int UC_RISCV_REG_FS9 = 183; + public static final int UC_RISCV_REG_FS10 = 184; + public static final int UC_RISCV_REG_FS11 = 185; + public static final int UC_RISCV_REG_FT8 = 186; + public static final int UC_RISCV_REG_FT9 = 187; + public static final int UC_RISCV_REG_FT10 = 188; + public static final int UC_RISCV_REG_FT11 = 189; } diff --git a/bindings/java/unicorn/UnicornConst.java b/bindings/java/unicorn/UnicornConst.java index 73cc4bff..0c535c28 100644 --- a/bindings/java/unicorn/UnicornConst.java +++ b/bindings/java/unicorn/UnicornConst.java @@ -6,11 +6,15 @@ public interface UnicornConst { public static final int UC_API_MAJOR = 2; public static final int UC_API_MINOR = 0; + + public static final int UC_API_PATCH = 0; + public static final int UC_API_EXTRA = 5; public static final int UC_VERSION_MAJOR = 2; public static final int UC_VERSION_MINOR = 0; - public static final int UC_VERSION_EXTRA = 0; + public static final int UC_VERSION_PATCH = 0; + public static final int UC_VERSION_EXTRA = 5; public static final int UC_SECOND_SCALE = 1000000; public static final int UC_MILISECOND_SCALE = 1000; public static final int UC_ARCH_ARM = 1; diff --git a/bindings/java/unicorn/X86Const.java b/bindings/java/unicorn/X86Const.java index a614b06f..b64147b0 100644 --- a/bindings/java/unicorn/X86Const.java +++ b/bindings/java/unicorn/X86Const.java @@ -281,7 +281,12 @@ public interface X86Const { public static final int UC_X86_REG_GS_BASE = 231; public static final int UC_X86_REG_FLAGS = 232; public static final int UC_X86_REG_RFLAGS = 233; - public static final int UC_X86_REG_ENDING = 234; + public static final int UC_X86_REG_FIP = 234; + public static final int UC_X86_REG_FCS = 235; + public static final int UC_X86_REG_FDP = 236; + public static final int UC_X86_REG_FDS = 237; + public static final int UC_X86_REG_FOP = 238; + public static final int UC_X86_REG_ENDING = 239; // X86 instructions diff --git a/bindings/pascal/unicorn/M68kConst.pas b/bindings/pascal/unicorn/M68kConst.pas index 072ed476..587ee15a 100644 --- a/bindings/pascal/unicorn/M68kConst.pas +++ b/bindings/pascal/unicorn/M68kConst.pas @@ -7,15 +7,15 @@ interface const // M68K CPU - UC_CPU_M5206_CPU = 0; - UC_CPU_M68000_CPU = 1; - UC_CPU_M68020_CPU = 2; - UC_CPU_M68030_CPU = 3; - UC_CPU_M68040_CPU = 4; - UC_CPU_M68060_CPU = 5; - UC_CPU_M5208_CPU = 6; - UC_CPU_CFV4E_CPU = 7; - UC_CPU_ANY_CPU = 8; + UC_CPU_M68K_M5206 = 0; + UC_CPU_M68K_M68000 = 1; + UC_CPU_M68K_M68020 = 2; + UC_CPU_M68K_M68030 = 3; + UC_CPU_M68K_M68040 = 4; + UC_CPU_M68K_M68060 = 5; + UC_CPU_M68K_M5208 = 6; + UC_CPU_M68K_CFV4E = 7; + UC_CPU_M68K_ANY = 8; // M68K registers diff --git a/bindings/pascal/unicorn/RiscvConst.pas b/bindings/pascal/unicorn/RiscvConst.pas index 7420f59f..39dcb405 100644 --- a/bindings/pascal/unicorn/RiscvConst.pas +++ b/bindings/pascal/unicorn/RiscvConst.pas @@ -57,41 +57,168 @@ const UC_RISCV_REG_X30 = 31; UC_RISCV_REG_X31 = 32; +// RISCV CSR + UC_RISCV_REG_USTATUS = 33; + UC_RISCV_REG_UIE = 34; + UC_RISCV_REG_UTVEC = 35; + UC_RISCV_REG_USCRATCH = 36; + UC_RISCV_REG_UEPC = 37; + UC_RISCV_REG_UCAUSE = 38; + UC_RISCV_REG_UTVAL = 39; + UC_RISCV_REG_UIP = 40; + UC_RISCV_REG_FFLAGS = 41; + UC_RISCV_REG_FRM = 42; + UC_RISCV_REG_FCSR = 43; + UC_RISCV_REG_CYCLE = 44; + UC_RISCV_REG_TIME = 45; + UC_RISCV_REG_INSTRET = 46; + UC_RISCV_REG_HPMCOUNTER3 = 47; + UC_RISCV_REG_HPMCOUNTER4 = 48; + UC_RISCV_REG_HPMCOUNTER5 = 49; + UC_RISCV_REG_HPMCOUNTER6 = 50; + UC_RISCV_REG_HPMCOUNTER7 = 51; + UC_RISCV_REG_HPMCOUNTER8 = 52; + UC_RISCV_REG_HPMCOUNTER9 = 53; + UC_RISCV_REG_HPMCOUNTER10 = 54; + UC_RISCV_REG_HPMCOUNTER11 = 55; + UC_RISCV_REG_HPMCOUNTER12 = 56; + UC_RISCV_REG_HPMCOUNTER13 = 57; + UC_RISCV_REG_HPMCOUNTER14 = 58; + UC_RISCV_REG_HPMCOUNTER15 = 59; + UC_RISCV_REG_HPMCOUNTER16 = 60; + UC_RISCV_REG_HPMCOUNTER17 = 61; + UC_RISCV_REG_HPMCOUNTER18 = 62; + UC_RISCV_REG_HPMCOUNTER19 = 63; + UC_RISCV_REG_HPMCOUNTER20 = 64; + UC_RISCV_REG_HPMCOUNTER21 = 65; + UC_RISCV_REG_HPMCOUNTER22 = 66; + UC_RISCV_REG_HPMCOUNTER23 = 67; + UC_RISCV_REG_HPMCOUNTER24 = 68; + UC_RISCV_REG_HPMCOUNTER25 = 69; + UC_RISCV_REG_HPMCOUNTER26 = 70; + UC_RISCV_REG_HPMCOUNTER27 = 71; + UC_RISCV_REG_HPMCOUNTER28 = 72; + UC_RISCV_REG_HPMCOUNTER29 = 73; + UC_RISCV_REG_HPMCOUNTER30 = 74; + UC_RISCV_REG_HPMCOUNTER31 = 75; + UC_RISCV_REG_CYCLEH = 76; + UC_RISCV_REG_TIMEH = 77; + UC_RISCV_REG_INSTRETH = 78; + UC_RISCV_REG_HPMCOUNTER3H = 79; + UC_RISCV_REG_HPMCOUNTER4H = 80; + UC_RISCV_REG_HPMCOUNTER5H = 81; + UC_RISCV_REG_HPMCOUNTER6H = 82; + UC_RISCV_REG_HPMCOUNTER7H = 83; + UC_RISCV_REG_HPMCOUNTER8H = 84; + UC_RISCV_REG_HPMCOUNTER9H = 85; + UC_RISCV_REG_HPMCOUNTER10H = 86; + UC_RISCV_REG_HPMCOUNTER11H = 87; + UC_RISCV_REG_HPMCOUNTER12H = 88; + UC_RISCV_REG_HPMCOUNTER13H = 89; + UC_RISCV_REG_HPMCOUNTER14H = 90; + UC_RISCV_REG_HPMCOUNTER15H = 91; + UC_RISCV_REG_HPMCOUNTER16H = 92; + UC_RISCV_REG_HPMCOUNTER17H = 93; + UC_RISCV_REG_HPMCOUNTER18H = 94; + UC_RISCV_REG_HPMCOUNTER19H = 95; + UC_RISCV_REG_HPMCOUNTER20H = 96; + UC_RISCV_REG_HPMCOUNTER21H = 97; + UC_RISCV_REG_HPMCOUNTER22H = 98; + UC_RISCV_REG_HPMCOUNTER23H = 99; + UC_RISCV_REG_HPMCOUNTER24H = 100; + UC_RISCV_REG_HPMCOUNTER25H = 101; + UC_RISCV_REG_HPMCOUNTER26H = 102; + UC_RISCV_REG_HPMCOUNTER27H = 103; + UC_RISCV_REG_HPMCOUNTER28H = 104; + UC_RISCV_REG_HPMCOUNTER29H = 105; + UC_RISCV_REG_HPMCOUNTER30H = 106; + UC_RISCV_REG_HPMCOUNTER31H = 107; + UC_RISCV_REG_MCYCLE = 108; + UC_RISCV_REG_MINSTRET = 109; + UC_RISCV_REG_MCYCLEH = 110; + UC_RISCV_REG_MINSTRETH = 111; + UC_RISCV_REG_MVENDORID = 112; + UC_RISCV_REG_MARCHID = 113; + UC_RISCV_REG_MIMPID = 114; + UC_RISCV_REG_MHARTID = 115; + UC_RISCV_REG_MSTATUS = 116; + UC_RISCV_REG_MISA = 117; + UC_RISCV_REG_MEDELEG = 118; + UC_RISCV_REG_MIDELEG = 119; + UC_RISCV_REG_MIE = 120; + UC_RISCV_REG_MTVEC = 121; + UC_RISCV_REG_MCOUNTEREN = 122; + UC_RISCV_REG_MSTATUSH = 123; + UC_RISCV_REG_MUCOUNTEREN = 124; + UC_RISCV_REG_MSCOUNTEREN = 125; + UC_RISCV_REG_MHCOUNTEREN = 126; + UC_RISCV_REG_MSCRATCH = 127; + UC_RISCV_REG_MEPC = 128; + UC_RISCV_REG_MCAUSE = 129; + UC_RISCV_REG_MTVAL = 130; + UC_RISCV_REG_MIP = 131; + UC_RISCV_REG_MBADADDR = 132; + UC_RISCV_REG_SSTATUS = 133; + UC_RISCV_REG_SEDELEG = 134; + UC_RISCV_REG_SIDELEG = 135; + UC_RISCV_REG_SIE = 136; + UC_RISCV_REG_STVEC = 137; + UC_RISCV_REG_SCOUNTEREN = 138; + UC_RISCV_REG_SSCRATCH = 139; + UC_RISCV_REG_SEPC = 140; + UC_RISCV_REG_SCAUSE = 141; + UC_RISCV_REG_STVAL = 142; + UC_RISCV_REG_SIP = 143; + UC_RISCV_REG_SBADADDR = 144; + UC_RISCV_REG_SPTBR = 145; + UC_RISCV_REG_SATP = 146; + UC_RISCV_REG_HSTATUS = 147; + UC_RISCV_REG_HEDELEG = 148; + UC_RISCV_REG_HIDELEG = 149; + UC_RISCV_REG_HIE = 150; + UC_RISCV_REG_HCOUNTEREN = 151; + UC_RISCV_REG_HTVAL = 152; + UC_RISCV_REG_HIP = 153; + UC_RISCV_REG_HTINST = 154; + UC_RISCV_REG_HGATP = 155; + UC_RISCV_REG_HTIMEDELTA = 156; + UC_RISCV_REG_HTIMEDELTAH = 157; + // Floating-point registers - UC_RISCV_REG_F0 = 33; - UC_RISCV_REG_F1 = 34; - UC_RISCV_REG_F2 = 35; - UC_RISCV_REG_F3 = 36; - UC_RISCV_REG_F4 = 37; - UC_RISCV_REG_F5 = 38; - UC_RISCV_REG_F6 = 39; - UC_RISCV_REG_F7 = 40; - UC_RISCV_REG_F8 = 41; - UC_RISCV_REG_F9 = 42; - UC_RISCV_REG_F10 = 43; - UC_RISCV_REG_F11 = 44; - UC_RISCV_REG_F12 = 45; - UC_RISCV_REG_F13 = 46; - UC_RISCV_REG_F14 = 47; - UC_RISCV_REG_F15 = 48; - UC_RISCV_REG_F16 = 49; - UC_RISCV_REG_F17 = 50; - UC_RISCV_REG_F18 = 51; - UC_RISCV_REG_F19 = 52; - UC_RISCV_REG_F20 = 53; - UC_RISCV_REG_F21 = 54; - UC_RISCV_REG_F22 = 55; - UC_RISCV_REG_F23 = 56; - UC_RISCV_REG_F24 = 57; - UC_RISCV_REG_F25 = 58; - UC_RISCV_REG_F26 = 59; - UC_RISCV_REG_F27 = 60; - UC_RISCV_REG_F28 = 61; - UC_RISCV_REG_F29 = 62; - UC_RISCV_REG_F30 = 63; - UC_RISCV_REG_F31 = 64; - UC_RISCV_REG_PC = 65; - UC_RISCV_REG_ENDING = 66; + UC_RISCV_REG_F0 = 158; + UC_RISCV_REG_F1 = 159; + UC_RISCV_REG_F2 = 160; + UC_RISCV_REG_F3 = 161; + UC_RISCV_REG_F4 = 162; + UC_RISCV_REG_F5 = 163; + UC_RISCV_REG_F6 = 164; + UC_RISCV_REG_F7 = 165; + UC_RISCV_REG_F8 = 166; + UC_RISCV_REG_F9 = 167; + UC_RISCV_REG_F10 = 168; + UC_RISCV_REG_F11 = 169; + UC_RISCV_REG_F12 = 170; + UC_RISCV_REG_F13 = 171; + UC_RISCV_REG_F14 = 172; + UC_RISCV_REG_F15 = 173; + UC_RISCV_REG_F16 = 174; + UC_RISCV_REG_F17 = 175; + UC_RISCV_REG_F18 = 176; + UC_RISCV_REG_F19 = 177; + UC_RISCV_REG_F20 = 178; + UC_RISCV_REG_F21 = 179; + UC_RISCV_REG_F22 = 180; + UC_RISCV_REG_F23 = 181; + UC_RISCV_REG_F24 = 182; + UC_RISCV_REG_F25 = 183; + UC_RISCV_REG_F26 = 184; + UC_RISCV_REG_F27 = 185; + UC_RISCV_REG_F28 = 186; + UC_RISCV_REG_F29 = 187; + UC_RISCV_REG_F30 = 188; + UC_RISCV_REG_F31 = 189; + UC_RISCV_REG_PC = 190; + UC_RISCV_REG_ENDING = 191; // Alias registers UC_RISCV_REG_ZERO = 1; @@ -127,38 +254,38 @@ const UC_RISCV_REG_T4 = 30; UC_RISCV_REG_T5 = 31; UC_RISCV_REG_T6 = 32; - UC_RISCV_REG_FT0 = 33; - UC_RISCV_REG_FT1 = 34; - UC_RISCV_REG_FT2 = 35; - UC_RISCV_REG_FT3 = 36; - UC_RISCV_REG_FT4 = 37; - UC_RISCV_REG_FT5 = 38; - UC_RISCV_REG_FT6 = 39; - UC_RISCV_REG_FT7 = 40; - UC_RISCV_REG_FS0 = 41; - UC_RISCV_REG_FS1 = 42; - UC_RISCV_REG_FA0 = 43; - UC_RISCV_REG_FA1 = 44; - UC_RISCV_REG_FA2 = 45; - UC_RISCV_REG_FA3 = 46; - UC_RISCV_REG_FA4 = 47; - UC_RISCV_REG_FA5 = 48; - UC_RISCV_REG_FA6 = 49; - UC_RISCV_REG_FA7 = 50; - UC_RISCV_REG_FS2 = 51; - UC_RISCV_REG_FS3 = 52; - UC_RISCV_REG_FS4 = 53; - UC_RISCV_REG_FS5 = 54; - UC_RISCV_REG_FS6 = 55; - UC_RISCV_REG_FS7 = 56; - UC_RISCV_REG_FS8 = 57; - UC_RISCV_REG_FS9 = 58; - UC_RISCV_REG_FS10 = 59; - UC_RISCV_REG_FS11 = 60; - UC_RISCV_REG_FT8 = 61; - UC_RISCV_REG_FT9 = 62; - UC_RISCV_REG_FT10 = 63; - UC_RISCV_REG_FT11 = 64; + UC_RISCV_REG_FT0 = 158; + UC_RISCV_REG_FT1 = 159; + UC_RISCV_REG_FT2 = 160; + UC_RISCV_REG_FT3 = 161; + UC_RISCV_REG_FT4 = 162; + UC_RISCV_REG_FT5 = 163; + UC_RISCV_REG_FT6 = 164; + UC_RISCV_REG_FT7 = 165; + UC_RISCV_REG_FS0 = 166; + UC_RISCV_REG_FS1 = 167; + UC_RISCV_REG_FA0 = 168; + UC_RISCV_REG_FA1 = 169; + UC_RISCV_REG_FA2 = 170; + UC_RISCV_REG_FA3 = 171; + UC_RISCV_REG_FA4 = 172; + UC_RISCV_REG_FA5 = 173; + UC_RISCV_REG_FA6 = 174; + UC_RISCV_REG_FA7 = 175; + UC_RISCV_REG_FS2 = 176; + UC_RISCV_REG_FS3 = 177; + UC_RISCV_REG_FS4 = 178; + UC_RISCV_REG_FS5 = 179; + UC_RISCV_REG_FS6 = 180; + UC_RISCV_REG_FS7 = 181; + UC_RISCV_REG_FS8 = 182; + UC_RISCV_REG_FS9 = 183; + UC_RISCV_REG_FS10 = 184; + UC_RISCV_REG_FS11 = 185; + UC_RISCV_REG_FT8 = 186; + UC_RISCV_REG_FT9 = 187; + UC_RISCV_REG_FT10 = 188; + UC_RISCV_REG_FT11 = 189; implementation end. \ No newline at end of file diff --git a/bindings/pascal/unicorn/UnicornConst.pas b/bindings/pascal/unicorn/UnicornConst.pas index af67d5de..9dfbe0ed 100644 --- a/bindings/pascal/unicorn/UnicornConst.pas +++ b/bindings/pascal/unicorn/UnicornConst.pas @@ -7,11 +7,15 @@ interface const UC_API_MAJOR = 2; UC_API_MINOR = 0; + + UC_API_PATCH = 0; + UC_API_EXTRA = 5; UC_VERSION_MAJOR = 2; UC_VERSION_MINOR = 0; - UC_VERSION_EXTRA = 0; + UC_VERSION_PATCH = 0; + UC_VERSION_EXTRA = 5; UC_SECOND_SCALE = 1000000; UC_MILISECOND_SCALE = 1000; UC_ARCH_ARM = 1; diff --git a/bindings/pascal/unicorn/X86Const.pas b/bindings/pascal/unicorn/X86Const.pas index 7301659d..ab0a85f1 100644 --- a/bindings/pascal/unicorn/X86Const.pas +++ b/bindings/pascal/unicorn/X86Const.pas @@ -282,7 +282,12 @@ const UC_X86_REG_GS_BASE = 231; UC_X86_REG_FLAGS = 232; UC_X86_REG_RFLAGS = 233; - UC_X86_REG_ENDING = 234; + UC_X86_REG_FIP = 234; + UC_X86_REG_FCS = 235; + UC_X86_REG_FDP = 236; + UC_X86_REG_FDS = 237; + UC_X86_REG_FOP = 238; + UC_X86_REG_ENDING = 239; // X86 instructions diff --git a/bindings/python/unicorn/x86_const.py b/bindings/python/unicorn/x86_const.py index fd380464..b99f46b1 100644 --- a/bindings/python/unicorn/x86_const.py +++ b/bindings/python/unicorn/x86_const.py @@ -277,7 +277,12 @@ UC_X86_REG_FS_BASE = 230 UC_X86_REG_GS_BASE = 231 UC_X86_REG_FLAGS = 232 UC_X86_REG_RFLAGS = 233 -UC_X86_REG_ENDING = 234 +UC_X86_REG_FIP = 234 +UC_X86_REG_FCS = 235 +UC_X86_REG_FDP = 236 +UC_X86_REG_FDS = 237 +UC_X86_REG_FOP = 238 +UC_X86_REG_ENDING = 239 # X86 instructions diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb index b4e72a04..dd59f78c 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb @@ -4,15 +4,15 @@ module UnicornEngine # M68K CPU - UC_CPU_M5206_CPU = 0 - UC_CPU_M68000_CPU = 1 - UC_CPU_M68020_CPU = 2 - UC_CPU_M68030_CPU = 3 - UC_CPU_M68040_CPU = 4 - UC_CPU_M68060_CPU = 5 - UC_CPU_M5208_CPU = 6 - UC_CPU_CFV4E_CPU = 7 - UC_CPU_ANY_CPU = 8 + UC_CPU_M68K_M5206 = 0 + UC_CPU_M68K_M68000 = 1 + UC_CPU_M68K_M68020 = 2 + UC_CPU_M68K_M68030 = 3 + UC_CPU_M68K_M68040 = 4 + UC_CPU_M68K_M68060 = 5 + UC_CPU_M68K_M5208 = 6 + UC_CPU_M68K_CFV4E = 7 + UC_CPU_M68K_ANY = 8 # M68K registers diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb index 636686e2..59623bcf 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb @@ -54,41 +54,168 @@ module UnicornEngine UC_RISCV_REG_X30 = 31 UC_RISCV_REG_X31 = 32 +# RISCV CSR + UC_RISCV_REG_USTATUS = 33 + UC_RISCV_REG_UIE = 34 + UC_RISCV_REG_UTVEC = 35 + UC_RISCV_REG_USCRATCH = 36 + UC_RISCV_REG_UEPC = 37 + UC_RISCV_REG_UCAUSE = 38 + UC_RISCV_REG_UTVAL = 39 + UC_RISCV_REG_UIP = 40 + UC_RISCV_REG_FFLAGS = 41 + UC_RISCV_REG_FRM = 42 + UC_RISCV_REG_FCSR = 43 + UC_RISCV_REG_CYCLE = 44 + UC_RISCV_REG_TIME = 45 + UC_RISCV_REG_INSTRET = 46 + UC_RISCV_REG_HPMCOUNTER3 = 47 + UC_RISCV_REG_HPMCOUNTER4 = 48 + UC_RISCV_REG_HPMCOUNTER5 = 49 + UC_RISCV_REG_HPMCOUNTER6 = 50 + UC_RISCV_REG_HPMCOUNTER7 = 51 + UC_RISCV_REG_HPMCOUNTER8 = 52 + UC_RISCV_REG_HPMCOUNTER9 = 53 + UC_RISCV_REG_HPMCOUNTER10 = 54 + UC_RISCV_REG_HPMCOUNTER11 = 55 + UC_RISCV_REG_HPMCOUNTER12 = 56 + UC_RISCV_REG_HPMCOUNTER13 = 57 + UC_RISCV_REG_HPMCOUNTER14 = 58 + UC_RISCV_REG_HPMCOUNTER15 = 59 + UC_RISCV_REG_HPMCOUNTER16 = 60 + UC_RISCV_REG_HPMCOUNTER17 = 61 + UC_RISCV_REG_HPMCOUNTER18 = 62 + UC_RISCV_REG_HPMCOUNTER19 = 63 + UC_RISCV_REG_HPMCOUNTER20 = 64 + UC_RISCV_REG_HPMCOUNTER21 = 65 + UC_RISCV_REG_HPMCOUNTER22 = 66 + UC_RISCV_REG_HPMCOUNTER23 = 67 + UC_RISCV_REG_HPMCOUNTER24 = 68 + UC_RISCV_REG_HPMCOUNTER25 = 69 + UC_RISCV_REG_HPMCOUNTER26 = 70 + UC_RISCV_REG_HPMCOUNTER27 = 71 + UC_RISCV_REG_HPMCOUNTER28 = 72 + UC_RISCV_REG_HPMCOUNTER29 = 73 + UC_RISCV_REG_HPMCOUNTER30 = 74 + UC_RISCV_REG_HPMCOUNTER31 = 75 + UC_RISCV_REG_CYCLEH = 76 + UC_RISCV_REG_TIMEH = 77 + UC_RISCV_REG_INSTRETH = 78 + UC_RISCV_REG_HPMCOUNTER3H = 79 + UC_RISCV_REG_HPMCOUNTER4H = 80 + UC_RISCV_REG_HPMCOUNTER5H = 81 + UC_RISCV_REG_HPMCOUNTER6H = 82 + UC_RISCV_REG_HPMCOUNTER7H = 83 + UC_RISCV_REG_HPMCOUNTER8H = 84 + UC_RISCV_REG_HPMCOUNTER9H = 85 + UC_RISCV_REG_HPMCOUNTER10H = 86 + UC_RISCV_REG_HPMCOUNTER11H = 87 + UC_RISCV_REG_HPMCOUNTER12H = 88 + UC_RISCV_REG_HPMCOUNTER13H = 89 + UC_RISCV_REG_HPMCOUNTER14H = 90 + UC_RISCV_REG_HPMCOUNTER15H = 91 + UC_RISCV_REG_HPMCOUNTER16H = 92 + UC_RISCV_REG_HPMCOUNTER17H = 93 + UC_RISCV_REG_HPMCOUNTER18H = 94 + UC_RISCV_REG_HPMCOUNTER19H = 95 + UC_RISCV_REG_HPMCOUNTER20H = 96 + UC_RISCV_REG_HPMCOUNTER21H = 97 + UC_RISCV_REG_HPMCOUNTER22H = 98 + UC_RISCV_REG_HPMCOUNTER23H = 99 + UC_RISCV_REG_HPMCOUNTER24H = 100 + UC_RISCV_REG_HPMCOUNTER25H = 101 + UC_RISCV_REG_HPMCOUNTER26H = 102 + UC_RISCV_REG_HPMCOUNTER27H = 103 + UC_RISCV_REG_HPMCOUNTER28H = 104 + UC_RISCV_REG_HPMCOUNTER29H = 105 + UC_RISCV_REG_HPMCOUNTER30H = 106 + UC_RISCV_REG_HPMCOUNTER31H = 107 + UC_RISCV_REG_MCYCLE = 108 + UC_RISCV_REG_MINSTRET = 109 + UC_RISCV_REG_MCYCLEH = 110 + UC_RISCV_REG_MINSTRETH = 111 + UC_RISCV_REG_MVENDORID = 112 + UC_RISCV_REG_MARCHID = 113 + UC_RISCV_REG_MIMPID = 114 + UC_RISCV_REG_MHARTID = 115 + UC_RISCV_REG_MSTATUS = 116 + UC_RISCV_REG_MISA = 117 + UC_RISCV_REG_MEDELEG = 118 + UC_RISCV_REG_MIDELEG = 119 + UC_RISCV_REG_MIE = 120 + UC_RISCV_REG_MTVEC = 121 + UC_RISCV_REG_MCOUNTEREN = 122 + UC_RISCV_REG_MSTATUSH = 123 + UC_RISCV_REG_MUCOUNTEREN = 124 + UC_RISCV_REG_MSCOUNTEREN = 125 + UC_RISCV_REG_MHCOUNTEREN = 126 + UC_RISCV_REG_MSCRATCH = 127 + UC_RISCV_REG_MEPC = 128 + UC_RISCV_REG_MCAUSE = 129 + UC_RISCV_REG_MTVAL = 130 + UC_RISCV_REG_MIP = 131 + UC_RISCV_REG_MBADADDR = 132 + UC_RISCV_REG_SSTATUS = 133 + UC_RISCV_REG_SEDELEG = 134 + UC_RISCV_REG_SIDELEG = 135 + UC_RISCV_REG_SIE = 136 + UC_RISCV_REG_STVEC = 137 + UC_RISCV_REG_SCOUNTEREN = 138 + UC_RISCV_REG_SSCRATCH = 139 + UC_RISCV_REG_SEPC = 140 + UC_RISCV_REG_SCAUSE = 141 + UC_RISCV_REG_STVAL = 142 + UC_RISCV_REG_SIP = 143 + UC_RISCV_REG_SBADADDR = 144 + UC_RISCV_REG_SPTBR = 145 + UC_RISCV_REG_SATP = 146 + UC_RISCV_REG_HSTATUS = 147 + UC_RISCV_REG_HEDELEG = 148 + UC_RISCV_REG_HIDELEG = 149 + UC_RISCV_REG_HIE = 150 + UC_RISCV_REG_HCOUNTEREN = 151 + UC_RISCV_REG_HTVAL = 152 + UC_RISCV_REG_HIP = 153 + UC_RISCV_REG_HTINST = 154 + UC_RISCV_REG_HGATP = 155 + UC_RISCV_REG_HTIMEDELTA = 156 + UC_RISCV_REG_HTIMEDELTAH = 157 + # Floating-point registers - UC_RISCV_REG_F0 = 33 - UC_RISCV_REG_F1 = 34 - UC_RISCV_REG_F2 = 35 - UC_RISCV_REG_F3 = 36 - UC_RISCV_REG_F4 = 37 - UC_RISCV_REG_F5 = 38 - UC_RISCV_REG_F6 = 39 - UC_RISCV_REG_F7 = 40 - UC_RISCV_REG_F8 = 41 - UC_RISCV_REG_F9 = 42 - UC_RISCV_REG_F10 = 43 - UC_RISCV_REG_F11 = 44 - UC_RISCV_REG_F12 = 45 - UC_RISCV_REG_F13 = 46 - UC_RISCV_REG_F14 = 47 - UC_RISCV_REG_F15 = 48 - UC_RISCV_REG_F16 = 49 - UC_RISCV_REG_F17 = 50 - UC_RISCV_REG_F18 = 51 - UC_RISCV_REG_F19 = 52 - UC_RISCV_REG_F20 = 53 - UC_RISCV_REG_F21 = 54 - UC_RISCV_REG_F22 = 55 - UC_RISCV_REG_F23 = 56 - UC_RISCV_REG_F24 = 57 - UC_RISCV_REG_F25 = 58 - UC_RISCV_REG_F26 = 59 - UC_RISCV_REG_F27 = 60 - UC_RISCV_REG_F28 = 61 - UC_RISCV_REG_F29 = 62 - UC_RISCV_REG_F30 = 63 - UC_RISCV_REG_F31 = 64 - UC_RISCV_REG_PC = 65 - UC_RISCV_REG_ENDING = 66 + UC_RISCV_REG_F0 = 158 + UC_RISCV_REG_F1 = 159 + UC_RISCV_REG_F2 = 160 + UC_RISCV_REG_F3 = 161 + UC_RISCV_REG_F4 = 162 + UC_RISCV_REG_F5 = 163 + UC_RISCV_REG_F6 = 164 + UC_RISCV_REG_F7 = 165 + UC_RISCV_REG_F8 = 166 + UC_RISCV_REG_F9 = 167 + UC_RISCV_REG_F10 = 168 + UC_RISCV_REG_F11 = 169 + UC_RISCV_REG_F12 = 170 + UC_RISCV_REG_F13 = 171 + UC_RISCV_REG_F14 = 172 + UC_RISCV_REG_F15 = 173 + UC_RISCV_REG_F16 = 174 + UC_RISCV_REG_F17 = 175 + UC_RISCV_REG_F18 = 176 + UC_RISCV_REG_F19 = 177 + UC_RISCV_REG_F20 = 178 + UC_RISCV_REG_F21 = 179 + UC_RISCV_REG_F22 = 180 + UC_RISCV_REG_F23 = 181 + UC_RISCV_REG_F24 = 182 + UC_RISCV_REG_F25 = 183 + UC_RISCV_REG_F26 = 184 + UC_RISCV_REG_F27 = 185 + UC_RISCV_REG_F28 = 186 + UC_RISCV_REG_F29 = 187 + UC_RISCV_REG_F30 = 188 + UC_RISCV_REG_F31 = 189 + UC_RISCV_REG_PC = 190 + UC_RISCV_REG_ENDING = 191 # Alias registers UC_RISCV_REG_ZERO = 1 @@ -124,36 +251,36 @@ module UnicornEngine UC_RISCV_REG_T4 = 30 UC_RISCV_REG_T5 = 31 UC_RISCV_REG_T6 = 32 - UC_RISCV_REG_FT0 = 33 - UC_RISCV_REG_FT1 = 34 - UC_RISCV_REG_FT2 = 35 - UC_RISCV_REG_FT3 = 36 - UC_RISCV_REG_FT4 = 37 - UC_RISCV_REG_FT5 = 38 - UC_RISCV_REG_FT6 = 39 - UC_RISCV_REG_FT7 = 40 - UC_RISCV_REG_FS0 = 41 - UC_RISCV_REG_FS1 = 42 - UC_RISCV_REG_FA0 = 43 - UC_RISCV_REG_FA1 = 44 - UC_RISCV_REG_FA2 = 45 - UC_RISCV_REG_FA3 = 46 - UC_RISCV_REG_FA4 = 47 - UC_RISCV_REG_FA5 = 48 - UC_RISCV_REG_FA6 = 49 - UC_RISCV_REG_FA7 = 50 - UC_RISCV_REG_FS2 = 51 - UC_RISCV_REG_FS3 = 52 - UC_RISCV_REG_FS4 = 53 - UC_RISCV_REG_FS5 = 54 - UC_RISCV_REG_FS6 = 55 - UC_RISCV_REG_FS7 = 56 - UC_RISCV_REG_FS8 = 57 - UC_RISCV_REG_FS9 = 58 - UC_RISCV_REG_FS10 = 59 - UC_RISCV_REG_FS11 = 60 - UC_RISCV_REG_FT8 = 61 - UC_RISCV_REG_FT9 = 62 - UC_RISCV_REG_FT10 = 63 - UC_RISCV_REG_FT11 = 64 + UC_RISCV_REG_FT0 = 158 + UC_RISCV_REG_FT1 = 159 + UC_RISCV_REG_FT2 = 160 + UC_RISCV_REG_FT3 = 161 + UC_RISCV_REG_FT4 = 162 + UC_RISCV_REG_FT5 = 163 + UC_RISCV_REG_FT6 = 164 + UC_RISCV_REG_FT7 = 165 + UC_RISCV_REG_FS0 = 166 + UC_RISCV_REG_FS1 = 167 + UC_RISCV_REG_FA0 = 168 + UC_RISCV_REG_FA1 = 169 + UC_RISCV_REG_FA2 = 170 + UC_RISCV_REG_FA3 = 171 + UC_RISCV_REG_FA4 = 172 + UC_RISCV_REG_FA5 = 173 + UC_RISCV_REG_FA6 = 174 + UC_RISCV_REG_FA7 = 175 + UC_RISCV_REG_FS2 = 176 + UC_RISCV_REG_FS3 = 177 + UC_RISCV_REG_FS4 = 178 + UC_RISCV_REG_FS5 = 179 + UC_RISCV_REG_FS6 = 180 + UC_RISCV_REG_FS7 = 181 + UC_RISCV_REG_FS8 = 182 + UC_RISCV_REG_FS9 = 183 + UC_RISCV_REG_FS10 = 184 + UC_RISCV_REG_FS11 = 185 + UC_RISCV_REG_FT8 = 186 + UC_RISCV_REG_FT9 = 187 + UC_RISCV_REG_FT10 = 188 + UC_RISCV_REG_FT11 = 189 end \ No newline at end of file diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb index 6c22c744..937edc56 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb @@ -4,11 +4,15 @@ module UnicornEngine UC_API_MAJOR = 2 UC_API_MINOR = 0 + + UC_API_PATCH = 0 + UC_API_EXTRA = 5 UC_VERSION_MAJOR = 2 UC_VERSION_MINOR = 0 - UC_VERSION_EXTRA = 0 + UC_VERSION_PATCH = 0 + UC_VERSION_EXTRA = 5 UC_SECOND_SCALE = 1000000 UC_MILISECOND_SCALE = 1000 UC_ARCH_ARM = 1 diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb index 84701acb..76e899df 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb @@ -279,7 +279,12 @@ module UnicornEngine UC_X86_REG_GS_BASE = 231 UC_X86_REG_FLAGS = 232 UC_X86_REG_RFLAGS = 233 - UC_X86_REG_ENDING = 234 + UC_X86_REG_FIP = 234 + UC_X86_REG_FCS = 235 + UC_X86_REG_FDP = 236 + UC_X86_REG_FDS = 237 + UC_X86_REG_FOP = 238 + UC_X86_REG_ENDING = 239 # X86 instructions From 6fabf305373b136f7d7428d7c8b573580d5924fe Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 19:12:36 +0100 Subject: [PATCH 07/18] Fix a invalid memory access Note: This probably addresses the ramdom failed CI on mingw64 --- qemu/unicorn_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/unicorn_common.h b/qemu/unicorn_common.h index 84bbb9f1..5176430e 100644 --- a/qemu/unicorn_common.h +++ b/qemu/unicorn_common.h @@ -58,9 +58,9 @@ static void release_common(void *t) // these function is not available outside qemu // so we keep them here instead of outside uc_close. + memory_free(s->uc); address_space_destroy(&s->uc->address_space_memory); address_space_destroy(&s->uc->address_space_io); - memory_free(s->uc); /* clean up uc->l1_map. */ tb_cleanup(s->uc); /* clean up tcg_ctx->code_gen_buffer. */ From 3f64491fdacc06fd10660a8045c1bb04bac1ffd3 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 19:38:02 +0100 Subject: [PATCH 08/18] Add further test for arm system mode transition --- tests/unit/test_arm.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/tests/unit/test_arm.c b/tests/unit/test_arm.c index 80c07443..b1eaebde 100644 --- a/tests/unit/test_arm.c +++ b/tests/unit/test_arm.c @@ -325,6 +325,8 @@ static void test_arm_usr32_to_svc32() OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); r_sp = 0x12345678; OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp)); + r_lr = 0x00102220; + OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr)); r_cpsr = 0x4000009b; // UND32 OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); @@ -332,18 +334,28 @@ static void test_arm_usr32_to_svc32() OK(uc_reg_write(uc, UC_ARM_REG_SPSR, &r_spsr)); r_sp = 0xDEAD0000; OK(uc_reg_write(uc, UC_ARM_REG_SP, &r_sp)); - r_lr = code_start + 8; + r_lr = 0x00509998; OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr)); + OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); + TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 0xb); // We are in UND32 + r_cpsr = 0x40000090; // USR32 OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); r_sp = 0x0010000; OK(uc_reg_write(uc, UC_ARM_REG_R13, &r_sp)); + r_lr = 0x0001234; + OK(uc_reg_write(uc, UC_ARM_REG_LR, &r_lr)); + + OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); + TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 0); // We are in USR32 r_cpsr = 0x40000093; // SVC32 OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr)); + OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr)); OK(uc_reg_read(uc, UC_ARM_REG_SP, &r_sp)); + TEST_CHECK((r_cpsr & ((1 << 4) - 1)) == 3); // We are in SVC32 TEST_CHECK(r_sp == 0x12345678); OK(uc_close(uc)); From 7a886f59df4be5d2db8a4f56b7922b600221ba04 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 19:38:22 +0100 Subject: [PATCH 09/18] Fix #1525 --- qemu/target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 0ee137f9..d9e77e34 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -7983,11 +7983,11 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, * to switch mode. (Those are caught by translate.c for writes * triggered by guest instructions.) */ - mask &= ~CPSR_M; - // Unicorn: No, it can also be uc_reg_write, let user switch registers banks. if (write_type == CPSRWriteByUnicorn) { switch_mode(env, val & CPSR_M); + } else { + mask &= ~CPSR_M; } } else if (bad_mode_switch(env, val & CPSR_M, write_type)) { /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in From b8817518ae15905fd59e4e69005c8ce5382662d8 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 20:02:21 +0100 Subject: [PATCH 10/18] Add a test for arm64 pac extension --- tests/unit/test_arm64.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/tests/unit/test_arm64.c b/tests/unit/test_arm64.c index 9ae38b0f..804a4842 100644 --- a/tests/unit/test_arm64.c +++ b/tests/unit/test_arm64.c @@ -4,9 +4,10 @@ const uint64_t code_start = 0x1000; const uint64_t code_len = 0x4000; static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode, - const char *code, uint64_t size) + const char *code, uint64_t size, uc_cpu_arm cpu) { OK(uc_open(arch, mode, uc)); + OK(uc_ctl_set_cpu_model(*uc, cpu)); OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL)); OK(uc_mem_write(*uc, code_start, code, size)); } @@ -27,7 +28,7 @@ static void test_arm64_until() uint64_t r_pc = 0x00000000; uint64_t r_x28 = 0x12341234; - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); // initialize machine registers OK(uc_reg_write(uc, UC_ARM64_REG_X16, &r_x16)); @@ -54,7 +55,7 @@ static void test_arm64_code_patching() { uc_engine *uc; char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1 - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); // zero out x0 uint64_t r_x0 = 0x0; OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0)); @@ -83,7 +84,7 @@ static void test_arm64_code_patching_count() { uc_engine *uc; char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1 - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); // zero out x0 uint64_t r_x0 = 0x0; OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0)); @@ -109,7 +110,31 @@ static void test_arm64_code_patching_count() OK(uc_close(uc)); } +static void test_arm64_v8_pac() { + uc_engine *uc; + char code[] = "\x28\xfd\xea\xc8"; // casal x10, x8, [x9] + uint64_t r_x9, r_x8, mem; + + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_MAX); + + OK(uc_mem_map(uc, 0x40000, 0x1000, UC_PROT_ALL)); + OK(uc_mem_write(uc, 0x40000, "\x00\x00\x00\x00\x00\x00\x00\x00", 8)); + r_x9 = 0x40000; + OK(uc_reg_write(uc, UC_ARM64_REG_X9, &r_x9)); + r_x8 = 0xdeadbeafdeadbeaf; + OK(uc_reg_write(uc, UC_ARM64_REG_X8, &r_x8)); + + OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); + + OK(uc_mem_read(uc, 0x40000, (void*)&mem, 8)); + + TEST_CHECK(mem == r_x8); + + OK(uc_close(uc)); +} + TEST_LIST = {{"test_arm64_until", test_arm64_until}, {"test_arm64_code_patching", test_arm64_code_patching}, {"test_arm64_code_patching_count", test_arm64_code_patching_count}, + {"test_arm64_v8_pac", test_arm64_v8_pac}, {NULL, NULL}}; From c3a49766d8fe2530ce4c23cb3b0aed6e9be09ef2 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 20:02:41 +0100 Subject: [PATCH 11/18] Fix #1522 --- qemu/target/arm/cpu64.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index 52933554..a91dc6d4 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -320,8 +320,6 @@ static const ARMCPUInfo aarch64_cpus[] = { ARMCPU *cpu_aarch64_init(struct uc_struct *uc) { - int i; - char *cpu_model = "cortex-a72"; ARMCPU *cpu; CPUState *cs; CPUClass *cc; @@ -331,6 +329,13 @@ ARMCPU *cpu_aarch64_init(struct uc_struct *uc) return NULL; } + if (uc->cpu_model == INT_MAX) { + uc->cpu_model = UC_CPU_AARCH64_A72; + } else if (uc->cpu_model >= sizeof(aarch64_cpus)) { + free(cpu); + return NULL; + } + cs = (CPUState *)cpu; cc = (CPUClass *)&cpu->cc; cs->cc = cc; @@ -349,17 +354,8 @@ ARMCPU *cpu_aarch64_init(struct uc_struct *uc) /* init ARMCPU */ arm_cpu_initfn(uc, cs); - for (i = 0; i < ARRAY_SIZE(aarch64_cpus); i++) { - if (strcmp(cpu_model, aarch64_cpus[i].name) == 0) { - if (aarch64_cpus[i].initfn) { - aarch64_cpus[i].initfn(uc, cs); - } - break; - } - } - if (i == ARRAY_SIZE(aarch64_cpus)) { - free(cpu); - return NULL; + if (aarch64_cpus[uc->cpu_model].initfn) { + aarch64_cpus[uc->cpu_model].initfn(uc, cs); } /* postinit ARMCPU */ From 8e70f3e5243f803da8961cc178f23c09a7a7d39f Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 21:56:58 +0100 Subject: [PATCH 12/18] Format code --- tests/unit/test_arm64.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/tests/unit/test_arm64.c b/tests/unit/test_arm64.c index 804a4842..0c177164 100644 --- a/tests/unit/test_arm64.c +++ b/tests/unit/test_arm64.c @@ -28,7 +28,8 @@ static void test_arm64_until() uint64_t r_pc = 0x00000000; uint64_t r_x28 = 0x12341234; - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_AARCH64_A72); // initialize machine registers OK(uc_reg_write(uc, UC_ARM64_REG_X16, &r_x16)); @@ -55,7 +56,8 @@ static void test_arm64_code_patching() { uc_engine *uc; char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1 - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_AARCH64_A72); // zero out x0 uint64_t r_x0 = 0x0; OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0)); @@ -84,7 +86,8 @@ static void test_arm64_code_patching_count() { uc_engine *uc; char code[] = "\x00\x04\x00\x11"; // add w0, w0, 0x1 - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_A72); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_AARCH64_A72); // zero out x0 uint64_t r_x0 = 0x0; OK(uc_reg_write(uc, UC_ARM64_REG_X0, &r_x0)); @@ -110,12 +113,14 @@ static void test_arm64_code_patching_count() OK(uc_close(uc)); } -static void test_arm64_v8_pac() { +static void test_arm64_v8_pac() +{ uc_engine *uc; char code[] = "\x28\xfd\xea\xc8"; // casal x10, x8, [x9] uint64_t r_x9, r_x8, mem; - uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, UC_CPU_AARCH64_MAX); + uc_common_setup(&uc, UC_ARCH_ARM64, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_AARCH64_MAX); OK(uc_mem_map(uc, 0x40000, 0x1000, UC_PROT_ALL)); OK(uc_mem_write(uc, 0x40000, "\x00\x00\x00\x00\x00\x00\x00\x00", 8)); @@ -126,7 +131,7 @@ static void test_arm64_v8_pac() { OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); - OK(uc_mem_read(uc, 0x40000, (void*)&mem, 8)); + OK(uc_mem_read(uc, 0x40000, (void *)&mem, 8)); TEST_CHECK(mem == r_x8); From e84a5c44e9bf2e9dc8b25818ec263c90530b4b32 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 21:57:32 +0100 Subject: [PATCH 13/18] Add a test for arm mrc instruction (also for coproc) --- tests/unit/test_arm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/tests/unit/test_arm.c b/tests/unit/test_arm.c index b1eaebde..100f8b5c 100644 --- a/tests/unit/test_arm.c +++ b/tests/unit/test_arm.c @@ -457,6 +457,20 @@ static void test_arm_not_allow_privilege_escalation() OK(uc_close(uc)); } +static void test_arm_mrc() +{ + uc_engine *uc; + // mrc p15, #0, r0, c1, c1, #0 + char code[] = "\x11\x0F\x11\xEE"; + + uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code, sizeof(code) - 1, + UC_CPU_ARM_MAX); + + OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); + + OK(uc_close(uc)); +} + TEST_LIST = {{"test_arm_nop", test_arm_nop}, {"test_arm_thumb_sub", test_arm_thumb_sub}, {"test_armeb_sub", test_armeb_sub}, @@ -471,4 +485,5 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop}, {"test_arm_thumb_smlabb", test_arm_thumb_smlabb}, {"test_arm_not_allow_privilege_escalation", test_arm_not_allow_privilege_escalation}, + {"test_arm_mrc", test_arm_mrc}, {NULL, NULL}}; \ No newline at end of file From 4567b4a7908132a0cf4a5273682a9e2e6b33d93e Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 21:57:46 +0100 Subject: [PATCH 14/18] Fix the wrong arm cpu index --- include/unicorn/arm.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/unicorn/arm.h b/include/unicorn/arm.h index 966aada9..a5b88563 100644 --- a/include/unicorn/arm.h +++ b/include/unicorn/arm.h @@ -43,6 +43,7 @@ typedef enum uc_cpu_arm { UC_CPU_ARM_PXA260, UC_CPU_ARM_PXA261, UC_CPU_ARM_PXA262, + UC_CPU_ARM_PXA270, UC_CPU_ARM_PXA270A0, UC_CPU_ARM_PXA270A1, UC_CPU_ARM_PXA270B0, From 8ad9f8ecb1cbed9f1e5e451970f885b4b457c5bf Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 21:58:40 +0100 Subject: [PATCH 15/18] This reverts Hack 05ba21160619724033ec83469bbb66bda9e3f5fb and applies the correct fix And enable experimental v8 support for arm max cpu --- qemu/target/arm/cpu.c | 66 ++++++++++++++++++++++++++++++++++++----- qemu/target/arm/cpu64.c | 11 ------- 2 files changed, 59 insertions(+), 18 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index e034192c..f5cb2eb7 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -184,13 +184,6 @@ static void arm_cpu_reset(CPUState *dev) } else { env->pstate = PSTATE_MODE_EL1h; } - /* - * Unicorn: Hack to force to enable EL2/EL3 for aarch64 so that we can - * use the full 64bits virtual address space. - * - * See cpu_aarch64_init for details. - */ - env->pstate = PSTATE_MODE_EL1h; env->pc = cpu->rvbar; } @@ -705,6 +698,17 @@ void arm_cpu_post_init(CPUState *obj) cpu->rvbar = 0; } + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { + /* Add the has_el3 state CPU property only if EL3 is allowed. This will + * prevent "has_el3" from existing on CPUs which cannot support EL3. + */ + cpu->has_el3 = true; + } + + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { + cpu->has_el2 = true; + } + if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu = true; } @@ -1954,6 +1958,54 @@ static void arm_max_initfn(struct uc_struct *uc, CPUState *obj) /* old-style VFP short-vector support */ FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1, cpu->isar.mvfr0); + +// Unicorn: Enable this on ARM_MAX +//#ifdef CONFIG_USER_ONLY + /* We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; + + t = cpu->isar.id_isar5; + FIELD_DP32(t, ID_ISAR5, AES, 2, t); + FIELD_DP32(t, ID_ISAR5, SHA1, 1, t); + FIELD_DP32(t, ID_ISAR5, SHA2, 1, t); + FIELD_DP32(t, ID_ISAR5, CRC32, 1, t); + FIELD_DP32(t, ID_ISAR5, RDM, 1, t); + FIELD_DP32(t, ID_ISAR5, VCMA, 1, t); + cpu->isar.id_isar5 = t; + + t = cpu->isar.id_isar6; + FIELD_DP32(t, ID_ISAR6, JSCVT, 1, t); + FIELD_DP32(t, ID_ISAR6, DP, 1, t); + FIELD_DP32(t, ID_ISAR6, FHM, 1, t); + FIELD_DP32(t, ID_ISAR6, SB, 1, t); + FIELD_DP32(t, ID_ISAR6, SPECRES, 1, t); + cpu->isar.id_isar6 = t; + + t = cpu->isar.mvfr1; + FIELD_DP32(t, MVFR1, FPHP, 2, t); /* v8.0 FP support */ + cpu->isar.mvfr1 = t; + + t = cpu->isar.mvfr2; + FIELD_DP32(t, MVFR2, SIMDMISC, 3, t); /* SIMD MaxNum */ + FIELD_DP32(t, MVFR2, FPMISC, 4, t); /* FP MaxNum */ + cpu->isar.mvfr2 = t; + + t = cpu->isar.id_mmfr3; + FIELD_DP32(t, ID_MMFR3, PAN, 2, t); /* ATS1E1 */ + cpu->isar.id_mmfr3 = t; + + t = cpu->isar.id_mmfr4; + FIELD_DP32(t, ID_MMFR4, HPDS, 1, t); /* AA32HPD */ + FIELD_DP32(t, ID_MMFR4, AC2, 1, t); /* ACTLR2, HACTLR2 */ + FIELD_DP32(t, ID_MMFR4, CNP, 1, t); /* TTCNP */ + cpu->isar.id_mmfr4 = t; + } +//#endif } } #endif diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c index a91dc6d4..95a7ef25 100644 --- a/qemu/target/arm/cpu64.c +++ b/qemu/target/arm/cpu64.c @@ -361,17 +361,6 @@ ARMCPU *cpu_aarch64_init(struct uc_struct *uc) /* postinit ARMCPU */ arm_cpu_post_init(cs); - /* - * Unicorn: Hack to force to enable EL2/EL3 for aarch64 so that we can - * use the full 64bits virtual address space. - * - * While EL2/EL3 is enabled but running within EL1, we could - * get somewhat like "x86 flat mode", though aarch64 only allows - * a maximum of 52bits virtual address space. - */ - ARM_CPU(cs)->has_el2 = true; - ARM_CPU(cs)->has_el3 = true; - /* realize ARMCPU */ arm_cpu_realizefn(uc, cs); From c671efe79899e4f0242ecda46692a818525dc444 Mon Sep 17 00:00:00 2001 From: lazymio Date: Wed, 5 Jan 2022 22:00:59 +0100 Subject: [PATCH 16/18] Update bindings --- bindings/dotnet/UnicornManaged/Const/Arm.fs | 15 ++++++++------- bindings/go/unicorn/arm_const.go | 15 ++++++++------- bindings/java/unicorn/ArmConst.java | 15 ++++++++------- bindings/pascal/unicorn/ArmConst.pas | 15 ++++++++------- bindings/python/unicorn/arm_const.py | 15 ++++++++------- .../unicorn_gem/lib/unicorn_engine/arm_const.rb | 15 ++++++++------- 6 files changed, 48 insertions(+), 42 deletions(-) diff --git a/bindings/dotnet/UnicornManaged/Const/Arm.fs b/bindings/dotnet/UnicornManaged/Const/Arm.fs index a571722b..326b32db 100644 --- a/bindings/dotnet/UnicornManaged/Const/Arm.fs +++ b/bindings/dotnet/UnicornManaged/Const/Arm.fs @@ -35,13 +35,14 @@ module Arm = let UC_CPU_ARM_PXA260 = 23 let UC_CPU_ARM_PXA261 = 24 let UC_CPU_ARM_PXA262 = 25 - let UC_CPU_ARM_PXA270A0 = 26 - let UC_CPU_ARM_PXA270A1 = 27 - let UC_CPU_ARM_PXA270B0 = 28 - let UC_CPU_ARM_PXA270B1 = 29 - let UC_CPU_ARM_PXA270C0 = 30 - let UC_CPU_ARM_PXA270C5 = 31 - let UC_CPU_ARM_MAX = 32 + let UC_CPU_ARM_PXA270 = 26 + let UC_CPU_ARM_PXA270A0 = 27 + let UC_CPU_ARM_PXA270A1 = 28 + let UC_CPU_ARM_PXA270B0 = 29 + let UC_CPU_ARM_PXA270B1 = 30 + let UC_CPU_ARM_PXA270C0 = 31 + let UC_CPU_ARM_PXA270C5 = 32 + let UC_CPU_ARM_MAX = 33 // ARM registers diff --git a/bindings/go/unicorn/arm_const.go b/bindings/go/unicorn/arm_const.go index 87177e20..81eac268 100644 --- a/bindings/go/unicorn/arm_const.go +++ b/bindings/go/unicorn/arm_const.go @@ -30,13 +30,14 @@ const ( CPU_ARM_PXA260 = 23 CPU_ARM_PXA261 = 24 CPU_ARM_PXA262 = 25 - CPU_ARM_PXA270A0 = 26 - CPU_ARM_PXA270A1 = 27 - CPU_ARM_PXA270B0 = 28 - CPU_ARM_PXA270B1 = 29 - CPU_ARM_PXA270C0 = 30 - CPU_ARM_PXA270C5 = 31 - CPU_ARM_MAX = 32 + CPU_ARM_PXA270 = 26 + CPU_ARM_PXA270A0 = 27 + CPU_ARM_PXA270A1 = 28 + CPU_ARM_PXA270B0 = 29 + CPU_ARM_PXA270B1 = 30 + CPU_ARM_PXA270C0 = 31 + CPU_ARM_PXA270C5 = 32 + CPU_ARM_MAX = 33 // ARM registers diff --git a/bindings/java/unicorn/ArmConst.java b/bindings/java/unicorn/ArmConst.java index 7ae2d9fa..6524a8b3 100644 --- a/bindings/java/unicorn/ArmConst.java +++ b/bindings/java/unicorn/ArmConst.java @@ -32,13 +32,14 @@ public interface ArmConst { public static final int UC_CPU_ARM_PXA260 = 23; public static final int UC_CPU_ARM_PXA261 = 24; public static final int UC_CPU_ARM_PXA262 = 25; - public static final int UC_CPU_ARM_PXA270A0 = 26; - public static final int UC_CPU_ARM_PXA270A1 = 27; - public static final int UC_CPU_ARM_PXA270B0 = 28; - public static final int UC_CPU_ARM_PXA270B1 = 29; - public static final int UC_CPU_ARM_PXA270C0 = 30; - public static final int UC_CPU_ARM_PXA270C5 = 31; - public static final int UC_CPU_ARM_MAX = 32; + public static final int UC_CPU_ARM_PXA270 = 26; + public static final int UC_CPU_ARM_PXA270A0 = 27; + public static final int UC_CPU_ARM_PXA270A1 = 28; + public static final int UC_CPU_ARM_PXA270B0 = 29; + public static final int UC_CPU_ARM_PXA270B1 = 30; + public static final int UC_CPU_ARM_PXA270C0 = 31; + public static final int UC_CPU_ARM_PXA270C5 = 32; + public static final int UC_CPU_ARM_MAX = 33; // ARM registers diff --git a/bindings/pascal/unicorn/ArmConst.pas b/bindings/pascal/unicorn/ArmConst.pas index 32558aea..c62e9c6c 100644 --- a/bindings/pascal/unicorn/ArmConst.pas +++ b/bindings/pascal/unicorn/ArmConst.pas @@ -33,13 +33,14 @@ const UC_CPU_ARM_PXA260 = 23; UC_CPU_ARM_PXA261 = 24; UC_CPU_ARM_PXA262 = 25; - UC_CPU_ARM_PXA270A0 = 26; - UC_CPU_ARM_PXA270A1 = 27; - UC_CPU_ARM_PXA270B0 = 28; - UC_CPU_ARM_PXA270B1 = 29; - UC_CPU_ARM_PXA270C0 = 30; - UC_CPU_ARM_PXA270C5 = 31; - UC_CPU_ARM_MAX = 32; + UC_CPU_ARM_PXA270 = 26; + UC_CPU_ARM_PXA270A0 = 27; + UC_CPU_ARM_PXA270A1 = 28; + UC_CPU_ARM_PXA270B0 = 29; + UC_CPU_ARM_PXA270B1 = 30; + UC_CPU_ARM_PXA270C0 = 31; + UC_CPU_ARM_PXA270C5 = 32; + UC_CPU_ARM_MAX = 33; // ARM registers diff --git a/bindings/python/unicorn/arm_const.py b/bindings/python/unicorn/arm_const.py index 36fac155..be63377c 100644 --- a/bindings/python/unicorn/arm_const.py +++ b/bindings/python/unicorn/arm_const.py @@ -28,13 +28,14 @@ UC_CPU_ARM_PXA255 = 22 UC_CPU_ARM_PXA260 = 23 UC_CPU_ARM_PXA261 = 24 UC_CPU_ARM_PXA262 = 25 -UC_CPU_ARM_PXA270A0 = 26 -UC_CPU_ARM_PXA270A1 = 27 -UC_CPU_ARM_PXA270B0 = 28 -UC_CPU_ARM_PXA270B1 = 29 -UC_CPU_ARM_PXA270C0 = 30 -UC_CPU_ARM_PXA270C5 = 31 -UC_CPU_ARM_MAX = 32 +UC_CPU_ARM_PXA270 = 26 +UC_CPU_ARM_PXA270A0 = 27 +UC_CPU_ARM_PXA270A1 = 28 +UC_CPU_ARM_PXA270B0 = 29 +UC_CPU_ARM_PXA270B1 = 30 +UC_CPU_ARM_PXA270C0 = 31 +UC_CPU_ARM_PXA270C5 = 32 +UC_CPU_ARM_MAX = 33 # ARM registers diff --git a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb index c0e5b049..232e0161 100644 --- a/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb +++ b/bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb @@ -30,13 +30,14 @@ module UnicornEngine UC_CPU_ARM_PXA260 = 23 UC_CPU_ARM_PXA261 = 24 UC_CPU_ARM_PXA262 = 25 - UC_CPU_ARM_PXA270A0 = 26 - UC_CPU_ARM_PXA270A1 = 27 - UC_CPU_ARM_PXA270B0 = 28 - UC_CPU_ARM_PXA270B1 = 29 - UC_CPU_ARM_PXA270C0 = 30 - UC_CPU_ARM_PXA270C5 = 31 - UC_CPU_ARM_MAX = 32 + UC_CPU_ARM_PXA270 = 26 + UC_CPU_ARM_PXA270A0 = 27 + UC_CPU_ARM_PXA270A1 = 28 + UC_CPU_ARM_PXA270B0 = 29 + UC_CPU_ARM_PXA270B1 = 30 + UC_CPU_ARM_PXA270C0 = 31 + UC_CPU_ARM_PXA270C5 = 32 + UC_CPU_ARM_MAX = 33 # ARM registers From be7fbf13061734fe0682de9dfe8b959e545044e6 Mon Sep 17 00:00:00 2001 From: lazymio Date: Sat, 8 Jan 2022 22:10:17 +0100 Subject: [PATCH 17/18] Handle CPU fault when invalidating TB cache --- qemu/accel/tcg/translate-all.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/qemu/accel/tcg/translate-all.c b/qemu/accel/tcg/translate-all.c index c0488ca9..e48670eb 100644 --- a/qemu/accel/tcg/translate-all.c +++ b/qemu/accel/tcg/translate-all.c @@ -985,11 +985,22 @@ static void uc_invalidate_tb(struct uc_struct *uc, uint64_t start_addr, size_t l { tb_page_addr_t start, end; - // GVA to GPA + uc->nested_level++; + if (sigsetjmp(uc->jmp_bufs[uc->nested_level - 1], 0) != 0) { + // We a get cpu fault in get_page_addr_code, ignore it. + uc->nested_level--; + return; + } + + // GPA to GVA + // start_addr : GPA + // addr: GVA // (GPA -> HVA via memory_region_get_ram_addr(mr) + GPA + block->host, // HVA->HPA via host mmu) start = get_page_addr_code(uc->cpu->env_ptr, start_addr) & (target_ulong)(-1); - + + uc->nested_level--; + // For 32bit target. end = (start + len) & (target_ulong)(-1); From 36afa1022c6cd482d7ff6e6afad800d2513e0c95 Mon Sep 17 00:00:00 2001 From: lazymio Date: Mon, 10 Jan 2022 15:16:10 +0100 Subject: [PATCH 18/18] More PPC registers Add FPR0-31, CR0-7, LR, CTR, MSR, XER, FPSCR for PPC Add a test for ppc32 float point --- include/unicorn/ppc.h | 48 +++++++ qemu/target/ppc/translate_init.inc.c | 2 + qemu/target/ppc/unicorn.c | 192 +++++++++++++++++++++++++-- tests/unit/test_ppc.c | 33 ++++- 4 files changed, 262 insertions(+), 13 deletions(-) diff --git a/include/unicorn/ppc.h b/include/unicorn/ppc.h index 14a20498..5705ffff 100644 --- a/include/unicorn/ppc.h +++ b/include/unicorn/ppc.h @@ -370,6 +370,54 @@ typedef enum uc_ppc_reg { UC_PPC_REG_29, UC_PPC_REG_30, UC_PPC_REG_31, + + UC_PPC_REG_CR0, + UC_PPC_REG_CR1, + UC_PPC_REG_CR2, + UC_PPC_REG_CR3, + UC_PPC_REG_CR4, + UC_PPC_REG_CR5, + UC_PPC_REG_CR6, + UC_PPC_REG_CR7, + + UC_PPC_REG_FPR0, + UC_PPC_REG_FPR1, + UC_PPC_REG_FPR2, + UC_PPC_REG_FPR3, + UC_PPC_REG_FPR4, + UC_PPC_REG_FPR5, + UC_PPC_REG_FPR6, + UC_PPC_REG_FPR7, + UC_PPC_REG_FPR8, + UC_PPC_REG_FPR9, + UC_PPC_REG_FPR10, + UC_PPC_REG_FPR11, + UC_PPC_REG_FPR12, + UC_PPC_REG_FPR13, + UC_PPC_REG_FPR14, + UC_PPC_REG_FPR15, + UC_PPC_REG_FPR16, + UC_PPC_REG_FPR17, + UC_PPC_REG_FPR18, + UC_PPC_REG_FPR19, + UC_PPC_REG_FPR20, + UC_PPC_REG_FPR21, + UC_PPC_REG_FPR22, + UC_PPC_REG_FPR23, + UC_PPC_REG_FPR24, + UC_PPC_REG_FPR25, + UC_PPC_REG_FPR26, + UC_PPC_REG_FPR27, + UC_PPC_REG_FPR28, + UC_PPC_REG_FPR29, + UC_PPC_REG_FPR30, + UC_PPC_REG_FPR31, + + UC_PPC_REG_LR, + UC_PPC_REG_XER, + UC_PPC_REG_CTR, + UC_PPC_REG_MSR, + UC_PPC_REG_FPSCR } uc_ppc_reg; #ifdef __cplusplus diff --git a/qemu/target/ppc/translate_init.inc.c b/qemu/target/ppc/translate_init.inc.c index 65956ad1..920ea602 100644 --- a/qemu/target/ppc/translate_init.inc.c +++ b/qemu/target/ppc/translate_init.inc.c @@ -11196,5 +11196,7 @@ PowerPCCPU *cpu_ppc_init(struct uc_struct *uc) qemu_init_vcpu(cs); + ppc_cpu_reset((CPUState *)cpu); + return cpu; } diff --git a/qemu/target/ppc/unicorn.c b/qemu/target/ppc/unicorn.c index d8d50d57..52737f76 100644 --- a/qemu/target/ppc/unicorn.c +++ b/qemu/target/ppc/unicorn.c @@ -9,6 +9,8 @@ #include "unicorn_common.h" #include "uc_priv.h" #include "unicorn.h" +#include "helper_regs.h" +#include "cpu.h" #ifdef TARGET_PPC64 typedef uint64_t ppcreg_t; @@ -16,6 +18,65 @@ typedef uint64_t ppcreg_t; typedef uint32_t ppcreg_t; #endif +// Unicorn version to ensure writing MSR without exception +static inline int uc_ppc_store_msr(CPUPPCState *env, target_ulong value, + int alter_hv) +{ + // int excp; + // CPUState *cs = env_cpu(env); + + // excp = 0; + value &= env->msr_mask; + + /* Neither mtmsr nor guest state can alter HV */ + if (!alter_hv || !(env->msr & MSR_HVB)) { + value &= ~MSR_HVB; + value |= env->msr & MSR_HVB; + } + if (((value >> MSR_IR) & 1) != msr_ir || + ((value >> MSR_DR) & 1) != msr_dr) { + // cpu_interrupt_exittb(cs); + } + if ((env->mmu_model & POWERPC_MMU_BOOKE) && + ((value >> MSR_GS) & 1) != msr_gs) { + // cpu_interrupt_exittb(cs); + } + if (unlikely((env->flags & POWERPC_FLAG_TGPR) && + ((value ^ env->msr) & (1 << MSR_TGPR)))) { + /* Swap temporary saved registers with GPRs */ + hreg_swap_gpr_tgpr(env); + } + if (unlikely((value >> MSR_EP) & 1) != msr_ep) { + /* Change the exception prefix on PowerPC 601 */ + env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; + } + /* + * If PR=1 then EE, IR and DR must be 1 + * + * Note: We only enforce this on 64-bit server processors. + * It appears that: + * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS + * exploits it. + * - 64-bit embedded implementations do not need any operation to be + * performed when PR is set. + */ + if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { + value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); + } + + env->msr = value; + hreg_compute_hflags(env); + + // if (unlikely(msr_pow == 1)) { + // if (!env->pending_interrupts && (*env->check_pow)(env)) { + // cs->halted = 1; + // excp = EXCP_HALTED; + // } + // } + + return 0; +} + static uint64_t ppc_mem_redirect(uint64_t address) { /* // kseg0 range masks off high address bit @@ -79,6 +140,7 @@ void ppc_reg_reset(struct uc_struct *uc) env->nip = 0; } +// http://www.csit-sun.pub.ro/~cpop/Documentatie_SMP/Motorola_PowerPC/PowerPc/GenInfo/pemch2.pdf static void reg_read(CPUPPCState *env, unsigned int regid, void *value) { if (regid >= UC_PPC_REG_0 && regid <= UC_PPC_REG_31) @@ -90,12 +152,65 @@ static void reg_read(CPUPPCState *env, unsigned int regid, void *value) case UC_PPC_REG_PC: *(ppcreg_t *)value = env->nip; break; - /* case UC_PPC_REG_CP0_CONFIG3: - *(mipsreg_t *)value = env->CP0_Config3; - break; - case UC_MIPS_REG_CP0_USERLOCAL: - *(mipsreg_t *)value = env->active_tc.CP0_UserLocal; - break; */ + case UC_PPC_REG_FPR0: + case UC_PPC_REG_FPR1: + case UC_PPC_REG_FPR2: + case UC_PPC_REG_FPR3: + case UC_PPC_REG_FPR4: + case UC_PPC_REG_FPR5: + case UC_PPC_REG_FPR6: + case UC_PPC_REG_FPR7: + case UC_PPC_REG_FPR8: + case UC_PPC_REG_FPR9: + case UC_PPC_REG_FPR10: + case UC_PPC_REG_FPR11: + case UC_PPC_REG_FPR12: + case UC_PPC_REG_FPR13: + case UC_PPC_REG_FPR14: + case UC_PPC_REG_FPR15: + case UC_PPC_REG_FPR16: + case UC_PPC_REG_FPR17: + case UC_PPC_REG_FPR18: + case UC_PPC_REG_FPR19: + case UC_PPC_REG_FPR20: + case UC_PPC_REG_FPR21: + case UC_PPC_REG_FPR22: + case UC_PPC_REG_FPR23: + case UC_PPC_REG_FPR24: + case UC_PPC_REG_FPR25: + case UC_PPC_REG_FPR26: + case UC_PPC_REG_FPR27: + case UC_PPC_REG_FPR28: + case UC_PPC_REG_FPR29: + case UC_PPC_REG_FPR30: + case UC_PPC_REG_FPR31: + *(uint64_t *)value = env->vsr[regid - UC_PPC_REG_FPR0].VsrD(0); + break; + case UC_PPC_REG_CR0: + case UC_PPC_REG_CR1: + case UC_PPC_REG_CR2: + case UC_PPC_REG_CR3: + case UC_PPC_REG_CR4: + case UC_PPC_REG_CR5: + case UC_PPC_REG_CR6: + case UC_PPC_REG_CR7: + *(uint32_t *)value = env->crf[regid - UC_PPC_REG_CR0]; + break; + case UC_PPC_REG_LR: + *(ppcreg_t *)value = env->lr; + break; + case UC_PPC_REG_CTR: + *(ppcreg_t *)value = env->ctr; + break; + case UC_PPC_REG_MSR: + *(ppcreg_t *)value = env->msr; + break; + case UC_PPC_REG_XER: + *(uint32_t *)value = env->xer; + break; + case UC_PPC_REG_FPSCR: + *(uint32_t *)value = env->fpscr; + break; } } @@ -113,12 +228,65 @@ static void reg_write(CPUPPCState *env, unsigned int regid, const void *value) case UC_PPC_REG_PC: env->nip = *(ppcreg_t *)value; break; - /* case UC_MIPS_REG_CP0_CONFIG3: - env->CP0_Config3 = *(mipsreg_t *)value; - break; - case UC_MIPS_REG_CP0_USERLOCAL: - env->active_tc.CP0_UserLocal = *(mipsreg_t *)value; - break; */ + case UC_PPC_REG_FPR0: + case UC_PPC_REG_FPR1: + case UC_PPC_REG_FPR2: + case UC_PPC_REG_FPR3: + case UC_PPC_REG_FPR4: + case UC_PPC_REG_FPR5: + case UC_PPC_REG_FPR6: + case UC_PPC_REG_FPR7: + case UC_PPC_REG_FPR8: + case UC_PPC_REG_FPR9: + case UC_PPC_REG_FPR10: + case UC_PPC_REG_FPR11: + case UC_PPC_REG_FPR12: + case UC_PPC_REG_FPR13: + case UC_PPC_REG_FPR14: + case UC_PPC_REG_FPR15: + case UC_PPC_REG_FPR16: + case UC_PPC_REG_FPR17: + case UC_PPC_REG_FPR18: + case UC_PPC_REG_FPR19: + case UC_PPC_REG_FPR20: + case UC_PPC_REG_FPR21: + case UC_PPC_REG_FPR22: + case UC_PPC_REG_FPR23: + case UC_PPC_REG_FPR24: + case UC_PPC_REG_FPR25: + case UC_PPC_REG_FPR26: + case UC_PPC_REG_FPR27: + case UC_PPC_REG_FPR28: + case UC_PPC_REG_FPR29: + case UC_PPC_REG_FPR30: + case UC_PPC_REG_FPR31: + env->vsr[regid - UC_PPC_REG_FPR0].VsrD(0) = *(uint64_t *)value; + break; + case UC_PPC_REG_CR0: + case UC_PPC_REG_CR1: + case UC_PPC_REG_CR2: + case UC_PPC_REG_CR3: + case UC_PPC_REG_CR4: + case UC_PPC_REG_CR5: + case UC_PPC_REG_CR6: + case UC_PPC_REG_CR7: + env->crf[regid - UC_PPC_REG_CR0] = *(uint32_t *)value; + break; + case UC_PPC_REG_LR: + env->lr = *(ppcreg_t *)value; + break; + case UC_PPC_REG_CTR: + env->ctr = *(ppcreg_t *)value; + break; + case UC_PPC_REG_MSR: + uc_ppc_store_msr(env, *(ppcreg_t *)value, 0); + break; + case UC_PPC_REG_XER: + env->xer = *(uint32_t *)value; + break; + case UC_PPC_REG_FPSCR: + store_fpscr(env, *(uint32_t *)value, 0xffffffff); + break; } } diff --git a/tests/unit/test_ppc.c b/tests/unit/test_ppc.c index 41fed7c4..21ba64fa 100644 --- a/tests/unit/test_ppc.c +++ b/tests/unit/test_ppc.c @@ -34,4 +34,35 @@ static void test_ppc32_add() OK(uc_close(uc)); } -TEST_LIST = {{"test_ppc32_add", test_ppc32_add}, {NULL, NULL}}; \ No newline at end of file +// https://www.ibm.com/docs/en/aix/7.2?topic=set-fadd-fa-floating-add-instruction +static void test_ppc32_fadd() +{ + uc_engine *uc; + char code[] = "\xfc\xc4\x28\x2a"; // fadd 6, 4, 5 + uint32_t r_msr; + uint64_t r_fpr4, r_fpr5, r_fpr6; + + uc_common_setup(&uc, UC_ARCH_PPC, UC_MODE_32 | UC_MODE_BIG_ENDIAN, code, + sizeof(code) - 1); + + OK(uc_reg_read(uc, UC_PPC_REG_MSR, &r_msr)); + r_msr |= (1 << 13); // Big endian + OK(uc_reg_write(uc, UC_PPC_REG_MSR, &r_msr)); // enable FP + + r_fpr4 = 0xC053400000000000ul; + r_fpr5 = 0x400C000000000000ul; + OK(uc_reg_write(uc, UC_PPC_REG_FPR4, &r_fpr4)); + OK(uc_reg_write(uc, UC_PPC_REG_FPR5, &r_fpr5)); + + OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0)); + + OK(uc_reg_read(uc, UC_PPC_REG_FPR6, &r_fpr6)); + + TEST_CHECK(r_fpr6 == 0xC052600000000000ul); + + OK(uc_close(uc)); +} + +TEST_LIST = {{"test_ppc32_add", test_ppc32_add}, + {"test_ppc32_fadd", test_ppc32_fadd}, + {NULL, NULL}}; \ No newline at end of file