diff --git a/msvc/msvc.sln b/msvc/msvc.sln deleted file mode 100644 index de130302..00000000 --- a/msvc/msvc.sln +++ /dev/null @@ -1,124 +0,0 @@ - -Microsoft Visual Studio Solution File, Format Version 12.00 -# Visual Studio 2012 -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "x86_64-softmmu", "unicorn\x86_64-softmmu\x86_64-softmmu.vcxproj", "{17077E86-AE7C-41AF-86ED-2BAC03B019BC}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "unicorn", "unicorn\unicorn\unicorn.vcxproj", "{B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}" - ProjectSection(ProjectDependencies) = postProject - {17077E86-AE7C-41AF-86ED-2BAC03B019BC} = {17077E86-AE7C-41AF-86ED-2BAC03B019BC} - EndProjectSection -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_x86", "samples\sample_x86\sample_x86.vcxproj", "{F8053D66-8267-433A-BF2C-E07E2298C338}" - ProjectSection(ProjectDependencies) = postProject - {17077E86-AE7C-41AF-86ED-2BAC03B019BC} = {17077E86-AE7C-41AF-86ED-2BAC03B019BC} - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} - EndProjectSection -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "aarch64-softmmu", "unicorn\aarch64-softmmu\aarch64-softmmu.vcxproj", "{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "arm-softmmu", "unicorn\arm-softmmu\arm-softmmu.vcxproj", "{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "m68k-softmmu", "unicorn\m68k-softmmu\m68k-softmmu.vcxproj", "{2C5AD347-6E34-463B-8289-00578E43B255}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips-softmmu", "unicorn\mips-softmmu\mips-softmmu.vcxproj", "{63050112-E486-4396-B5E4-303C3BC12D39}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips64-softmmu", "unicorn\mips64-softmmu\mips64-softmmu.vcxproj", "{4A9F9353-DB63-460A-BB1C-9CB519DFD414}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips64el-softmmu", "unicorn\mips64el-softmmu\mips64el-softmmu.vcxproj", "{4478909E-6983-425C-9D9F-558CF258E61E}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mipsel-softmmu", "unicorn\mipsel-softmmu\mipsel-softmmu.vcxproj", "{006A7908-ABF3-4D18-BC35-0A29E39B95F9}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sparc-softmmu", "unicorn\sparc-softmmu\sparc-softmmu.vcxproj", "{698C2D54-475C-446F-B879-F629BBEF75FE}" -EndProject -Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sparc64-softmmu", "unicorn\sparc64-softmmu\sparc64-softmmu.vcxproj", "{8804AD29-E398-480C-AC0F-98EC1B7A51CB}" -EndProject -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "softmmu", "softmmu", "{857A09AF-FE20-461C-B66F-D779422AD46B}" -EndProject -Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "samples", "samples", "{F8E85E25-4D67-4A6B-A976-C920790B8798}" -EndProject -Global - GlobalSection(SolutionConfigurationPlatforms) = preSolution - Debug|Win32 = Debug|Win32 - Debug|x64 = Debug|x64 - Release|Win32 = Release|Win32 - Release|x64 = Release|x64 - EndGlobalSection - GlobalSection(ProjectConfigurationPlatforms) = postSolution - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.ActiveCfg = Debug|Win32 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.Build.0 = Debug|Win32 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|x64.ActiveCfg = Debug|x64 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|x64.Build.0 = Debug|x64 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.ActiveCfg = Release|Win32 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.Build.0 = Release|Win32 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|x64.ActiveCfg = Release|x64 - {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|x64.Build.0 = Release|x64 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.ActiveCfg = Debug|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.Build.0 = Debug|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|x64.ActiveCfg = Debug|x64 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|x64.Build.0 = Debug|x64 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.ActiveCfg = Release|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.Build.0 = Release|Win32 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|x64.ActiveCfg = Release|x64 - {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|x64.Build.0 = Release|x64 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|Win32.ActiveCfg = Debug|Win32 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|Win32.Build.0 = Debug|Win32 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|x64.ActiveCfg = Debug|x64 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|x64.Build.0 = Debug|x64 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|Win32.ActiveCfg = Release|Win32 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|Win32.Build.0 = Release|Win32 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.ActiveCfg = Release|x64 - {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.Build.0 = Release|x64 - {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.ActiveCfg = Debug|Win32 - {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.ActiveCfg = Debug|x64 - {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.ActiveCfg = Release|Win32 - {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.ActiveCfg = Release|x64 - {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.ActiveCfg = Debug|Win32 - {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.ActiveCfg = Debug|x64 - {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.ActiveCfg = Release|Win32 - {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.ActiveCfg = Release|x64 - {2C5AD347-6E34-463B-8289-00578E43B255}.Debug|Win32.ActiveCfg = Debug|Win32 - {2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.ActiveCfg = Debug|x64 - {2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.ActiveCfg = Release|Win32 - {2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.ActiveCfg = Release|x64 - {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.ActiveCfg = Debug|Win32 - {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.ActiveCfg = Debug|x64 - {63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.ActiveCfg = Release|Win32 - {63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.ActiveCfg = Release|x64 - {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.ActiveCfg = Debug|Win32 - {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.ActiveCfg = Debug|x64 - {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.ActiveCfg = Release|Win32 - {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.ActiveCfg = Release|x64 - {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.ActiveCfg = Debug|Win32 - {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.ActiveCfg = Debug|x64 - {4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.ActiveCfg = Release|Win32 - {4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.ActiveCfg = Release|x64 - {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|Win32.ActiveCfg = Debug|Win32 - {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.ActiveCfg = Debug|x64 - {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.ActiveCfg = Release|Win32 - {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.ActiveCfg = Release|x64 - {698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|Win32.ActiveCfg = Debug|Win32 - {698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.ActiveCfg = Debug|x64 - {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.ActiveCfg = Release|Win32 - {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.ActiveCfg = Release|x64 - {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|Win32.ActiveCfg = Debug|Win32 - {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.ActiveCfg = Debug|x64 - {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.ActiveCfg = Release|Win32 - {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.ActiveCfg = Release|x64 - EndGlobalSection - GlobalSection(SolutionProperties) = preSolution - HideSolutionNode = FALSE - EndGlobalSection - GlobalSection(NestedProjects) = preSolution - {2A7F483F-CD19-4F84-BBDA-B6A1865E2773} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {F67EB1EA-DCFA-4758-A2AA-4B570BA78036} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {2C5AD347-6E34-463B-8289-00578E43B255} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {63050112-E486-4396-B5E4-303C3BC12D39} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {4A9F9353-DB63-460A-BB1C-9CB519DFD414} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {4478909E-6983-425C-9D9F-558CF258E61E} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {006A7908-ABF3-4D18-BC35-0A29E39B95F9} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {698C2D54-475C-446F-B879-F629BBEF75FE} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {8804AD29-E398-480C-AC0F-98EC1B7A51CB} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {17077E86-AE7C-41AF-86ED-2BAC03B019BC} = {857A09AF-FE20-461C-B66F-D779422AD46B} - {F8053D66-8267-433A-BF2C-E07E2298C338} = {F8E85E25-4D67-4A6B-A976-C920790B8798} - EndGlobalSection -EndGlobal diff --git a/msvc/readme.txt b/msvc/readme.txt index 8cc58614..9630c541 100644 --- a/msvc/readme.txt +++ b/msvc/readme.txt @@ -1,5 +1,9 @@ + +TODO: fix mips translate.c file where case OPC_DALIGN ... OPC_DALIGN_END: has many in between cases!!! + + *** TODO: this file needs work *** diff --git a/msvc/samples/mem_apis/mem_apis.vcxproj b/msvc/samples/mem_apis/mem_apis.vcxproj new file mode 100644 index 00000000..991123e5 --- /dev/null +++ b/msvc/samples/mem_apis/mem_apis.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {9D588288-5A28-4AB3-96EA-442CAA508F8E} + Win32Proj + mem_apis + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/mem_apis/mem_apis.vcxproj.filters b/msvc/samples/mem_apis/mem_apis.vcxproj.filters new file mode 100644 index 00000000..570aef12 --- /dev/null +++ b/msvc/samples/mem_apis/mem_apis.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_arm/sample_arm.vcxproj b/msvc/samples/sample_arm/sample_arm.vcxproj new file mode 100644 index 00000000..bfad03ba --- /dev/null +++ b/msvc/samples/sample_arm/sample_arm.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {9F32C692-9106-43AF-A291-779A2D8BE096} + Win32Proj + sample_arm + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_arm/sample_arm.vcxproj.filters b/msvc/samples/sample_arm/sample_arm.vcxproj.filters new file mode 100644 index 00000000..76c03db8 --- /dev/null +++ b/msvc/samples/sample_arm/sample_arm.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_arm64/sample_arm64.vcxproj b/msvc/samples/sample_arm64/sample_arm64.vcxproj new file mode 100644 index 00000000..38e04b36 --- /dev/null +++ b/msvc/samples/sample_arm64/sample_arm64.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B} + Win32Proj + sample_arm64 + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_arm64/sample_arm64.vcxproj.filters b/msvc/samples/sample_arm64/sample_arm64.vcxproj.filters new file mode 100644 index 00000000..1be43ac5 --- /dev/null +++ b/msvc/samples/sample_arm64/sample_arm64.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj b/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj new file mode 100644 index 00000000..73e171ee --- /dev/null +++ b/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {7AA02EDF-D797-494B-929C-F628F4E4EA62} + Win32Proj + sample_batch_reg + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj.filters b/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj.filters new file mode 100644 index 00000000..098f8333 --- /dev/null +++ b/msvc/samples/sample_batch_reg/sample_batch_reg.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_m68k/sample_m68k.vcxproj b/msvc/samples/sample_m68k/sample_m68k.vcxproj new file mode 100644 index 00000000..35a49fa0 --- /dev/null +++ b/msvc/samples/sample_m68k/sample_m68k.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + {11727C54-463F-472A-88AF-6C3D6071BF0B} + Win32Proj + sample_m68k + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_m68k/sample_m68k.vcxproj.filters b/msvc/samples/sample_m68k/sample_m68k.vcxproj.filters new file mode 100644 index 00000000..033b3c0e --- /dev/null +++ b/msvc/samples/sample_m68k/sample_m68k.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_mips/sample_mips.vcxproj b/msvc/samples/sample_mips/sample_mips.vcxproj new file mode 100644 index 00000000..474710bf --- /dev/null +++ b/msvc/samples/sample_mips/sample_mips.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD} + Win32Proj + sample_mips + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_mips/sample_mips.vcxproj.filters b/msvc/samples/sample_mips/sample_mips.vcxproj.filters new file mode 100644 index 00000000..95514576 --- /dev/null +++ b/msvc/samples/sample_mips/sample_mips.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_sparc/sample_sparc.vcxproj b/msvc/samples/sample_sparc/sample_sparc.vcxproj new file mode 100644 index 00000000..3e5dc384 --- /dev/null +++ b/msvc/samples/sample_sparc/sample_sparc.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {A25CA34D-2F64-442B-A5D3-B13CB56C9957} + Win32Proj + sample_sparc + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_sparc/sample_sparc.vcxproj.filters b/msvc/samples/sample_sparc/sample_sparc.vcxproj.filters new file mode 100644 index 00000000..306de23f --- /dev/null +++ b/msvc/samples/sample_sparc/sample_sparc.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj b/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj new file mode 100644 index 00000000..3f3cd866 --- /dev/null +++ b/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + {9D96D09A-DE17-4011-9247-F0009E8D6DB5} + Win32Proj + sample_x86_32_gdt_and_seg_regs + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + + + \ No newline at end of file diff --git a/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj.filters b/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj.filters new file mode 100644 index 00000000..960616db --- /dev/null +++ b/msvc/samples/sample_x86_32_gdt_and_seg_regs/sample_x86_32_gdt_and_seg_regs.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/samples/shellcode/shellcode.vcxproj b/msvc/samples/shellcode/shellcode.vcxproj new file mode 100644 index 00000000..1c72b06c --- /dev/null +++ b/msvc/samples/shellcode/shellcode.vcxproj @@ -0,0 +1,169 @@ + + + + + Debug + Win32 + + + Debug + x64 + + + Release + Win32 + + + Release + x64 + + + + + + + {F113B460-4B21-4014-9A15-D472FAA9E3F9} + Win32Proj + shellcode + + + + Application + true + v110_xp + MultiByte + + + Application + true + v110_xp + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + Application + false + v110_xp + true + MultiByte + + + + + + + + + + + + + + + + + + + true + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + true + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(SolutionDir)$(Platform)\$(Configuration)\ + $(ProjectDir)$(Platform)\$(Configuration)\ + + + false + $(ProjectDir)$(Platform)\$(Configuration)\ + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + + Level3 + Disabled + WIN32;_DEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreadedDebug + + + Console + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + Level3 + + + MaxSpeed + true + true + WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;__i386__ + ../../../include + false + MultiThreaded + + + Console + true + true + true + $(SolutionDir)$(Platform)\$(Configuration)\ + + + + + + \ No newline at end of file diff --git a/msvc/samples/shellcode/shellcode.vcxproj.filters b/msvc/samples/shellcode/shellcode.vcxproj.filters new file mode 100644 index 00000000..1f571b64 --- /dev/null +++ b/msvc/samples/shellcode/shellcode.vcxproj.filters @@ -0,0 +1,6 @@ + + + + + + \ No newline at end of file diff --git a/msvc/unicorn.sln b/msvc/unicorn.sln new file mode 100644 index 00000000..778f73ec --- /dev/null +++ b/msvc/unicorn.sln @@ -0,0 +1,245 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Visual Studio 2012 +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "x86_64-softmmu", "unicorn\x86_64-softmmu\x86_64-softmmu.vcxproj", "{17077E86-AE7C-41AF-86ED-2BAC03B019BC}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "unicorn", "unicorn\unicorn\unicorn.vcxproj", "{B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}" + ProjectSection(ProjectDependencies) = postProject + {006A7908-ABF3-4D18-BC35-0A29E39B95F9} = {006A7908-ABF3-4D18-BC35-0A29E39B95F9} + {63050112-E486-4396-B5E4-303C3BC12D39} = {63050112-E486-4396-B5E4-303C3BC12D39} + {8804AD29-E398-480C-AC0F-98EC1B7A51CB} = {8804AD29-E398-480C-AC0F-98EC1B7A51CB} + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773} = {2A7F483F-CD19-4F84-BBDA-B6A1865E2773} + {2C5AD347-6E34-463B-8289-00578E43B255} = {2C5AD347-6E34-463B-8289-00578E43B255} + {4A9F9353-DB63-460A-BB1C-9CB519DFD414} = {4A9F9353-DB63-460A-BB1C-9CB519DFD414} + {698C2D54-475C-446F-B879-F629BBEF75FE} = {698C2D54-475C-446F-B879-F629BBEF75FE} + {17077E86-AE7C-41AF-86ED-2BAC03B019BC} = {17077E86-AE7C-41AF-86ED-2BAC03B019BC} + {4478909E-6983-425C-9D9F-558CF258E61E} = {4478909E-6983-425C-9D9F-558CF258E61E} + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036} = {F67EB1EA-DCFA-4758-A2AA-4B570BA78036} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_x86", "samples\sample_x86\sample_x86.vcxproj", "{F8053D66-8267-433A-BF2C-E07E2298C338}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "aarch64-softmmu", "unicorn\aarch64-softmmu\aarch64-softmmu.vcxproj", "{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "arm-softmmu", "unicorn\arm-softmmu\arm-softmmu.vcxproj", "{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "m68k-softmmu", "unicorn\m68k-softmmu\m68k-softmmu.vcxproj", "{2C5AD347-6E34-463B-8289-00578E43B255}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips-softmmu", "unicorn\mips-softmmu\mips-softmmu.vcxproj", "{63050112-E486-4396-B5E4-303C3BC12D39}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips64-softmmu", "unicorn\mips64-softmmu\mips64-softmmu.vcxproj", "{4A9F9353-DB63-460A-BB1C-9CB519DFD414}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mips64el-softmmu", "unicorn\mips64el-softmmu\mips64el-softmmu.vcxproj", "{4478909E-6983-425C-9D9F-558CF258E61E}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mipsel-softmmu", "unicorn\mipsel-softmmu\mipsel-softmmu.vcxproj", "{006A7908-ABF3-4D18-BC35-0A29E39B95F9}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sparc-softmmu", "unicorn\sparc-softmmu\sparc-softmmu.vcxproj", "{698C2D54-475C-446F-B879-F629BBEF75FE}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sparc64-softmmu", "unicorn\sparc64-softmmu\sparc64-softmmu.vcxproj", "{8804AD29-E398-480C-AC0F-98EC1B7A51CB}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "softmmu", "softmmu", "{857A09AF-FE20-461C-B66F-D779422AD46B}" +EndProject +Project("{2150E333-8FDC-42A3-9474-1A3956D46DE8}") = "samples", "samples", "{F8E85E25-4D67-4A6B-A976-C920790B8798}" +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_arm", "samples\sample_arm\sample_arm.vcxproj", "{9F32C692-9106-43AF-A291-779A2D8BE096}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "mem_apis", "samples\mem_apis\mem_apis.vcxproj", "{9D588288-5A28-4AB3-96EA-442CAA508F8E}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_arm64", "samples\sample_arm64\sample_arm64.vcxproj", "{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_batch_reg", "samples\sample_batch_reg\sample_batch_reg.vcxproj", "{7AA02EDF-D797-494B-929C-F628F4E4EA62}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_m68k", "samples\sample_m68k\sample_m68k.vcxproj", "{11727C54-463F-472A-88AF-6C3D6071BF0B}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_mips", "samples\sample_mips\sample_mips.vcxproj", "{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_sparc", "samples\sample_sparc\sample_sparc.vcxproj", "{A25CA34D-2F64-442B-A5D3-B13CB56C9957}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "sample_x86_32_gdt_and_seg_regs", "samples\sample_x86_32_gdt_and_seg_regs\sample_x86_32_gdt_and_seg_regs.vcxproj", "{9D96D09A-DE17-4011-9247-F0009E8D6DB5}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "shellcode", "samples\shellcode\shellcode.vcxproj", "{F113B460-4B21-4014-9A15-D472FAA9E3F9}" + ProjectSection(ProjectDependencies) = postProject + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} = {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96} + EndProjectSection +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|Win32 = Debug|Win32 + Debug|x64 = Debug|x64 + Release|Win32 = Release|Win32 + Release|x64 = Release|x64 + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.ActiveCfg = Debug|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|Win32.Build.0 = Debug|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|x64.ActiveCfg = Debug|x64 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Debug|x64.Build.0 = Debug|x64 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.ActiveCfg = Release|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|Win32.Build.0 = Release|Win32 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|x64.ActiveCfg = Release|x64 + {17077E86-AE7C-41AF-86ED-2BAC03B019BC}.Release|x64.Build.0 = Release|x64 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.ActiveCfg = Debug|Win32 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|Win32.Build.0 = Debug|Win32 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|x64.ActiveCfg = Debug|x64 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Debug|x64.Build.0 = Debug|x64 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.ActiveCfg = Release|Win32 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|Win32.Build.0 = Release|Win32 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|x64.ActiveCfg = Release|x64 + {B6EFD6D7-C2D4-4FBB-B363-2E08CE09CC96}.Release|x64.Build.0 = Release|x64 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|Win32.ActiveCfg = Debug|Win32 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|Win32.Build.0 = Debug|Win32 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|x64.ActiveCfg = Debug|x64 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Debug|x64.Build.0 = Debug|x64 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|Win32.ActiveCfg = Release|Win32 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|Win32.Build.0 = Release|Win32 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.ActiveCfg = Release|x64 + {F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.Build.0 = Release|x64 + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.ActiveCfg = Debug|Win32 + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.ActiveCfg = Debug|x64 + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.ActiveCfg = Release|Win32 + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.ActiveCfg = Release|x64 + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.ActiveCfg = Debug|Win32 + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.ActiveCfg = Debug|x64 + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.ActiveCfg = Release|Win32 + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.ActiveCfg = Release|x64 + {2C5AD347-6E34-463B-8289-00578E43B255}.Debug|Win32.ActiveCfg = Debug|Win32 + {2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.ActiveCfg = Debug|x64 + {2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.ActiveCfg = Release|Win32 + {2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.ActiveCfg = Release|x64 + {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.ActiveCfg = Debug|Win32 + {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.Build.0 = Debug|Win32 + {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.ActiveCfg = Debug|x64 + {63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.ActiveCfg = Release|Win32 + {63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.ActiveCfg = Release|x64 + {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.ActiveCfg = Debug|Win32 + {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.Build.0 = Debug|Win32 + {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.ActiveCfg = Debug|x64 + {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.ActiveCfg = Release|Win32 + {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.ActiveCfg = Release|x64 + {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.ActiveCfg = Debug|Win32 + {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.Build.0 = Debug|Win32 + {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.ActiveCfg = Debug|x64 + {4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.ActiveCfg = Release|Win32 + {4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.ActiveCfg = Release|x64 + {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|Win32.ActiveCfg = Debug|Win32 + {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|Win32.Build.0 = Debug|Win32 + {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.ActiveCfg = Debug|x64 + {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.ActiveCfg = Release|Win32 + {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.ActiveCfg = Release|x64 + {698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|Win32.ActiveCfg = Debug|Win32 + {698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.ActiveCfg = Debug|x64 + {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.ActiveCfg = Release|Win32 + {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.ActiveCfg = Release|x64 + {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|Win32.ActiveCfg = Debug|Win32 + {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.ActiveCfg = Debug|x64 + {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.ActiveCfg = Release|Win32 + {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.ActiveCfg = Release|x64 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.ActiveCfg = Debug|Win32 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.Build.0 = Debug|Win32 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|x64.ActiveCfg = Debug|x64 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Release|Win32.ActiveCfg = Release|Win32 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Release|Win32.Build.0 = Release|Win32 + {9F32C692-9106-43AF-A291-779A2D8BE096}.Release|x64.ActiveCfg = Release|x64 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.ActiveCfg = Debug|Win32 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.Build.0 = Debug|Win32 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|x64.ActiveCfg = Debug|x64 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.ActiveCfg = Release|Win32 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.Build.0 = Release|Win32 + {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|x64.ActiveCfg = Release|x64 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.ActiveCfg = Debug|Win32 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.Build.0 = Debug|Win32 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|x64.ActiveCfg = Debug|x64 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|x64.Build.0 = Debug|x64 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.ActiveCfg = Release|Win32 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.Build.0 = Release|Win32 + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|x64.ActiveCfg = Release|x64 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.ActiveCfg = Debug|Win32 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.Build.0 = Debug|Win32 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|x64.ActiveCfg = Debug|x64 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.ActiveCfg = Release|Win32 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.Build.0 = Release|Win32 + {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|x64.ActiveCfg = Release|x64 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|Win32.ActiveCfg = Debug|Win32 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|Win32.Build.0 = Debug|Win32 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|x64.ActiveCfg = Debug|x64 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|Win32.ActiveCfg = Release|Win32 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|Win32.Build.0 = Release|Win32 + {11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|x64.ActiveCfg = Release|x64 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|Win32.ActiveCfg = Debug|Win32 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|Win32.Build.0 = Debug|Win32 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|x64.ActiveCfg = Debug|x64 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|Win32.ActiveCfg = Release|Win32 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|Win32.Build.0 = Release|Win32 + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|x64.ActiveCfg = Release|x64 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|Win32.ActiveCfg = Debug|Win32 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|Win32.Build.0 = Debug|Win32 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|x64.ActiveCfg = Debug|x64 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|Win32.ActiveCfg = Release|Win32 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|Win32.Build.0 = Release|Win32 + {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|x64.ActiveCfg = Release|x64 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|Win32.ActiveCfg = Debug|Win32 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|Win32.Build.0 = Debug|Win32 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|x64.ActiveCfg = Debug|x64 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|Win32.ActiveCfg = Release|Win32 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|Win32.Build.0 = Release|Win32 + {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|x64.ActiveCfg = Release|x64 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|Win32.ActiveCfg = Debug|Win32 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|Win32.Build.0 = Debug|Win32 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|x64.ActiveCfg = Debug|x64 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|Win32.ActiveCfg = Release|Win32 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|Win32.Build.0 = Release|Win32 + {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|x64.ActiveCfg = Release|x64 + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection + GlobalSection(NestedProjects) = preSolution + {2A7F483F-CD19-4F84-BBDA-B6A1865E2773} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {F67EB1EA-DCFA-4758-A2AA-4B570BA78036} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {2C5AD347-6E34-463B-8289-00578E43B255} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {63050112-E486-4396-B5E4-303C3BC12D39} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {4A9F9353-DB63-460A-BB1C-9CB519DFD414} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {4478909E-6983-425C-9D9F-558CF258E61E} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {006A7908-ABF3-4D18-BC35-0A29E39B95F9} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {698C2D54-475C-446F-B879-F629BBEF75FE} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {8804AD29-E398-480C-AC0F-98EC1B7A51CB} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {17077E86-AE7C-41AF-86ED-2BAC03B019BC} = {857A09AF-FE20-461C-B66F-D779422AD46B} + {F8053D66-8267-433A-BF2C-E07E2298C338} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {9F32C692-9106-43AF-A291-779A2D8BE096} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {9D588288-5A28-4AB3-96EA-442CAA508F8E} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {04DC0E3A-F247-45C2-AE27-8DE7493AA43B} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {7AA02EDF-D797-494B-929C-F628F4E4EA62} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {11727C54-463F-472A-88AF-6C3D6071BF0B} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {E34ECD90-3977-4A4B-9641-4D7F1766E9FD} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {A25CA34D-2F64-442B-A5D3-B13CB56C9957} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {9D96D09A-DE17-4011-9247-F0009E8D6DB5} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + {F113B460-4B21-4014-9A15-D472FAA9E3F9} = {F8E85E25-4D67-4A6B-A976-C920790B8798} + EndGlobalSection +EndGlobal diff --git a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj index 28462280..022c72e7 100644 --- a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj +++ b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj @@ -18,6 +18,61 @@ x64 + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + true + true + true + true + + + + + + + + + + + + + + + + + + + + + + + + {63050112-E486-4396-B5E4-303C3BC12D39} Win32Proj diff --git a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters index 9cd85105..4fe4cf12 100644 --- a/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters +++ b/msvc/unicorn/mips-softmmu/mips-softmmu.vcxproj.filters @@ -1,2 +1,128 @@  - \ No newline at end of file + + + + {723b39e0-f3cc-46d9-b9e8-6fe7e38bdf26} + + + {19efec2a-ac41-4941-9dfc-4937f91829b4} + + + {d60f24b3-d409-40d8-b7d2-f3e71960841a} + + + {1c2a8ce7-cc6f-41e8-b532-a2f030f6799d} + + + {65e8fb9c-fe61-4100-9f0e-1eab5babb4d3} + + + {0784e023-e00c-4034-adc4-9b1ad07d2eb7} + + + + + + + + + + + + + fpu + + + tcg + + + tcg + + + tcg\i386 + + + hw\mips + + + hw\mips + + + hw\mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + \ No newline at end of file diff --git a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj index 1da93282..b27454b6 100644 --- a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj +++ b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj @@ -18,6 +18,61 @@ x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + true + true + true + true + + + + + {4A9F9353-DB63-460A-BB1C-9CB519DFD414} Win32Proj diff --git a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters index 9cd85105..52799b95 100644 --- a/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters +++ b/msvc/unicorn/mips64-softmmu/mips64-softmmu.vcxproj.filters @@ -1,2 +1,128 @@  - \ No newline at end of file + + + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + + + + + + + + + fpu + + + hw\mips + + + hw\mips + + + hw\mips + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + {d5143bfc-0d98-4c10-aa97-eddbc37aca5e} + + + {c27c2a6c-adb5-4f4a-ae2d-778d1aff259e} + + + {39b8b5d5-ffa1-4eb6-ab78-2edb05e49e84} + + + {bbe2ce8b-4fcd-496e-9f45-6f65ada00d84} + + + {3c66ada6-0f5f-40f5-a62c-c6dee6596791} + + + {a4e58c5f-5143-4c18-b291-2f472259d6d9} + + + \ No newline at end of file diff --git a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj index ef6b62c7..e3137490 100644 --- a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj +++ b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj @@ -18,6 +18,61 @@ x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + true + true + true + true + + + + + {4478909E-6983-425C-9D9F-558CF258E61E} Win32Proj diff --git a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters index 9cd85105..3cfe41ac 100644 --- a/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters +++ b/msvc/unicorn/mips64el-softmmu/mips64el-softmmu.vcxproj.filters @@ -1,2 +1,128 @@  - \ No newline at end of file + + + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + + + + + + + + + fpu + + + hw\mips + + + hw\mips + + + hw\mips + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + {2b2b58ad-804f-435b-b55d-1c21e050cf31} + + + {a6046583-2534-498c-9bd2-08dd8c222c18} + + + {2253570a-0bc0-4366-9eab-095257ab37b2} + + + {b4ef3640-fe65-476d-9b4f-3c6d82a5dbfd} + + + {95533292-741a-46c5-a003-cbb60c8654ce} + + + {de33cbbc-f374-4451-a083-23c5a98c843e} + + + \ No newline at end of file diff --git a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj index 70a00857..71f8f484 100644 --- a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj +++ b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj @@ -18,6 +18,61 @@ x64 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + true + true + true + true + + + + + {006A7908-ABF3-4D18-BC35-0A29E39B95F9} Win32Proj diff --git a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters index 9cd85105..f9942f55 100644 --- a/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters +++ b/msvc/unicorn/mipsel-softmmu/mipsel-softmmu.vcxproj.filters @@ -1,2 +1,128 @@  - \ No newline at end of file + + + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + + + + + + + + fpu + + + hw\mips + + + hw\mips + + + hw\mips + + + tcg + + + tcg + + + tcg\i386 + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + target-mips + + + + + + {00b0caab-f50f-47a1-99ea-a452f1e712e3} + + + {f666e049-ed32-4817-9998-b6898ce2b71a} + + + {b2a1fb8b-789a-45a6-a814-9312ad75bd70} + + + {cce3d221-0ae7-4cea-a9bd-5fe10a932c20} + + + {9b5981d1-89fd-4210-ac4d-7b3dab34871b} + + + {e6bea1c8-7307-44c8-9956-25321f73287f} + + + \ No newline at end of file diff --git a/msvc/unicorn/unicorn/unicorn.vcxproj b/msvc/unicorn/unicorn/unicorn.vcxproj index bd6f3596..a501538b 100644 --- a/msvc/unicorn/unicorn/unicorn.vcxproj +++ b/msvc/unicorn/unicorn/unicorn.vcxproj @@ -165,6 +165,7 @@ + @@ -236,7 +237,7 @@ Level3 Disabled - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_X86 + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 MultiThreadedDebug .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -248,7 +249,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -260,7 +261,7 @@ Level3 Disabled - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_X86 + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 MultiThreadedDebug .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -272,7 +273,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -286,7 +287,7 @@ MaxSpeed true true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_X86 + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 MultiThreaded .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -300,7 +301,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -314,7 +315,7 @@ MaxSpeed true true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_X86 + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 MultiThreaded .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -328,7 +329,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat diff --git a/msvc/unicorn/unicorn/unicorn.vcxproj.filters b/msvc/unicorn/unicorn/unicorn.vcxproj.filters index 5aee4575..f03098bd 100644 --- a/msvc/unicorn/unicorn/unicorn.vcxproj.filters +++ b/msvc/unicorn/unicorn/unicorn.vcxproj.filters @@ -494,5 +494,8 @@ qemu + + qemu + \ No newline at end of file diff --git a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj index 21e50c15..472c24f6 100644 --- a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj +++ b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj @@ -58,7 +58,16 @@ + + + + + + + + + @@ -67,6 +76,8 @@ + + {17077E86-AE7C-41AF-86ED-2BAC03B019BC} diff --git a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters index 61f6c986..8531d5c2 100644 --- a/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters +++ b/msvc/unicorn/x86_64-softmmu/x86_64-softmmu.vcxproj.filters @@ -131,5 +131,34 @@ tcg\i386 + + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + + + target-i386 + \ No newline at end of file diff --git a/qemu/hw/mips/cputimer.c b/qemu/hw/mips/cputimer.c index 3807a715..71d28815 100644 --- a/qemu/hw/mips/cputimer.c +++ b/qemu/hw/mips/cputimer.c @@ -34,7 +34,7 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env) uint32_t idx; /* Don't return same value twice, so get another value */ do { - lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u); + lfsr = (lfsr >> 1) ^ ((0-(lfsr & 1u)) & 0xd0000001u); idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired; } while (idx == prev_idx); prev_idx = idx; diff --git a/qemu/hw/mips/mips_r4k.c b/qemu/hw/mips/mips_r4k.c index 6b722c03..40f59926 100644 --- a/qemu/hw/mips/mips_r4k.c +++ b/qemu/hw/mips/mips_r4k.c @@ -44,10 +44,13 @@ static int mips_r4k_init(struct uc_struct *uc, MachineState *machine) void mips_machine_init(struct uc_struct *uc) { static QEMUMachine mips_machine = { - .name = "mips", - .init = mips_r4k_init, - .is_default = 1, - .arch = UC_ARCH_MIPS, + NULL, + "mips", + mips_r4k_init, + NULL, + 0, + 1, + UC_ARCH_MIPS, }; qemu_register_machine(uc, &mips_machine, TYPE_MACHINE, NULL); diff --git a/qemu/include/exec/cpu-defs.h b/qemu/include/exec/cpu-defs.h index 07dcf667..82c9ce57 100644 --- a/qemu/include/exec/cpu-defs.h +++ b/qemu/include/exec/cpu-defs.h @@ -94,14 +94,29 @@ typedef struct CPUTLBEntry { use the corresponding iotlb value. */ uintptr_t addend; /* padding to get a power of two size */ -#if defined(_MSC_VER) && defined(_WIN64) - // dummy would be size 0 which isnt supported by msvc, so we remove it -#else + +#ifdef _MSC_VER +# define TARGET_ULONG_SIZE (TARGET_LONG_BITS/8) +# ifdef _WIN64 +# define UINTPTR_SIZE 8 +# else +# define UINTPTR_SIZE 4 +# endif + +#define DUMMY_SIZE (1 << CPU_TLB_ENTRY_BITS) - \ + (TARGET_ULONG_SIZE * 3 + \ + ((-TARGET_ULONG_SIZE * 3) & (UINTPTR_SIZE - 1)) + \ + UINTPTR_SIZE) + +#if DUMMY_SIZE > 0 + uint8_t dummy[DUMMY_SIZE]; +#endif +#else // _MSC_VER uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - (sizeof(target_ulong) * 3 + - (((-(int)sizeof(target_ulong)) * 3) & (sizeof(uintptr_t) - 1)) + + ((-sizeof(target_ulong) * 3) & (sizeof(uintptr_t) - 1)) + sizeof(uintptr_t))]; -#endif +#endif // _MSC_VER } CPUTLBEntry; QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index d88ae9d3..920552e7 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -977,15 +977,6 @@ typedef struct CPUX86State { uint8_t nmi_injected; uint8_t nmi_pending; -#if NB_MMU_MODES == 0 -#error NB_MMU_MODES is zero -#endif -#if CPU_TLB_SIZE == 0 -#error CPU_TLB_SIZE is zero -#endif -#if CPU_VTLB_SIZE == 0 -#error CPU_VTLB_SIZE is zero -#endif CPU_COMMON /* Fields from here on are preserved across CPU reset. */ diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 65f75564..13da4361 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -1144,10 +1144,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) jcc_op = (b >> 1) & 7; switch (s->cc_op) { - case CC_OP_SUBB: - case CC_OP_SUBW: - case CC_OP_SUBL: - case CC_OP_SUBQ: + case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: /* We optimize relational operators for the cmp/jcc case. */ size = s->cc_op - CC_OP_SUBB; switch (jcc_op) { diff --git a/qemu/target-mips/cpu.c b/qemu/target-mips/cpu.c index b7bc1a51..f73d95c2 100644 --- a/qemu/target-mips/cpu.c +++ b/qemu/target-mips/cpu.c @@ -146,14 +146,22 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data void mips_cpu_register_types(void *opaque) { const TypeInfo mips_cpu_type_info = { - .name = TYPE_MIPS_CPU, - .parent = TYPE_CPU, - .instance_userdata = opaque, - .instance_size = sizeof(MIPSCPU), - .instance_init = mips_cpu_initfn, - .abstract = false, - .class_size = sizeof(MIPSCPUClass), - .class_init = mips_cpu_class_init, + TYPE_MIPS_CPU, + TYPE_CPU, + + sizeof(MIPSCPUClass), + sizeof(MIPSCPU), + opaque, + + mips_cpu_initfn, + NULL, + NULL, + + mips_cpu_class_init, + NULL, + NULL, + + false, }; type_register_static(opaque, &mips_cpu_type_info); diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h index 1c192cef..1a0a386a 100644 --- a/qemu/target-mips/cpu.h +++ b/qemu/target-mips/cpu.h @@ -571,7 +571,7 @@ struct CPUMIPSState { uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ int insn_flags; /* Supported instruction set */ - CPU_COMMON + CPU_COMMON /* Fields from here on are preserved across CPU reset. */ CPUMIPSMVPContext *mvp; diff --git a/qemu/target-mips/dsp_helper.c b/qemu/target-mips/dsp_helper.c index 349f2a00..46528de3 100644 --- a/qemu/target-mips/dsp_helper.c +++ b/qemu/target-mips/dsp_helper.c @@ -3678,7 +3678,7 @@ void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env) void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env) { - return cpu_wrdsp(rs, mask_num, env); + cpu_wrdsp(rs, mask_num, env); } uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env) diff --git a/qemu/target-mips/helper.c b/qemu/target-mips/helper.c index 607b3f21..eca150d3 100644 --- a/qemu/target-mips/helper.c +++ b/qemu/target-mips/helper.c @@ -377,43 +377,44 @@ hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int r #endif static const char * const excp_names[EXCP_LAST + 1] = { - [EXCP_RESET] = "reset", - [EXCP_SRESET] = "soft reset", - [EXCP_DSS] = "debug single step", - [EXCP_DINT] = "debug interrupt", - [EXCP_NMI] = "non-maskable interrupt", - [EXCP_MCHECK] = "machine check", - [EXCP_EXT_INTERRUPT] = "interrupt", - [EXCP_DFWATCH] = "deferred watchpoint", - [EXCP_DIB] = "debug instruction breakpoint", - [EXCP_IWATCH] = "instruction fetch watchpoint", - [EXCP_AdEL] = "address error load", - [EXCP_AdES] = "address error store", - [EXCP_TLBF] = "TLB refill", - [EXCP_IBE] = "instruction bus error", - [EXCP_DBp] = "debug breakpoint", - [EXCP_SYSCALL] = "syscall", - [EXCP_BREAK] = "break", - [EXCP_CpU] = "coprocessor unusable", - [EXCP_RI] = "reserved instruction", - [EXCP_OVERFLOW] = "arithmetic overflow", - [EXCP_TRAP] = "trap", - [EXCP_FPE] = "floating point", - [EXCP_DDBS] = "debug data break store", - [EXCP_DWATCH] = "data watchpoint", - [EXCP_LTLBL] = "TLB modify", - [EXCP_TLBL] = "TLB load", - [EXCP_TLBS] = "TLB store", - [EXCP_DBE] = "data bus error", - [EXCP_DDBL] = "debug data break load", - [EXCP_THREAD] = "thread", - [EXCP_MDMX] = "MDMX", - [EXCP_C2E] = "precise coprocessor 2", - [EXCP_CACHE] = "cache error", - [EXCP_TLBXI] = "TLB execute-inhibit", - [EXCP_TLBRI] = "TLB read-inhibit", - [EXCP_MSADIS] = "MSA disabled", - [EXCP_MSAFPE] = "MSA floating point", + "reset", + "soft reset", + "debug single step", + "debug interrupt", + "debug data break load", + "debug data break store", + "non-maskable interrupt", + "machine check", + "interrupt", + "deferred watchpoint", + "debug instruction breakpoint", + "instruction fetch watchpoint", + "address error load", + "address error store", + "TLB refill", + "instruction bus error", + "debug breakpoint", + "syscall", + "break", + "coprocessor unusable", + "reserved instruction", + "arithmetic overflow", + "trap", + "floating point", + "data watchpoint", + "TLB modify", + "TLB load", + "TLB store", + "data bus error", + "thread", + "MDMX", + "precise coprocessor 2", + "cache error", + "DSP disabled", + "MSA disabled", + "MSA floating point", + "TLB execute-inhibit", + "TLB read-inhibit", }; target_ulong exception_resume_pc (CPUMIPSState *env) diff --git a/qemu/target-mips/msa_helper.c b/qemu/target-mips/msa_helper.c index b08f37f7..dccadc46 100644 --- a/qemu/target-mips/msa_helper.c +++ b/qemu/target-mips/msa_helper.c @@ -21,7 +21,7 @@ #include "exec/helper-proto.h" /* Data format min and max values */ -#define DF_BITS(df) (1 << ((df) + 3)) +#define DF_BITS(df) ((uint64_t)1 << ((df) + 3)) #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1) #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1) @@ -29,8 +29,8 @@ #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1))) #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1))) -#define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df))) -#define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m))) +#define DF_MAX_UINT(df) (uint64_t)((0-1ULL) >> (64 - DF_BITS(df))) +#define M_MAX_UINT(m) (uint64_t)((0-1ULL) >> (64 - (m))) #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df)) #define SIGNED(x, df) \ @@ -786,7 +786,7 @@ static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2) { int64_t q_min = DF_MIN_INT(df); int64_t q_max = DF_MAX_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2); if (arg1 == q_min && arg2 == q_min) { return q_max; @@ -984,7 +984,7 @@ static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1, int64_t q_max = DF_MAX_INT(df); int64_t q_min = DF_MIN_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2); q_prod = arg1 * arg2; q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1); @@ -999,7 +999,7 @@ static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1, int64_t q_max = DF_MAX_INT(df); int64_t q_min = DF_MIN_INT(df); - int64_t r_bit = 1 << (DF_BITS(df) - 2); + int64_t r_bit = (int64_t)1 << (DF_BITS(df) - 2); q_prod = arg1 * arg2; q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1); diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index cd6255b8..9a0e0dc9 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -5328,7 +5328,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 18: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_1e0i(tcg_ctx, mfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -5338,7 +5338,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 19: switch (sel) { - case 0 ...7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -5458,7 +5458,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 27: switch (sel) { - case 0 ... 3: + case 0: case 1: case 2: case 3: tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ rn = "CacheErr"; break; @@ -5524,7 +5524,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; - case 2 ... 7: + case 2: case 3: case 4: case 5: case 6: case 7: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -5947,7 +5947,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 18: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -5957,7 +5957,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 19: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -6088,7 +6088,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 27: switch (sel) { - case 0 ... 3: + case 0: case 1: case 2: case 3: /* ignored */ rn = "CacheErr"; break; @@ -6154,7 +6154,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; - case 2 ... 7: + case 2: case 3: case 4: case 5: case 6: case 7: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -6572,7 +6572,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 18: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_1e0i(tcg_ctx, dmfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -6582,7 +6582,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 19: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -6699,7 +6699,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 27: switch (sel) { /* ignored */ - case 0 ... 3: + case 0: case 1: case 2: case 3: tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ rn = "CacheErr"; break; @@ -6764,7 +6764,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; - case 2 ... 7: + case 2: case 3: case 4: case 5: case 6: case 7: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -7191,7 +7191,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 18: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -7201,7 +7201,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 19: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -7328,7 +7328,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 27: switch (sel) { - case 0 ... 3: + case 0: case 1: case 2: case 3: /* ignored */ rn = "CacheErr"; break; @@ -7394,7 +7394,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) gen_mtc0_store32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); rn = "DESAVE"; break; - case 2 ... 7: + case 2: case 3: case 4: case 5: case 6: case 7: CP0_CHECK(ctx->kscrexist & (1 << sel)); tcg_gen_st_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_KScratch[sel-2])); @@ -7530,7 +7530,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, break; case 16: switch (sel) { - case 0 ... 7: + case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: gen_helper_mftc0_configx(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_const_tl(tcg_ctx, sel)); break; default: @@ -16208,7 +16208,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) tcg_temp_free(tcg_ctx, t0); } break; - case OPC_MULT ... OPC_DIVU: + case OPC_MULT: case OPC_MULTU: case OPC_DIV: case OPC_DIVU: op2 = MASK_R6_MULDIV(ctx->opcode); switch (op2) { case R6_OPC_MUL: @@ -16274,7 +16274,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) generate_exception(ctx, EXCP_RI); } break; - case OPC_DMULT ... OPC_DDIVU: + case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU: op2 = MASK_R6_MULDIV(ctx->opcode); switch (op2) { case R6_OPC_DMUL: @@ -16353,7 +16353,7 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) gen_muldiv(ctx, op1, 0, rs, rt); break; #if defined(TARGET_MIPS64) - case OPC_DMULT ... OPC_DDIVU: + case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_muldiv(ctx, op1, 0, rs, rt); @@ -16422,7 +16422,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; } break; - case OPC_ADD ... OPC_SUBU: + case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU: gen_arith(ctx, op1, rd, rs, rt); break; case OPC_SLLV: /* Shifts */ @@ -16458,7 +16458,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) case OPC_JALR: gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); break; - case OPC_TGE ... OPC_TEQ: /* Traps */ + case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ: case OPC_TNE: gen_trap(ctx, op1, rs, rt, -1); break; @@ -16533,7 +16533,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) break; } break; - case OPC_DADD ... OPC_DSUBU: + case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU: check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); gen_arith(ctx, op1, rd, rs, rt); @@ -16591,8 +16591,8 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL2(ctx->opcode); switch (op1) { - case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ - case OPC_MSUB ... OPC_MSUBU: + case OPC_MADD: case OPC_MADDU: + case OPC_MSUB: case OPC_MSUBU: check_insn(ctx, ISA_MIPS32); gen_muldiv(ctx, op1, rd & 3, rs, rt); break; @@ -16683,16 +16683,17 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) break; case OPC_BSHFL: { - if (rd == 0) { + TCGv t0; + if (rd == 0) { /* Treat as NOP. */ break; } - TCGv t0 = tcg_temp_new(tcg_ctx); + t0 = tcg_temp_new(tcg_ctx); gen_load_gpr(ctx, t0, rt); op2 = MASK_BSHFL(ctx->opcode); switch (op2) { - case OPC_ALIGN ... OPC_ALIGN_END: + case OPC_ALIGN: case OPC_ALIGN_END: sa &= 3; if (sa == 0) { tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0); @@ -16728,16 +16729,17 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) case OPC_DBSHFL: check_mips_64(ctx); { - if (rd == 0) { + TCGv t0; + if (rd == 0) { /* Treat as NOP. */ break; } - TCGv t0 = tcg_temp_new(tcg_ctx); + t0 = tcg_temp_new(tcg_ctx); gen_load_gpr(ctx, t0, rt); op2 = MASK_DBSHFL(ctx->opcode); switch (op2) { - case OPC_DALIGN ... OPC_DALIGN_END: + case OPC_DALIGN: case OPC_DALIGN_END: sa &= 7; if (sa == 0) { tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0); @@ -16778,9 +16780,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) op1 = MASK_SPECIAL3(ctx->opcode); switch (op1) { - case OPC_DIV_G_2E ... OPC_DIVU_G_2E: - case OPC_MOD_G_2E ... OPC_MODU_G_2E: - case OPC_MULT_G_2E ... OPC_MULTU_G_2E: + case OPC_DIV_G_2E: case OPC_DIVU_G_2E: + case OPC_MOD_G_2E: case OPC_MODU_G_2E: + case OPC_MULT_G_2E: case OPC_MULTU_G_2E: /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have * the same mask and op1. */ if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { @@ -17045,9 +17047,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DDIV_G_2E ... OPC_DDIVU_G_2E: - case OPC_DMULT_G_2E ... OPC_DMULTU_G_2E: - case OPC_DMOD_G_2E ... OPC_DMODU_G_2E: + case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E: + case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: + case OPC_DMOD_G_2E: case OPC_DMODU_G_2E: check_insn(ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; @@ -17310,7 +17312,7 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) case OPC_BSHFL: op2 = MASK_BSHFL(ctx->opcode); switch (op2) { - case OPC_ALIGN ... OPC_ALIGN_END: + case OPC_ALIGN: case OPC_ALIGN_END: case OPC_BITSWAP: check_insn(ctx, ISA_MIPS32R6); decode_opc_special3_r6(env, ctx); @@ -17322,16 +17324,16 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) } break; #if defined(TARGET_MIPS64) - case OPC_DEXTM ... OPC_DEXT: - case OPC_DINSM ... OPC_DINS: - check_insn(ctx, ISA_MIPS64R2); + case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT: + case OPC_DINSM: case OPC_DINSU: case OPC_DINS: + check_insn(ctx, ISA_MIPS64R2); check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_DBSHFL: op2 = MASK_DBSHFL(ctx->opcode); switch (op2) { - case OPC_DALIGN ... OPC_DALIGN_END: + case OPC_DALIGN: case OPC_DALIGN_END: case OPC_DBITSWAP: check_insn(ctx, ISA_MIPS32R6); decode_opc_special3_r6(env, ctx); @@ -18585,7 +18587,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); } break; - case OPC_TGEI ... OPC_TEQI: /* REGIMM traps */ + case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */ case OPC_TNEI: check_insn_opc_removed(ctx, ISA_MIPS32R6); gen_trap(ctx, op1, rs, -1, imm); @@ -18643,7 +18645,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa gen_cp0(env, ctx, op1, rt, rd); #endif /* !CONFIG_USER_ONLY */ break; - case OPC_C0_FIRST ... OPC_C0_LAST: + case OPC_C0_FIRST: case OPC_C0_LAST: #ifndef CONFIG_USER_ONLY gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); #endif /* !CONFIG_USER_ONLY */ @@ -18738,7 +18740,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa case OPC_XORI: gen_logic_imm(ctx, op, rt, rs, imm); break; - case OPC_J ... OPC_JAL: /* Jump */ + case OPC_J: case OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); break; @@ -18800,14 +18802,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa case OPC_LWR: case OPC_LL: check_insn_opc_removed(ctx, ISA_MIPS32R6); - case OPC_LB ... OPC_LH: - case OPC_LW ... OPC_LHU: + case OPC_LB: case OPC_LH: + case OPC_LW: case OPC_LBU: case OPC_LHU: gen_ld(ctx, op, rt, rs, imm); break; case OPC_SWL: case OPC_SWR: check_insn_opc_removed(ctx, ISA_MIPS32R6); - case OPC_SB ... OPC_SH: + case OPC_SB: case OPC_SH: case OPC_SW: gen_st(ctx, op, rt, rs, imm); break; @@ -19065,7 +19067,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa #if defined(TARGET_MIPS64) /* MIPS64 opcodes */ - case OPC_LDL ... OPC_LDR: + case OPC_LDL: case OPC_LDR: case OPC_LLD: check_insn_opc_removed(ctx, ISA_MIPS32R6); case OPC_LWU: @@ -19074,7 +19076,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa check_mips_64(ctx); gen_ld(ctx, op, rt, rs, imm); break; - case OPC_SDL ... OPC_SDR: + case OPC_SDL: case OPC_SDR: check_insn_opc_removed(ctx, ISA_MIPS32R6); case OPC_SD: check_insn(ctx, ISA_MIPS3); diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c index 148b394c..98b456fe 100644 --- a/qemu/target-mips/translate_init.c +++ b/qemu/target-mips/translate_init.c @@ -108,519 +108,701 @@ struct mips_def_t { static const mips_def_t mips_defs[] = { { - .name = "4Kc", - .CP0_PRid = 0x00018000, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + "4Kc", + 0x00018000, + MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32, - .mmu_type = MMU_TYPE_R4000, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x1278FF17, + 0, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32, + MMU_TYPE_R4000, }, { - .name = "4Km", - .CP0_PRid = 0x00018300, + "4Km", + 0x00018300, /* Config1 implemented, fixed mapping MMU, no virtual icache, uncached coherency. */ - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | + MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + MIPS_CONFIG1 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + + 0, + 4, + 32, + 2, + 0x1258FF17, + 0, + + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32 | ASE_MIPS16, + MMU_TYPE_FMT, }, { - .name = "4KEcR1", - .CP0_PRid = 0x00018400, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + "4KEcR1", + 0x00018400, + MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), + MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32, - .mmu_type = MMU_TYPE_R4000, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x1278FF17, + 0, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32, + MMU_TYPE_R4000, }, { - .name = "4KEmR1", - .CP0_PRid = 0x00018500, - .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | + "4KEmR1", + 0x00018500, + MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), + MIPS_CONFIG1 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x1258FF17, + 0, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32 | ASE_MIPS16, + MMU_TYPE_FMT, }, { - .name = "4KEc", - .CP0_PRid = 0x00019000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "4KEc", + 0x00019000, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (0 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1278FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2, - .mmu_type = MMU_TYPE_R4000, + MIPS_CONFIG2, + MIPS_CONFIG3 | (0 << CP0C3_VInt), + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x1278FF17, + 0, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R2, + MMU_TYPE_R4000, }, { - .name = "4KEm", - .CP0_PRid = 0x00019100, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "4KEm", + 0x00019100, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | + MIPS_CONFIG1 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x1258FF17, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_FMT, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x1258FF17, + 0, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R2 | ASE_MIPS16, + MMU_TYPE_FMT, }, { - .name = "24Kc", - .CP0_PRid = 0x00019300, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "24Kc", + 0x00019300, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, + MIPS_CONFIG2, + MIPS_CONFIG3 | (0 << CP0C3_VInt), + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x1278FF1F, - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_R4000, + 0x1278FF1F, + 0, + 0, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R2 | ASE_MIPS16, + MMU_TYPE_R4000, }, { - .name = "24Kf", - .CP0_PRid = 0x00019300, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "24Kf", + 0x00019300, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, + MIPS_CONFIG2, + MIPS_CONFIG3 | (0 << CP0C3_VInt), + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, /* No DSP implemented. */ - .CP0_Status_rw_bitmask = 0x3678FF1F, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + 0x3678FF1F, + 0, + 0, + (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, - .mmu_type = MMU_TYPE_R4000, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R2 | ASE_MIPS16, + MMU_TYPE_R4000, }, { - .name = "34Kf", - .CP0_PRid = 0x00019500, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "34Kf", + 0x00019500, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | (1 << CP0C3_DSPP), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | + 0, + 0, + 32, + 2, + 0x3778FF1F, + (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | (0xff << CP0TCSt_TASID), - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (0xf << CP0SRSCtl_HSS), + 0, + 32, + 32, + (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), - .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), - .CP0_SRSConf0_rw_bitmask = 0x3fffffff, - .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + 0x3fffffff, + (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), - .CP0_SRSConf1_rw_bitmask = 0x3fffffff, - .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + 0x3fffffff, + (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), - .CP0_SRSConf2_rw_bitmask = 0x3fffffff, - .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + 0x3fffffff, + (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), - .CP0_SRSConf3_rw_bitmask = 0x3fffffff, - .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + 0x3fffffff, + (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), - .CP0_SRSConf4_rw_bitmask = 0x3fffffff, - .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | + 0x3fffffff, + (0x3fe << CP0SRSC4_SRS15) | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, - .mmu_type = MMU_TYPE_R4000, + 0,0, + CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, + MMU_TYPE_R4000, }, { - .name = "74Kf", - .CP0_PRid = 0x00019700, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "74Kf", + 0x00019700, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x3778FF1F, + 0, + 0, + (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, - .mmu_type = MMU_TYPE_R4000, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + MMU_TYPE_R4000, }, { /* A generic CPU providing MIPS32 Release 5 features. FIXME: Eventually this should be replaced by a real CPU model. */ - .name = "mips32r5-generic", - .CP0_PRid = 0x00019700, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + "mips32r5-generic", + 0x00019700, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), - .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), - .CP0_Config4_rw_bitmask = 0, - .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), - .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP), + MIPS_CONFIG4 | (1U << CP0C4_M), + 0, + MIPS_CONFIG5 | (1 << CP0C5_UFR), + (0 << CP0C5_M) | (1 << CP0C5_K) | (1 << CP0C5_CV) | (0 << CP0C5_EVA) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | (0 << CP0C5_NFExists), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3778FF1F, - .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | + 0, + 0, + 0, + 4, + 32, + 2, + 0x3778FF1F, + 0, + 0, + (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), - .SEGBITS = 32, - .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, - .mmu_type = MMU_TYPE_R4000, + 0, + 32, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, + MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) { - .name = "R4000", - .CP0_PRid = 0x00000400, + "R4000", + 0x00000400, /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ - .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), /* Note: Config1 is only used internally, the R4000 has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3678FFFF, - /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 40, - .PABITS = 36, - .insn_flags = CPU_MIPS3, - .mmu_type = MMU_TYPE_R4000, + (1 << CP0C1_FP) | (47 << CP0C1_MMU), + 0, + 0, + 0,0, + 0,0, + 0, + 0, + 0xFFFFFFFF, + 4, + 16, + 2, + 0x3678FFFF, + 0, + 0, + /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ + (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), + 0, + 40, + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS3, + MMU_TYPE_R4000, }, { - .name = "VR5432", - .CP0_PRid = 0x00005400, + "VR5432", + 0x00005400, /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ - .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x3678FFFF, - /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 40, - .PABITS = 32, - .insn_flags = CPU_VR54XX, - .mmu_type = MMU_TYPE_R4000, + (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), + (1 << CP0C1_FP) | (47 << CP0C1_MMU), + 0, + 0, + 0,0, + 0,0, + 0, + 0, + 0xFFFFFFFFL, + 4, + 16, + 2, + 0x3678FFFF, + 0, + 0, + /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ + (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), + 0, + 40, + 32, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_VR54XX, + MMU_TYPE_R4000, }, { - .name = "5Kc", - .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + "5Kc", + 0x00018100, + MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | + MIPS_CONFIG1 | (31 << CP0C1_MMU) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x32F8FFFF, - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64, - .mmu_type = MMU_TYPE_R4000, + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + 0, + 4, + 32, + 2, + 0x32F8FFFF, + 0, + 0, + 0, + 0, + 42, + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS64, + MMU_TYPE_R4000, }, { - .name = "5Kf", - .CP0_PRid = 0x00018100, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + "5Kf", + 0x00018100, + MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 4, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x36F8FFFF, - /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,0, + 0,0, + 0, + 0, + + 0, + 4, + 32, + 2, + 0x36F8FFFF, + 0, + 0, + /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ + (1 << FCR0_D) | (1 << FCR0_S) | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, - .PABITS = 36, - .insn_flags = CPU_MIPS64, - .mmu_type = MMU_TYPE_R4000, + 0, + 42, + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS64, + MMU_TYPE_R4000, }, { - .name = "20Kc", + "20Kc", /* We emulate a later version of the 20Kc, earlier ones had a broken WAIT instruction. */ - .CP0_PRid = 0x000182a0, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | + 0x000182a0, + MIPS_CONFIG0 | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3, - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 1, - .CP0_Status_rw_bitmask = 0x36FBFFFF, - /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ - .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | + MIPS_CONFIG2, + MIPS_CONFIG3, + 0,.0, + 0,0, + 0, + 0, + 0, + 0, + 32, + 1, + 0x36FBFFFF, + 0, + 0, + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ + (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_D) | (1 << FCR0_S) | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 40, - .PABITS = 36, - .insn_flags = CPU_MIPS64 | ASE_MIPS3D, - .mmu_type = MMU_TYPE_R4000, + 0, + 40, + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS64 | ASE_MIPS3D, + MMU_TYPE_R4000, }, { /* A generic CPU providing MIPS64 Release 2 features. FIXME: Eventually this should be replaced by a real CPU model. */ - .name = "MIPS64R2-generic", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + "MIPS64R2-generic", + 0x00010000, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x36FBFFFF, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1 << CP0C3_LPA), + 0,0, + 0,0, + 0, + 0, + 0, + 0, + 32, + 2, + 0x36FBFFFF, + 0, + 0, + (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, + 0, + 42, /* The architectural limit is 59, but we have hardcoded 36 bit in some places... - .PABITS = 59, */ /* the architectural limit */ - .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, - .mmu_type = MMU_TYPE_R4000, + 59, */ /* the architectural limit */ + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS64R2 | ASE_MIPS3D, + MMU_TYPE_R4000, }, { /* A generic CPU supporting MIPS64 Release 6 ISA. FIXME: Support IEEE 754-2008 FP and misaligned memory accesses. Eventually this should be replaced by a real CPU model. */ - .name = "MIPS64R6-generic", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | + "MIPS64R6-generic", + 0x00010000, + MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | + MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | (3 << CP0C4_IE) | (1 << CP0C4_M), - .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x30D8FFFF, - .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | - (1U << CP0PG_RIE), - .CP0_PageGrain_rw_bitmask = 0, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + 0, + 0, + (1 << CP0C5_SBRI), + 0, + 0, + 0, + 0, + 32, + 2, + 0x30D8FFFF, + 0, + 0, + (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, + 0, + 42, /* The architectural limit is 59, but we have hardcoded 36 bit in some places... - .PABITS = 59, */ /* the architectural limit */ - .PABITS = 36, - .insn_flags = CPU_MIPS64R6, - .mmu_type = MMU_TYPE_R4000, + 59, */ /* the architectural limit */ + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, + (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | + (1U << CP0PG_RIE), + 0, + CPU_MIPS64R6, + MMU_TYPE_R4000, }, { - .name = "Loongson-2E", - .CP0_PRid = 0x6302, + "Loongson-2E", + 0x6302, /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | (0x1<<4) | (0x1<<1), /* Note: Config1 is only used internally, Loongson-2E has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x35D0FFFF, - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), - .SEGBITS = 40, - .PABITS = 40, - .insn_flags = CPU_LOONGSON2E, - .mmu_type = MMU_TYPE_R4000, + (1 << CP0C1_FP) | (47 << CP0C1_MMU), + 0, + 0, + 0,0, + 0,0, + 0, + 0, + 0, + 0, + 16, + 2, + 0x35D0FFFF, + 0, + 0, + (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + 0, + 40, + 40, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_LOONGSON2E, + MMU_TYPE_R4000, }, { - .name = "Loongson-2F", - .CP0_PRid = 0x6303, + "Loongson-2F", + 0x6303, /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ - .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | (0x1<<4) | (0x1<<1), /* Note: Config1 is only used internally, Loongson-2F has only Config0. */ - .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), - .SYNCI_Step = 16, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/ - .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), - .SEGBITS = 40, - .PABITS = 40, - .insn_flags = CPU_LOONGSON2F, - .mmu_type = MMU_TYPE_R4000, + (1 << CP0C1_FP) | (47 << CP0C1_MMU), + 0, + 0, + 0,0, + 0,0, + 0, + 0, + 0, + 0, + 16, + 2, + 0xF5D0FF1F, /*bit5:7 not writable*/ + 0, + 0, + (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + 0, + 40, + 40, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_LOONGSON2F, + MMU_TYPE_R4000, }, { /* A generic CPU providing MIPS64 ASE DSP 2 features. FIXME: Eventually this should be replaced by a real CPU model. */ - .name = "mips64dspr2", - .CP0_PRid = 0x00010000, - .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + "mips64dspr2", + 0x00010000, + MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), - .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + MIPS_CONFIG2, + MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), - .CP0_LLAddr_rw_bitmask = 0, - .CP0_LLAddr_shift = 0, - .SYNCI_Step = 32, - .CCRes = 2, - .CP0_Status_rw_bitmask = 0x37FBFFFF, - .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + 0,0, + 0,0, + 0, + 0, + 0, + 0, + 32, + 2, + 0x37FBFFFF, + 0, + 0, + (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), - .SEGBITS = 42, + 0, + 42, /* The architectural limit is 59, but we have hardcoded 36 bit in some places... - .PABITS = 59, */ /* the architectural limit */ - .PABITS = 36, - .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, - .mmu_type = MMU_TYPE_R4000, + 59, */ /* the architectural limit */ + 36, + 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, + CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, + MMU_TYPE_R4000, }, - + #endif }; diff --git a/qemu/target-mips/unicorn.c b/qemu/target-mips/unicorn.c index 43c98049..d0c7913c 100644 --- a/qemu/target-mips/unicorn.c +++ b/qemu/target-mips/unicorn.c @@ -42,10 +42,11 @@ static void mips_set_pc(struct uc_struct *uc, uint64_t address) void mips_release(void *ctx); void mips_release(void *ctx) { - int i; + MIPSCPU* cpu; + int i; TCGContext *tcg_ctx = (TCGContext *) ctx; release_common(ctx); - MIPSCPU* cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu); + cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu); g_free(cpu->env.tlb); g_free(cpu->env.mvp); @@ -68,8 +69,9 @@ void mips_release(void *ctx) void mips_reg_reset(struct uc_struct *uc) { - (void)uc; - CPUArchState *env = uc->cpu->env_ptr; + CPUArchState *env; + (void)uc; + env = uc->cpu->env_ptr; memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr)); env->active_tc.PC = 0; diff --git a/samples/mem_apis.c b/samples/mem_apis.c index d79378c8..7cb05874 100644 --- a/samples/mem_apis.c +++ b/samples/mem_apis.c @@ -20,30 +20,7 @@ #define __STDC_FORMAT_MACROS -// windows specific includes -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific includes -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER - -// common includes #include #include #include diff --git a/samples/sample_arm.c b/samples/sample_arm.c index b516f847..1e142c13 100644 --- a/samples/sample_arm.c +++ b/samples/sample_arm.c @@ -3,28 +3,8 @@ /* Sample code to demonstrate how to emulate ARM code */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER +#include // code to be emulated diff --git a/samples/sample_arm64.c b/samples/sample_arm64.c index 1ce39124..149928ac 100644 --- a/samples/sample_arm64.c +++ b/samples/sample_arm64.c @@ -3,28 +3,8 @@ /* Sample code to demonstrate how to emulate ARM64 code */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER +#include // code to be emulated diff --git a/samples/sample_batch_reg.c b/samples/sample_batch_reg.c index 5d3d55d2..9f083481 100644 --- a/samples/sample_batch_reg.c +++ b/samples/sample_batch_reg.c @@ -1,7 +1,8 @@ -#include "unicorn/platform.h" -#include -#include + #include +#include +#include + int syscall_abi[] = { UC_X86_REG_RAX, UC_X86_REG_RDI, UC_X86_REG_RSI, UC_X86_REG_RDX, diff --git a/samples/sample_m68k.c b/samples/sample_m68k.c index 272ef3e2..26ac4c1b 100644 --- a/samples/sample_m68k.c +++ b/samples/sample_m68k.c @@ -3,28 +3,9 @@ /* Sample code to demonstrate how to emulate m68k code */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD +#include -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER // code to be emulated #define M68K_CODE "\x76\xed" // movq #-19, %d3 diff --git a/samples/sample_mips.c b/samples/sample_mips.c index efe4012b..b032ec05 100644 --- a/samples/sample_mips.c +++ b/samples/sample_mips.c @@ -3,28 +3,8 @@ /* Sample code to demonstrate how to emulate Mips code (big endian) */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER +#include // code to be emulated diff --git a/samples/sample_sparc.c b/samples/sample_sparc.c index 09770916..24d937b3 100644 --- a/samples/sample_sparc.c +++ b/samples/sample_sparc.c @@ -3,28 +3,8 @@ /* Sample code to demonstrate how to emulate Sparc code */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER +#include // code to be emulated diff --git a/samples/sample_x86_32_gdt_and_seg_regs.c b/samples/sample_x86_32_gdt_and_seg_regs.c index 42851d4a..e1a17a5e 100644 --- a/samples/sample_x86_32_gdt_and_seg_regs.c +++ b/samples/sample_x86_32_gdt_and_seg_regs.c @@ -20,12 +20,10 @@ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include -#include "unicorn/platform.h" -#include #include +#include #include -#include "unicorn/platform.h" - +# #pragma pack(push, 1) struct SegmentDescriptor { union { @@ -164,8 +162,9 @@ static void gdt_demo() uc_err err; uint8_t buf[128]; uc_x86_mmr gdtr; - - /* + int i; + + /* bits 32 push dword 0x01234567 @@ -183,7 +182,7 @@ static void gdt_demo() struct SegmentDescriptor *gdt = (struct SegmentDescriptor*)calloc(31, sizeof(struct SegmentDescriptor)); - int r_esp = stack_address + 0x1000; // initial esp + int r_esp = (int)stack_address + 0x1000; // initial esp int r_cs = 0x73; int r_ss = 0x88; //ring 0 int r_ds = 0x7b; @@ -267,7 +266,6 @@ static void gdt_demo() err = uc_mem_read(uc, r_esp - 8, buf, 8); uc_assert_success(err); - int i; for (i = 0; i < 8; i++) { fprintf(stderr, "%02x", buf[i]); } diff --git a/samples/shellcode.c b/samples/shellcode.c index 4e95c774..dcf97437 100644 --- a/samples/shellcode.c +++ b/samples/shellcode.c @@ -3,30 +3,7 @@ /* Sample code to trace code with Linux code with syscall */ -// windows specific -#ifdef _MSC_VER -#include -#include -#define PRIx64 "llX" -#ifdef DYNLOAD -#include "unicorn_dynload.h" -#else // DYNLOAD #include -#ifdef _WIN64 -#pragma comment(lib, "unicorn_staload64.lib") -#else // _WIN64 -#pragma comment(lib, "unicorn_staload.lib") -#endif // _WIN64 -#endif // DYNLOAD - -// posix specific -#else // _MSC_VER -#include "unicorn/platform.h" -#include "unicorn/platform.h" -#include -#endif // _MSC_VER - -// common includes #include