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This commit is contained in:
xorstream
2017-01-21 12:28:22 +11:00
parent df41c49e2d
commit 770c5616e2
69 changed files with 3839 additions and 3839 deletions
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180
qemu/tcg/i386/tcg-target.c
View File

@ -78,12 +78,12 @@ static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R9,
#else
/* 32 bit mode uses stack based calling convention (GCC default).
We add a dummy value here for MSVC compatibility for the error:
"error C2466: cannot allocate an array of constant size 0"
The "tcg_target_call_iarg_regs" array is not accessed when
TCG_TARGET_REG_BITS == 32
*/
0,
We add a dummy value here for MSVC compatibility for the error:
"error C2466: cannot allocate an array of constant size 0"
The "tcg_target_call_iarg_regs" array is not accessed when
TCG_TARGET_REG_BITS == 32
*/
0,
#endif
};
@ -411,24 +411,24 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
static const uint8_t tcg_cond_to_jcc[] = {
#ifdef _MSC_VER
0, // TCG_COND_NEVER
0, // TCG_COND_ALWAYS
JCC_JL, // TCG_COND_LT
JCC_JGE, // TCG_COND_GE
JCC_JB, // TCG_COND_LTU
JCC_JAE, // TCG_COND_GEU
0, // n/a
0, // n/a
JCC_JE, // TCG_COND_EQ
JCC_JNE, // TCG_COND_NE
JCC_JLE, // TCG_COND_LE
JCC_JG, // TCG_COND_GT
JCC_JBE, // TCG_COND_LEU
JCC_JA, // TCG_COND_GTU
0, // n/a
0, // n/a
0, // TCG_COND_NEVER
0, // TCG_COND_ALWAYS
JCC_JL, // TCG_COND_LT
JCC_JGE, // TCG_COND_GE
JCC_JB, // TCG_COND_LTU
JCC_JAE, // TCG_COND_GEU
0, // n/a
0, // n/a
JCC_JE, // TCG_COND_EQ
JCC_JNE, // TCG_COND_NE
JCC_JLE, // TCG_COND_LE
JCC_JG, // TCG_COND_GT
JCC_JBE, // TCG_COND_LEU
JCC_JA, // TCG_COND_GTU
0, // n/a
0, // n/a
#else
[TCG_COND_EQ] = JCC_JE,
[TCG_COND_EQ] = JCC_JE,
[TCG_COND_NE] = JCC_JNE,
[TCG_COND_LT] = JCC_JL,
[TCG_COND_GE] = JCC_JGE,
@ -1155,43 +1155,43 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest)
*/
static void * const qemu_ld_helpers[16] = {
#ifdef _MSC_VER
helper_ret_ldub_mmu, // MO_UB
helper_ret_ldub_mmu, // MO_UB
# ifdef HOST_WORDS_BIGENDIAN
helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ
0, // MO_SB
0, // MO_BESW
0, // MO_BESL
0, // n/a
0, // n/a
helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ
0, // n/a
0, // MO_LESW
0, // MO_LESL
0, // n/a
helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ
0, // MO_SB
0, // MO_BESW
0, // MO_BESL
0, // n/a
0, // n/a
helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ
0, // n/a
0, // MO_LESW
0, // MO_LESL
0, // n/a
# else // !HOST_WORDS_BIGENDIAN
helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ
0, // MO_SB
0, // MO_LESW
0, // MO_LESL
0, // n/a
0, // n/a
helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ
0, // n/a
0, // MO_BESW
0, // MO_BESL
0, // n/a
helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ
0, // MO_SB
0, // MO_LESW
0, // MO_LESL
0, // n/a
0, // n/a
helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ
0, // n/a
0, // MO_BESW
0, // MO_BESL
0, // n/a
# endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER
[MO_UB] = helper_ret_ldub_mmu,
[MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu,
[MO_LEQ] = helper_le_ldq_mmu,
@ -1206,39 +1206,39 @@ static void * const qemu_ld_helpers[16] = {
*/
static void * const qemu_st_helpers[16] = {
#ifdef _MSC_VER
helper_ret_stb_mmu, // MO_UB
helper_ret_stb_mmu, // MO_UB
# ifdef HOST_WORDS_BIGENDIAN
helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ
0, // MO_SB
0, // MO_BESW
0, // MO_BESL
0, // n/a
0, // n/a
helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ
0, // n/a
0, // MO_LESW
0, // MO_LESL
0, // n/a
helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ
0, // MO_SB
0, // MO_BESW
0, // MO_BESL
0, // n/a
0, // n/a
helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ
0, // n/a
0, // MO_LESW
0, // MO_LESL
0, // n/a
# else // !HOST_WORDS_BIGENDIAN
helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ
0, // MO_SB
0, // MO_LESW
0, // MO_LESL
0, // n/a
0, // n/a
helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ
0, // n/a
0, // MO_BESW
0, // MO_BESL
0, // n/a
helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ
0, // MO_SB
0, // MO_LESW
0, // MO_LESL
0, // n/a
0, // n/a
helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ
0, // n/a
0, // MO_BESW
0, // MO_BESL
0, // n/a
# endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER
@ -2356,8 +2356,8 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
/* jmp *tb. */
tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ stack_addend);
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ stack_addend);
#else
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
@ -2387,12 +2387,12 @@ static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
unsigned a, b, c, d;
int max;
int max;
#ifdef _MSC_VER
int cpu_info[4];
__cpuid(cpu_info, 0);
max = cpu_info[0];
max = cpu_info[0];
#else
max = __get_cpuid_max(0, 0);
#endif

30
qemu/tcg/sparc/tcg-target.c
View File

@ -405,7 +405,7 @@ static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
}
static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
int32_t val2, int val2const, int op)
int32_t val2, int val2const, int op)
{
tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
| (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
@ -682,7 +682,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
}
c1 = TCG_REG_G0, c2const = 0;
cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
break;
break;
case TCG_COND_GTU:
case TCG_COND_LEU:
@ -783,16 +783,16 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
}
tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
} else if (bh == TCG_REG_G0) {
/* If we have a zero, we can perform the operation in two insns,
/* If we have a zero, we can perform the operation in two insns,
with the arithmetic first, and a conditional move into place. */
if (rh == ah) {
if (rh == ah) {
tcg_out_arithi(s, TCG_REG_T2, ah, 1,
is_sub ? ARITH_SUB : ARITH_ADD);
is_sub ? ARITH_SUB : ARITH_ADD);
tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
} else {
} else {
tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
}
tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
}
} else {
/* Otherwise adjust BH as if there is carry into T2 ... */
if (bhconst) {
@ -803,7 +803,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
}
/* ... smoosh T2 back to original BH if carry is clear ... */
tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
/* ... and finally perform the arithmetic with the new operand. */
/* ... and finally perform the arithmetic with the new operand. */
tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
}
@ -1315,11 +1315,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
goto gen_arith;
OP_32_64(neg):
c = ARITH_SUB;
goto gen_arith1;
c = ARITH_SUB;
goto gen_arith1;
OP_32_64(not):
c = ARITH_ORN;
goto gen_arith1;
c = ARITH_ORN;
goto gen_arith1;
case INDEX_op_div_i32:
tcg_out_div32(s, a0, a1, a2, c2, 0);
@ -1445,8 +1445,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
gen_arith1:
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64:

4
qemu/tcg/sparc/tcg-target.h
View File

@ -152,12 +152,12 @@ extern bool use_vis3_instructions;
#include <windows.h>
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start);
FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start);
}
#else
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
uintptr_t p;
uintptr_t p;
for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
__asm__ __volatile__("flush\t%0" : : "r" (p));
}

106
qemu/tcg/tcg.c
View File

@ -70,7 +70,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
/* The CIE and FDE header definitions will be common to all hosts. */
typedef struct {
//uint32_t QEMU_ALIGN(sizeof(void *), len);
uint32_t QEMU_ALIGN(8, len);
uint32_t QEMU_ALIGN(8, len);
uint32_t id;
uint8_t version;
char augmentation[1];
@ -81,7 +81,7 @@ typedef struct {
QEMU_PACK( typedef struct {
// uint32_t QEMU_ALIGN(sizeof(void *), len);
uint32_t QEMU_ALIGN(8, len);
uint32_t QEMU_ALIGN(8, len);
uint32_t cie_offset;
uintptr_t func_start;
uintptr_t func_len;
@ -1100,22 +1100,22 @@ static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
static const char * const cond_name[] =
{
#ifdef _MSC_VER
"never", // TCG_COND_NEVER
"always", // TCG_COND_ALWAYS
"lt", // TCG_COND_LT
"ge", // TCG_COND_GE
"ltu", // TCG_COND_LTU
"geu", // TCG_COND_GEU
NULL, // n/a
NULL, // n/a
"eq", // TCG_COND_EQ
"ne", // TCG_COND_NE
"le", // TCG_COND_LE
"gt", // TCG_COND_GT
"leu", // TCG_COND_LEU
"gtu", // TCG_COND_GTU
NULL, // n/a
NULL, // n/a
"never", // TCG_COND_NEVER
"always", // TCG_COND_ALWAYS
"lt", // TCG_COND_LT
"ge", // TCG_COND_GE
"ltu", // TCG_COND_LTU
"geu", // TCG_COND_GEU
NULL, // n/a
NULL, // n/a
"eq", // TCG_COND_EQ
"ne", // TCG_COND_NE
"le", // TCG_COND_LE
"gt", // TCG_COND_GT
"leu", // TCG_COND_LEU
"gtu", // TCG_COND_GTU
NULL, // n/a
NULL, // n/a
#else
[TCG_COND_NEVER] = "never",
[TCG_COND_ALWAYS] = "always",
@ -1135,43 +1135,43 @@ static const char * const cond_name[] =
static const char * const ldst_name[] =
{
#ifdef _MSC_VER
"ub", // MO_UB
"ub", // MO_UB
# ifdef HOST_WORDS_BIGENDIAN
"beuw", // MO_BEUW
"beul", // MO_BEUL
"beq", // MO_BEQ
"sb", // MO_SB
"besw", // MO_BESW
"besl", // MO_BESL
NULL, // n/a
NULL, // n/a
"leuw", // MO_LEUW
"leul", // MO_LEUL
"leq", // MO_LEQ
NULL, // n/a
"lesw", // MO_LESW
"lesl", // MO_LESL
NULL, // n/a
"beuw", // MO_BEUW
"beul", // MO_BEUL
"beq", // MO_BEQ
"sb", // MO_SB
"besw", // MO_BESW
"besl", // MO_BESL
NULL, // n/a
NULL, // n/a
"leuw", // MO_LEUW
"leul", // MO_LEUL
"leq", // MO_LEQ
NULL, // n/a
"lesw", // MO_LESW
"lesl", // MO_LESL
NULL, // n/a
# else // !HOST_WORDS_BIGENDIAN
"leuw", // MO_LEUW
"leul", // MO_LEUL
"leq", // MO_LEQ
"sb", // MO_SB
"lesw", // MO_LESW
"lesl", // MO_LESL
NULL, // n/a
NULL, // n/a
"beuw", // MO_BEUW
"beul", // MO_BEUL
"beq", // MO_BEQ
NULL, // n/a
"besw", // MO_BESW
"besl", // MO_BESL
NULL, // n/a
"leuw", // MO_LEUW
"leul", // MO_LEUL
"leq", // MO_LEQ
"sb", // MO_SB
"lesw", // MO_LESW
"lesl", // MO_LESL
NULL, // n/a
NULL, // n/a
"beuw", // MO_BEUW
"beul", // MO_BEUL
"beq", // MO_BEQ
NULL, // n/a
"besw", // MO_BESW
"besl", // MO_BESL
NULL, // n/a
# endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER
[MO_UB] = "ub",
[MO_UB] = "ub",
[MO_SB] = "sb",
[MO_LEUW] = "leuw",
[MO_LESW] = "lesw",
@ -2376,10 +2376,10 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
#if TCG_TARGET_REG_BITS == 32
// do this because msvc cannot have arrays with 0 entries.
nb_regs = 0;
// do this because msvc cannot have arrays with 0 entries.
nb_regs = 0;
#endif
if (nb_regs > nb_params) {
if (nb_regs > nb_params) {
nb_regs = nb_params;
}