fix conflicts when merging map-ptr branch to master branch
This commit is contained in:
@ -86,6 +86,9 @@ void memory_unmap(struct uc_struct *uc, MemoryRegion *mr)
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uc->mapped_block_count--;
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//shift remainder of array down over deleted pointer
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memcpy(&uc->mapped_blocks[i], &uc->mapped_blocks[i + 1], sizeof(MemoryRegion*) * (uc->mapped_block_count - i));
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mr->destructor(mr);
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g_free((char *)mr->name);
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g_free(mr->ioeventfds);
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break;
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}
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}
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@ -93,13 +96,20 @@ void memory_unmap(struct uc_struct *uc, MemoryRegion *mr)
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int memory_free(struct uc_struct *uc)
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{
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MemoryRegion *mr;
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int i;
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get_system_memory(uc)->enabled = false;
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for (i = 0; i < uc->mapped_block_count; i++) {
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uc->mapped_blocks[i]->enabled = false;
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memory_region_del_subregion(get_system_memory(uc), uc->mapped_blocks[i]);
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g_free(uc->mapped_blocks[i]);
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mr = uc->mapped_blocks[i];
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mr->enabled = false;
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memory_region_del_subregion(get_system_memory(uc), mr);
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mr->destructor(mr);
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g_free((char *)mr->name);
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g_free(mr->ioeventfds);
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g_free(mr);
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}
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return 0;
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}
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@ -11322,7 +11322,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
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return 4;
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}
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static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot)
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static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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@ -11343,10 +11343,12 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_s
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n_bytes = 2;
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// Unicorn: trace this instruction on request
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if (!is_bc_slot && env->uc->hook_insn) {
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if (env->uc->hook_insn) {
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struct hook_struct *trace = hook_find(env->uc, UC_HOOK_CODE, ctx->pc);
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if (trace)
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if (trace) {
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, trace->callback, env->uc, ctx->pc, trace->user_data);
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*insn_need_patch = true;
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}
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// if requested to emulate only some instructions, check if
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// we need to exit immediately
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if (env->uc->emu_count > 0) {
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@ -13928,7 +13930,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
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}
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}
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static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot)
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static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
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{
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
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@ -13943,10 +13945,12 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool is_b
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}
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// Unicorn: trace this instruction on request
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if (!is_bc_slot && env->uc->hook_insn) {
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if (env->uc->hook_insn) {
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struct hook_struct *trace = hook_find(env->uc, UC_HOOK_CODE, ctx->pc);
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if (trace)
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if (trace) {
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, trace->callback, env->uc, ctx->pc, trace->user_data);
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*insn_need_patch = true;
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}
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// if requested to emulate only some instructions, check if
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// we need to exit immediately
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if (env->uc->emu_count > 0) {
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@ -18503,7 +18507,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot)
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static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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#if defined(TARGET_MIPS64)
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@ -18514,7 +18518,6 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot)
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uint32_t op, op1;
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int16_t imm;
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/* make sure instructions are on a word boundary */
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if (ctx->pc & 0x3) {
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env->CP0_BadVAddr = ctx->pc;
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@ -18523,10 +18526,12 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot)
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}
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// Unicorn: trace this instruction on request
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if (!is_bc_slot && env->uc->hook_insn) {
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if (env->uc->hook_insn) {
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struct hook_struct *trace = hook_find(env->uc, UC_HOOK_CODE, ctx->pc);
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if (trace)
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if (trace) {
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gen_uc_tracecode(tcg_ctx, 0xf8f8f8f8, trace->callback, env->uc, ctx->pc, trace->user_data);
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*insn_need_patch = true;
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}
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// if requested to emulate only some instructions, check if
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// we need to exit immediately
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if (env->uc->emu_count > 0) {
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@ -19171,7 +19176,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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int max_insns;
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int insn_bytes;
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int is_slot = 0;
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bool is_bc_slot = false;
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TCGContext *tcg_ctx = env->uc->tcg_ctx;
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TCGArg *save_opparam_ptr = NULL;
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bool block_full = false;
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@ -19268,23 +19272,23 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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ctx.bstate = BS_EXCP;
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break;
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} else {
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bool insn_need_patch = false;
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// Unicorn: save param buffer
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if (env->uc->hook_insn)
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save_opparam_ptr = tcg_ctx->gen_opparam_ptr;
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is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
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is_bc_slot = (is_slot & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BC;
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if (!(ctx.hflags & MIPS_HFLAG_M16)) {
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ctx.opcode = cpu_ldl_code(env, ctx.pc);
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insn_bytes = 4;
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decode_opc(env, &ctx, is_bc_slot);
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decode_opc(env, &ctx, &insn_need_patch);
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} else if (ctx.insn_flags & ASE_MICROMIPS) {
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ctx.opcode = cpu_lduw_code(env, ctx.pc);
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insn_bytes = decode_micromips_opc(env, &ctx, is_bc_slot);
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insn_bytes = decode_micromips_opc(env, &ctx, &insn_need_patch);
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} else if (ctx.insn_flags & ASE_MIPS16) {
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ctx.opcode = cpu_lduw_code(env, ctx.pc);
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insn_bytes = decode_mips16_opc(env, &ctx, is_bc_slot);
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insn_bytes = decode_mips16_opc(env, &ctx, &insn_need_patch);
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} else {
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generate_exception(&ctx, EXCP_RI);
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ctx.bstate = BS_STOP;
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@ -19292,7 +19296,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
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}
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// Unicorn: patch the callback for the instruction size
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if (!is_bc_slot && env->uc->hook_insn)
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if (insn_need_patch)
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*(save_opparam_ptr + 1) = insn_bytes;
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}
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@ -20,6 +20,11 @@
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#include "cpu.h"
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#include "exec/helper-proto.h"
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static uint32_t compute_null(CPUSPARCState *env)
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{
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return 0;
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}
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static uint32_t compute_all_flags(CPUSPARCState *env)
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{
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return env->psr & PSR_ICC;
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@ -433,6 +438,7 @@ typedef struct CCTable {
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static const CCTable icc_table[CC_OP_NB] = {
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/* CC_OP_DYNAMIC should never happen */
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[CC_OP_DYNAMIC] = { compute_null, compute_null },
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[CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
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[CC_OP_DIV] = { compute_all_div, compute_C_div },
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[CC_OP_ADD] = { compute_all_add, compute_C_add },
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@ -449,6 +455,7 @@ static const CCTable icc_table[CC_OP_NB] = {
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#ifdef TARGET_SPARC64
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static const CCTable xcc_table[CC_OP_NB] = {
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/* CC_OP_DYNAMIC should never happen */
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[CC_OP_DYNAMIC] = { compute_null, compute_null },
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[CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
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[CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic },
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[CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
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@ -807,6 +807,9 @@ static void page_flush_tb(struct uc_struct *uc)
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{
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int i;
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if (uc->l1_map == NULL)
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return;
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for (i = 0; i < V_L1_SIZE; i++) {
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page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, uc->l1_map + i);
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}
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