diff --git a/qemu/target-arm/cpu64.c b/qemu/target-arm/cpu64.c
index 05d67a7b..30948ae3 100644
--- a/qemu/target-arm/cpu64.c
+++ b/qemu/target-arm/cpu64.c
@@ -163,8 +163,8 @@ static void aarch64_cpu_finalizefn(struct uc_struct *uc, Object *obj, void *opaq
 
 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
 {
-    CPUARMState *env = cs->env_ptr;
-    ARMCPU *cpu = ARM_CPU(env->uc, cs);
+    //CPUARMState *env = cs->env_ptr;
+    ARMCPU *cpu = ARM_CPU(NULL, cs);
     /* It's OK to look at env for the current mode here, because it's
      * never possible for an AArch64 TB to chain to an AArch32 TB.
      * (Otherwise we would need to use synchronize_from_tb instead.)
diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c
index 27527811..8e0eb5b8 100644
--- a/qemu/target-arm/translate.c
+++ b/qemu/target-arm/translate.c
@@ -2692,8 +2692,8 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
 // on msvc, so is replaced with separate versions for the shift to perform.
 //#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
 #if 0
-//#define VFP_SREG(insn, bigbit, smallbit) \
-//  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+#define VFP_SREG(insn, bigbit, smallbit) \
+  ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
 #endif
 
 #define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))