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Split mips cpu to 32 and 64

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This commit is contained in:
lazymio
2021-11-04 19:58:32 +01:00
parent 0555095388
commit 871de4ad65
2 changed files with 41 additions and 33 deletions
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65
include/unicorn/mips.h
View File

@ -19,37 +19,40 @@ extern "C" {
#pragma warning(disable : 4201) #pragma warning(disable : 4201)
#endif #endif
typedef enum uc_cpu_mips { typedef enum uc_cpu_mips32 {
UC_CPU_MIPS_4KC = 0, UC_CPU_MIPS32_4KC = 0,
UC_CPU_MIPS_4KM, UC_CPU_MIPS32_4KM,
UC_CPU_MIPS_4KECR1, UC_CPU_MIPS32_4KECR1,
UC_CPU_MIPS_4KEMR1, UC_CPU_MIPS32_4KEMR1,
UC_CPU_MIPS_4KEC, UC_CPU_MIPS32_4KEC,
UC_CPU_MIPS_4KEM, UC_CPU_MIPS32_4KEM,
UC_CPU_MIPS_24KC, UC_CPU_MIPS32_24KC,
UC_CPU_MIPS_24KEC, UC_CPU_MIPS32_24KEC,
UC_CPU_MIPS_24KF, UC_CPU_MIPS32_24KF,
UC_CPU_MIPS_34KF, UC_CPU_MIPS32_34KF,
UC_CPU_MIPS_74KF, UC_CPU_MIPS32_74KF,
UC_CPU_MIPS_M14K, UC_CPU_MIPS32_M14K,
UC_CPU_MIPS_M14KC, UC_CPU_MIPS32_M14KC,
UC_CPU_MIPS_P5600, UC_CPU_MIPS32_P5600,
UC_CPU_MIPS_MIPS32R6_GENERIC, UC_CPU_MIPS32_MIPS32R6_GENERIC,
UC_CPU_MIPS_I7200, UC_CPU_MIPS32_I7200,
UC_CPU_MIPS_R4000, } uc_cpu_mips32;
UC_CPU_MIPS_VR5432,
UC_CPU_MIPS_5KC, typedef enum uc_cpu_mips64 {
UC_CPU_MIPS_5KF, UC_CPU_MIPS64_R4000 = 0,
UC_CPU_MIPS_20KC, UC_CPU_MIPS64_VR5432,
UC_CPU_MIPS_MIPS64R2_GENERIC, UC_CPU_MIPS64_5KC,
UC_CPU_MIPS_5KEC, UC_CPU_MIPS64_5KF,
UC_CPU_MIPS_5KEF, UC_CPU_MIPS64_20KC,
UC_CPU_MIPS_I6400, UC_CPU_MIPS64_MIPS64R2_GENERIC,
UC_CPU_MIPS_I6500, UC_CPU_MIPS64_5KEC,
UC_CPU_MIPS_LOONGSON_2E, UC_CPU_MIPS64_5KEF,
UC_CPU_MIPS_LOONGSON_2F, UC_CPU_MIPS64_I6400,
UC_CPU_MIPS_MIPS64DSPR2 UC_CPU_MIPS64_I6500,
} uc_cpu_mips; UC_CPU_MIPS64_LOONGSON_2E,
UC_CPU_MIPS64_LOONGSON_2F,
UC_CPU_MIPS64_MIPS64DSPR2
} uc_cpu_mips64;
//> MIPS registers //> MIPS registers
typedef enum UC_MIPS_REG { typedef enum UC_MIPS_REG {

9
qemu/target/mips/cpu.c
View File

@ -162,16 +162,21 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc)
return NULL; return NULL;
} }
if (uc->cpu_model == INT_MAX) {
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 17; // R4000 uc->cpu_model = 17; // R4000
} else if (uc->cpu_model + UC_CPU_MIPS32_I7200 + 1 >= mips_defs_number ) {
free(cpu);
return NULL;
}
#else #else
if (uc->cpu_model == INT_MAX) {
uc->cpu_model = 10; // 74kf uc->cpu_model = 10; // 74kf
#endif
} else if (uc->cpu_model >= mips_defs_number) { } else if (uc->cpu_model >= mips_defs_number) {
free(cpu); free(cpu);
return NULL; return NULL;
} }
#endif
cs = (CPUState *)cpu; cs = (CPUState *)cpu;
cc = (CPUClass *)&cpu->cc; cc = (CPUClass *)&cpu->cc;