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mips: remove unused variable is_bc_slot

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This commit is contained in:
Nguyen Anh Quynh
2015-12-16 23:06:17 +08:00
parent 7b73a298c1
commit 8d3265d9e1
1 changed files with 6 additions and 8 deletions
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14
qemu/target-mips/translate.c
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@ -11322,7 +11322,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
return 4; return 4;
} }
static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot, bool *insn_need_patch) static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr; TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
@ -13930,7 +13930,7 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx,
} }
} }
static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot, bool *insn_need_patch) static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
{ {
TCGContext *tcg_ctx = env->uc->tcg_ctx; TCGContext *tcg_ctx = env->uc->tcg_ctx;
TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr; TCGv **cpu_gpr = (TCGv **)tcg_ctx->cpu_gpr;
@ -18507,7 +18507,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
} }
} }
static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool is_bc_slot, bool *insn_need_patch) static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch)
{ {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx; TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
@ -19176,7 +19176,6 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
int max_insns; int max_insns;
int insn_bytes; int insn_bytes;
int is_slot = 0; int is_slot = 0;
bool is_bc_slot = false;
TCGContext *tcg_ctx = env->uc->tcg_ctx; TCGContext *tcg_ctx = env->uc->tcg_ctx;
TCGArg *save_opparam_ptr = NULL; TCGArg *save_opparam_ptr = NULL;
bool block_full = false; bool block_full = false;
@ -19279,18 +19278,17 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
save_opparam_ptr = tcg_ctx->gen_opparam_ptr; save_opparam_ptr = tcg_ctx->gen_opparam_ptr;
is_slot = ctx.hflags & MIPS_HFLAG_BMASK; is_slot = ctx.hflags & MIPS_HFLAG_BMASK;
is_bc_slot = (is_slot & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BC;
if (!(ctx.hflags & MIPS_HFLAG_M16)) { if (!(ctx.hflags & MIPS_HFLAG_M16)) {
ctx.opcode = cpu_ldl_code(env, ctx.pc); ctx.opcode = cpu_ldl_code(env, ctx.pc);
insn_bytes = 4; insn_bytes = 4;
decode_opc(env, &ctx, is_bc_slot, &insn_need_patch); decode_opc(env, &ctx, &insn_need_patch);
} else if (ctx.insn_flags & ASE_MICROMIPS) { } else if (ctx.insn_flags & ASE_MICROMIPS) {
ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.opcode = cpu_lduw_code(env, ctx.pc);
insn_bytes = decode_micromips_opc(env, &ctx, is_bc_slot, &insn_need_patch); insn_bytes = decode_micromips_opc(env, &ctx, &insn_need_patch);
} else if (ctx.insn_flags & ASE_MIPS16) { } else if (ctx.insn_flags & ASE_MIPS16) {
ctx.opcode = cpu_lduw_code(env, ctx.pc); ctx.opcode = cpu_lduw_code(env, ctx.pc);
insn_bytes = decode_mips16_opc(env, &ctx, is_bc_slot, &insn_need_patch); insn_bytes = decode_mips16_opc(env, &ctx, &insn_need_patch);
} else { } else {
generate_exception(&ctx, EXCP_RI); generate_exception(&ctx, EXCP_RI);
ctx.bstate = BS_STOP; ctx.bstate = BS_STOP;