Merge with current master.

This commit is contained in:
xorstream
2017-01-20 18:22:28 +11:00
115 changed files with 7 additions and 10001 deletions

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@ -1,3 +1 @@
#common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
#obj-$(CONFIG_IOAPIC) += ioapic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o

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@ -1,2 +1,2 @@
obj-y += mips_r4k.o
obj-y += addr.o cputimer.o mips_int.o
obj-y += addr.o cputimer.o

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@ -129,38 +129,3 @@ void cpu_mips_stop_count(CPUMIPSState *env)
env->CP0_Count += (uint32_t)muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
TIMER_FREQ, get_ticks_per_sec());
}
#if 0
static void mips_timer_cb (void *opaque)
{
CPUMIPSState *env;
env = opaque;
#if 0
qemu_log("%s\n", __func__);
#endif
if (env->CP0_Cause & (1 << CP0Ca_DC))
return;
/* ??? This callback should occur when the counter is exactly equal to
the comparator value. Offset the count by one to avoid immediately
retriggering the callback before any virtual time has passed. */
env->CP0_Count++;
cpu_mips_timer_expire(env);
env->CP0_Count--;
}
#endif
void cpu_mips_clock_init (CPUMIPSState *env)
{
#if 0
/*
* If we're in KVM mode, don't create the periodic timer, that is handled in
* kernel.
*/
if (!kvm_enabled()) {
env->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &mips_timer_cb, env);
}
#endif
}

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@ -1,82 +0,0 @@
/*
* QEMU MIPS interrupt support
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
#include "hw/hw.h"
#include "hw/mips/cpudevs.h"
#include "cpu.h"
//#include "kvm_mips.h"
#if 0
static void cpu_mips_irq_request(void *opaque, int irq, int level)
{
MIPSCPU *cpu = opaque;
CPUMIPSState *env = &cpu->env;
CPUState *cs = CPU(cpu);
if (irq < 0 || irq > 7)
return;
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
if (kvm_enabled() && irq == 2) {
kvm_mips_set_interrupt(cpu, irq, level);
}
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
if (kvm_enabled() && irq == 2) {
kvm_mips_set_interrupt(cpu, irq, level);
}
}
if (env->CP0_Cause & CP0Ca_IP_mask) {
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
} else {
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
}
}
#endif
void cpu_mips_irq_init_cpu(CPUMIPSState *env)
{
#if 0
qemu_irq *qi;
int i;
qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8);
for (i = 0; i < 8; i++) {
env->irq[i] = qi[i];
}
#endif
}
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level)
{
#if 0
if (irq < 0 || irq > 2) {
return;
}
qemu_set_irq(env->irq[irq], level);
#endif
}

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@ -14,7 +14,6 @@
#include "hw/hw.h"
#include "hw/mips/mips.h"
#include "hw/mips/cpudevs.h"
#include "hw/mips/bios.h"
#include "sysemu/sysemu.h"
#include "hw/boards.h"
#include "exec/address-spaces.h"