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mothran
2015-08-23 21:42:02 -07:00
parent c5775a371e a167f7c456
commit 995924176a
29 changed files with 4130 additions and 4128 deletions
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242
include/unicorn/arm.h
View File

@ -13,131 +13,131 @@ extern "C" {
#endif
//> ARM registers
typedef enum arm_reg {
ARM_REG_INVALID = 0,
ARM_REG_APSR,
ARM_REG_APSR_NZCV,
ARM_REG_CPSR,
ARM_REG_FPEXC,
ARM_REG_FPINST,
ARM_REG_FPSCR,
ARM_REG_FPSCR_NZCV,
ARM_REG_FPSID,
ARM_REG_ITSTATE,
ARM_REG_LR,
ARM_REG_PC,
ARM_REG_SP,
ARM_REG_SPSR,
ARM_REG_D0,
ARM_REG_D1,
ARM_REG_D2,
ARM_REG_D3,
ARM_REG_D4,
ARM_REG_D5,
ARM_REG_D6,
ARM_REG_D7,
ARM_REG_D8,
ARM_REG_D9,
ARM_REG_D10,
ARM_REG_D11,
ARM_REG_D12,
ARM_REG_D13,
ARM_REG_D14,
ARM_REG_D15,
ARM_REG_D16,
ARM_REG_D17,
ARM_REG_D18,
ARM_REG_D19,
ARM_REG_D20,
ARM_REG_D21,
ARM_REG_D22,
ARM_REG_D23,
ARM_REG_D24,
ARM_REG_D25,
ARM_REG_D26,
ARM_REG_D27,
ARM_REG_D28,
ARM_REG_D29,
ARM_REG_D30,
ARM_REG_D31,
ARM_REG_FPINST2,
ARM_REG_MVFR0,
ARM_REG_MVFR1,
ARM_REG_MVFR2,
ARM_REG_Q0,
ARM_REG_Q1,
ARM_REG_Q2,
ARM_REG_Q3,
ARM_REG_Q4,
ARM_REG_Q5,
ARM_REG_Q6,
ARM_REG_Q7,
ARM_REG_Q8,
ARM_REG_Q9,
ARM_REG_Q10,
ARM_REG_Q11,
ARM_REG_Q12,
ARM_REG_Q13,
ARM_REG_Q14,
ARM_REG_Q15,
ARM_REG_R0,
ARM_REG_R1,
ARM_REG_R2,
ARM_REG_R3,
ARM_REG_R4,
ARM_REG_R5,
ARM_REG_R6,
ARM_REG_R7,
ARM_REG_R8,
ARM_REG_R9,
ARM_REG_R10,
ARM_REG_R11,
ARM_REG_R12,
ARM_REG_S0,
ARM_REG_S1,
ARM_REG_S2,
ARM_REG_S3,
ARM_REG_S4,
ARM_REG_S5,
ARM_REG_S6,
ARM_REG_S7,
ARM_REG_S8,
ARM_REG_S9,
ARM_REG_S10,
ARM_REG_S11,
ARM_REG_S12,
ARM_REG_S13,
ARM_REG_S14,
ARM_REG_S15,
ARM_REG_S16,
ARM_REG_S17,
ARM_REG_S18,
ARM_REG_S19,
ARM_REG_S20,
ARM_REG_S21,
ARM_REG_S22,
ARM_REG_S23,
ARM_REG_S24,
ARM_REG_S25,
ARM_REG_S26,
ARM_REG_S27,
ARM_REG_S28,
ARM_REG_S29,
ARM_REG_S30,
ARM_REG_S31,
typedef enum uc_arm_reg {
UC_ARM_REG_INVALID = 0,
UC_ARM_REG_APSR,
UC_ARM_REG_APSR_NZCV,
UC_ARM_REG_CPSR,
UC_ARM_REG_FPEXC,
UC_ARM_REG_FPINST,
UC_ARM_REG_FPSCR,
UC_ARM_REG_FPSCR_NZCV,
UC_ARM_REG_FPSID,
UC_ARM_REG_ITSTATE,
UC_ARM_REG_LR,
UC_ARM_REG_PC,
UC_ARM_REG_SP,
UC_ARM_REG_SPSR,
UC_ARM_REG_D0,
UC_ARM_REG_D1,
UC_ARM_REG_D2,
UC_ARM_REG_D3,
UC_ARM_REG_D4,
UC_ARM_REG_D5,
UC_ARM_REG_D6,
UC_ARM_REG_D7,
UC_ARM_REG_D8,
UC_ARM_REG_D9,
UC_ARM_REG_D10,
UC_ARM_REG_D11,
UC_ARM_REG_D12,
UC_ARM_REG_D13,
UC_ARM_REG_D14,
UC_ARM_REG_D15,
UC_ARM_REG_D16,
UC_ARM_REG_D17,
UC_ARM_REG_D18,
UC_ARM_REG_D19,
UC_ARM_REG_D20,
UC_ARM_REG_D21,
UC_ARM_REG_D22,
UC_ARM_REG_D23,
UC_ARM_REG_D24,
UC_ARM_REG_D25,
UC_ARM_REG_D26,
UC_ARM_REG_D27,
UC_ARM_REG_D28,
UC_ARM_REG_D29,
UC_ARM_REG_D30,
UC_ARM_REG_D31,
UC_ARM_REG_FPINST2,
UC_ARM_REG_MVFR0,
UC_ARM_REG_MVFR1,
UC_ARM_REG_MVFR2,
UC_ARM_REG_Q0,
UC_ARM_REG_Q1,
UC_ARM_REG_Q2,
UC_ARM_REG_Q3,
UC_ARM_REG_Q4,
UC_ARM_REG_Q5,
UC_ARM_REG_Q6,
UC_ARM_REG_Q7,
UC_ARM_REG_Q8,
UC_ARM_REG_Q9,
UC_ARM_REG_Q10,
UC_ARM_REG_Q11,
UC_ARM_REG_Q12,
UC_ARM_REG_Q13,
UC_ARM_REG_Q14,
UC_ARM_REG_Q15,
UC_ARM_REG_R0,
UC_ARM_REG_R1,
UC_ARM_REG_R2,
UC_ARM_REG_R3,
UC_ARM_REG_R4,
UC_ARM_REG_R5,
UC_ARM_REG_R6,
UC_ARM_REG_R7,
UC_ARM_REG_R8,
UC_ARM_REG_R9,
UC_ARM_REG_R10,
UC_ARM_REG_R11,
UC_ARM_REG_R12,
UC_ARM_REG_S0,
UC_ARM_REG_S1,
UC_ARM_REG_S2,
UC_ARM_REG_S3,
UC_ARM_REG_S4,
UC_ARM_REG_S5,
UC_ARM_REG_S6,
UC_ARM_REG_S7,
UC_ARM_REG_S8,
UC_ARM_REG_S9,
UC_ARM_REG_S10,
UC_ARM_REG_S11,
UC_ARM_REG_S12,
UC_ARM_REG_S13,
UC_ARM_REG_S14,
UC_ARM_REG_S15,
UC_ARM_REG_S16,
UC_ARM_REG_S17,
UC_ARM_REG_S18,
UC_ARM_REG_S19,
UC_ARM_REG_S20,
UC_ARM_REG_S21,
UC_ARM_REG_S22,
UC_ARM_REG_S23,
UC_ARM_REG_S24,
UC_ARM_REG_S25,
UC_ARM_REG_S26,
UC_ARM_REG_S27,
UC_ARM_REG_S28,
UC_ARM_REG_S29,
UC_ARM_REG_S30,
UC_ARM_REG_S31,
ARM_REG_ENDING, // <-- mark the end of the list or registers
UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
//> alias registers
ARM_REG_R13 = ARM_REG_SP,
ARM_REG_R14 = ARM_REG_LR,
ARM_REG_R15 = ARM_REG_PC,
UC_ARM_REG_R13 = UC_ARM_REG_SP,
UC_ARM_REG_R14 = UC_ARM_REG_LR,
UC_ARM_REG_R15 = UC_ARM_REG_PC,
ARM_REG_SB = ARM_REG_R9,
ARM_REG_SL = ARM_REG_R10,
ARM_REG_FP = ARM_REG_R11,
ARM_REG_IP = ARM_REG_R12,
} arm_reg;
UC_ARM_REG_SB = UC_ARM_REG_R9,
UC_ARM_REG_SL = UC_ARM_REG_R10,
UC_ARM_REG_FP = UC_ARM_REG_R11,
UC_ARM_REG_IP = UC_ARM_REG_R12,
} uc_arm_reg;
#ifdef __cplusplus
}

536
include/unicorn/arm64.h
View File

@ -13,282 +13,282 @@ extern "C" {
#endif
//> ARM64 registers
typedef enum arm64_reg {
ARM64_REG_INVALID = 0,
typedef enum uc_arm64_reg {
UC_ARM64_REG_INVALID = 0,
ARM64_REG_X29,
ARM64_REG_X30,
ARM64_REG_NZCV,
ARM64_REG_SP,
ARM64_REG_WSP,
ARM64_REG_WZR,
ARM64_REG_XZR,
ARM64_REG_B0,
ARM64_REG_B1,
ARM64_REG_B2,
ARM64_REG_B3,
ARM64_REG_B4,
ARM64_REG_B5,
ARM64_REG_B6,
ARM64_REG_B7,
ARM64_REG_B8,
ARM64_REG_B9,
ARM64_REG_B10,
ARM64_REG_B11,
ARM64_REG_B12,
ARM64_REG_B13,
ARM64_REG_B14,
ARM64_REG_B15,
ARM64_REG_B16,
ARM64_REG_B17,
ARM64_REG_B18,
ARM64_REG_B19,
ARM64_REG_B20,
ARM64_REG_B21,
ARM64_REG_B22,
ARM64_REG_B23,
ARM64_REG_B24,
ARM64_REG_B25,
ARM64_REG_B26,
ARM64_REG_B27,
ARM64_REG_B28,
ARM64_REG_B29,
ARM64_REG_B30,
ARM64_REG_B31,
ARM64_REG_D0,
ARM64_REG_D1,
ARM64_REG_D2,
ARM64_REG_D3,
ARM64_REG_D4,
ARM64_REG_D5,
ARM64_REG_D6,
ARM64_REG_D7,
ARM64_REG_D8,
ARM64_REG_D9,
ARM64_REG_D10,
ARM64_REG_D11,
ARM64_REG_D12,
ARM64_REG_D13,
ARM64_REG_D14,
ARM64_REG_D15,
ARM64_REG_D16,
ARM64_REG_D17,
ARM64_REG_D18,
ARM64_REG_D19,
ARM64_REG_D20,
ARM64_REG_D21,
ARM64_REG_D22,
ARM64_REG_D23,
ARM64_REG_D24,
ARM64_REG_D25,
ARM64_REG_D26,
ARM64_REG_D27,
ARM64_REG_D28,
ARM64_REG_D29,
ARM64_REG_D30,
ARM64_REG_D31,
ARM64_REG_H0,
ARM64_REG_H1,
ARM64_REG_H2,
ARM64_REG_H3,
ARM64_REG_H4,
ARM64_REG_H5,
ARM64_REG_H6,
ARM64_REG_H7,
ARM64_REG_H8,
ARM64_REG_H9,
ARM64_REG_H10,
ARM64_REG_H11,
ARM64_REG_H12,
ARM64_REG_H13,
ARM64_REG_H14,
ARM64_REG_H15,
ARM64_REG_H16,
ARM64_REG_H17,
ARM64_REG_H18,
ARM64_REG_H19,
ARM64_REG_H20,
ARM64_REG_H21,
ARM64_REG_H22,
ARM64_REG_H23,
ARM64_REG_H24,
ARM64_REG_H25,
ARM64_REG_H26,
ARM64_REG_H27,
ARM64_REG_H28,
ARM64_REG_H29,
ARM64_REG_H30,
ARM64_REG_H31,
ARM64_REG_Q0,
ARM64_REG_Q1,
ARM64_REG_Q2,
ARM64_REG_Q3,
ARM64_REG_Q4,
ARM64_REG_Q5,
ARM64_REG_Q6,
ARM64_REG_Q7,
ARM64_REG_Q8,
ARM64_REG_Q9,
ARM64_REG_Q10,
ARM64_REG_Q11,
ARM64_REG_Q12,
ARM64_REG_Q13,
ARM64_REG_Q14,
ARM64_REG_Q15,
ARM64_REG_Q16,
ARM64_REG_Q17,
ARM64_REG_Q18,
ARM64_REG_Q19,
ARM64_REG_Q20,
ARM64_REG_Q21,
ARM64_REG_Q22,
ARM64_REG_Q23,
ARM64_REG_Q24,
ARM64_REG_Q25,
ARM64_REG_Q26,
ARM64_REG_Q27,
ARM64_REG_Q28,
ARM64_REG_Q29,
ARM64_REG_Q30,
ARM64_REG_Q31,
ARM64_REG_S0,
ARM64_REG_S1,
ARM64_REG_S2,
ARM64_REG_S3,
ARM64_REG_S4,
ARM64_REG_S5,
ARM64_REG_S6,
ARM64_REG_S7,
ARM64_REG_S8,
ARM64_REG_S9,
ARM64_REG_S10,
ARM64_REG_S11,
ARM64_REG_S12,
ARM64_REG_S13,
ARM64_REG_S14,
ARM64_REG_S15,
ARM64_REG_S16,
ARM64_REG_S17,
ARM64_REG_S18,
ARM64_REG_S19,
ARM64_REG_S20,
ARM64_REG_S21,
ARM64_REG_S22,
ARM64_REG_S23,
ARM64_REG_S24,
ARM64_REG_S25,
ARM64_REG_S26,
ARM64_REG_S27,
ARM64_REG_S28,
ARM64_REG_S29,
ARM64_REG_S30,
ARM64_REG_S31,
ARM64_REG_W0,
ARM64_REG_W1,
ARM64_REG_W2,
ARM64_REG_W3,
ARM64_REG_W4,
ARM64_REG_W5,
ARM64_REG_W6,
ARM64_REG_W7,
ARM64_REG_W8,
ARM64_REG_W9,
ARM64_REG_W10,
ARM64_REG_W11,
ARM64_REG_W12,
ARM64_REG_W13,
ARM64_REG_W14,
ARM64_REG_W15,
ARM64_REG_W16,
ARM64_REG_W17,
ARM64_REG_W18,
ARM64_REG_W19,
ARM64_REG_W20,
ARM64_REG_W21,
ARM64_REG_W22,
ARM64_REG_W23,
ARM64_REG_W24,
ARM64_REG_W25,
ARM64_REG_W26,
ARM64_REG_W27,
ARM64_REG_W28,
ARM64_REG_W29,
ARM64_REG_W30,
ARM64_REG_X0,
ARM64_REG_X1,
ARM64_REG_X2,
ARM64_REG_X3,
ARM64_REG_X4,
ARM64_REG_X5,
ARM64_REG_X6,
ARM64_REG_X7,
ARM64_REG_X8,
ARM64_REG_X9,
ARM64_REG_X10,
ARM64_REG_X11,
ARM64_REG_X12,
ARM64_REG_X13,
ARM64_REG_X14,
ARM64_REG_X15,
ARM64_REG_X16,
ARM64_REG_X17,
ARM64_REG_X18,
ARM64_REG_X19,
ARM64_REG_X20,
ARM64_REG_X21,
ARM64_REG_X22,
ARM64_REG_X23,
ARM64_REG_X24,
ARM64_REG_X25,
ARM64_REG_X26,
ARM64_REG_X27,
ARM64_REG_X28,
UC_ARM64_REG_X29,
UC_ARM64_REG_X30,
UC_ARM64_REG_NZCV,
UC_ARM64_REG_SP,
UC_ARM64_REG_WSP,
UC_ARM64_REG_WZR,
UC_ARM64_REG_XZR,
UC_ARM64_REG_B0,
UC_ARM64_REG_B1,
UC_ARM64_REG_B2,
UC_ARM64_REG_B3,
UC_ARM64_REG_B4,
UC_ARM64_REG_B5,
UC_ARM64_REG_B6,
UC_ARM64_REG_B7,
UC_ARM64_REG_B8,
UC_ARM64_REG_B9,
UC_ARM64_REG_B10,
UC_ARM64_REG_B11,
UC_ARM64_REG_B12,
UC_ARM64_REG_B13,
UC_ARM64_REG_B14,
UC_ARM64_REG_B15,
UC_ARM64_REG_B16,
UC_ARM64_REG_B17,
UC_ARM64_REG_B18,
UC_ARM64_REG_B19,
UC_ARM64_REG_B20,
UC_ARM64_REG_B21,
UC_ARM64_REG_B22,
UC_ARM64_REG_B23,
UC_ARM64_REG_B24,
UC_ARM64_REG_B25,
UC_ARM64_REG_B26,
UC_ARM64_REG_B27,
UC_ARM64_REG_B28,
UC_ARM64_REG_B29,
UC_ARM64_REG_B30,
UC_ARM64_REG_B31,
UC_ARM64_REG_D0,
UC_ARM64_REG_D1,
UC_ARM64_REG_D2,
UC_ARM64_REG_D3,
UC_ARM64_REG_D4,
UC_ARM64_REG_D5,
UC_ARM64_REG_D6,
UC_ARM64_REG_D7,
UC_ARM64_REG_D8,
UC_ARM64_REG_D9,
UC_ARM64_REG_D10,
UC_ARM64_REG_D11,
UC_ARM64_REG_D12,
UC_ARM64_REG_D13,
UC_ARM64_REG_D14,
UC_ARM64_REG_D15,
UC_ARM64_REG_D16,
UC_ARM64_REG_D17,
UC_ARM64_REG_D18,
UC_ARM64_REG_D19,
UC_ARM64_REG_D20,
UC_ARM64_REG_D21,
UC_ARM64_REG_D22,
UC_ARM64_REG_D23,
UC_ARM64_REG_D24,
UC_ARM64_REG_D25,
UC_ARM64_REG_D26,
UC_ARM64_REG_D27,
UC_ARM64_REG_D28,
UC_ARM64_REG_D29,
UC_ARM64_REG_D30,
UC_ARM64_REG_D31,
UC_ARM64_REG_H0,
UC_ARM64_REG_H1,
UC_ARM64_REG_H2,
UC_ARM64_REG_H3,
UC_ARM64_REG_H4,
UC_ARM64_REG_H5,
UC_ARM64_REG_H6,
UC_ARM64_REG_H7,
UC_ARM64_REG_H8,
UC_ARM64_REG_H9,
UC_ARM64_REG_H10,
UC_ARM64_REG_H11,
UC_ARM64_REG_H12,
UC_ARM64_REG_H13,
UC_ARM64_REG_H14,
UC_ARM64_REG_H15,
UC_ARM64_REG_H16,
UC_ARM64_REG_H17,
UC_ARM64_REG_H18,
UC_ARM64_REG_H19,
UC_ARM64_REG_H20,
UC_ARM64_REG_H21,
UC_ARM64_REG_H22,
UC_ARM64_REG_H23,
UC_ARM64_REG_H24,
UC_ARM64_REG_H25,
UC_ARM64_REG_H26,
UC_ARM64_REG_H27,
UC_ARM64_REG_H28,
UC_ARM64_REG_H29,
UC_ARM64_REG_H30,
UC_ARM64_REG_H31,
UC_ARM64_REG_Q0,
UC_ARM64_REG_Q1,
UC_ARM64_REG_Q2,
UC_ARM64_REG_Q3,
UC_ARM64_REG_Q4,
UC_ARM64_REG_Q5,
UC_ARM64_REG_Q6,
UC_ARM64_REG_Q7,
UC_ARM64_REG_Q8,
UC_ARM64_REG_Q9,
UC_ARM64_REG_Q10,
UC_ARM64_REG_Q11,
UC_ARM64_REG_Q12,
UC_ARM64_REG_Q13,
UC_ARM64_REG_Q14,
UC_ARM64_REG_Q15,
UC_ARM64_REG_Q16,
UC_ARM64_REG_Q17,
UC_ARM64_REG_Q18,
UC_ARM64_REG_Q19,
UC_ARM64_REG_Q20,
UC_ARM64_REG_Q21,
UC_ARM64_REG_Q22,
UC_ARM64_REG_Q23,
UC_ARM64_REG_Q24,
UC_ARM64_REG_Q25,
UC_ARM64_REG_Q26,
UC_ARM64_REG_Q27,
UC_ARM64_REG_Q28,
UC_ARM64_REG_Q29,
UC_ARM64_REG_Q30,
UC_ARM64_REG_Q31,
UC_ARM64_REG_S0,
UC_ARM64_REG_S1,
UC_ARM64_REG_S2,
UC_ARM64_REG_S3,
UC_ARM64_REG_S4,
UC_ARM64_REG_S5,
UC_ARM64_REG_S6,
UC_ARM64_REG_S7,
UC_ARM64_REG_S8,
UC_ARM64_REG_S9,
UC_ARM64_REG_S10,
UC_ARM64_REG_S11,
UC_ARM64_REG_S12,
UC_ARM64_REG_S13,
UC_ARM64_REG_S14,
UC_ARM64_REG_S15,
UC_ARM64_REG_S16,
UC_ARM64_REG_S17,
UC_ARM64_REG_S18,
UC_ARM64_REG_S19,
UC_ARM64_REG_S20,
UC_ARM64_REG_S21,
UC_ARM64_REG_S22,
UC_ARM64_REG_S23,
UC_ARM64_REG_S24,
UC_ARM64_REG_S25,
UC_ARM64_REG_S26,
UC_ARM64_REG_S27,
UC_ARM64_REG_S28,
UC_ARM64_REG_S29,
UC_ARM64_REG_S30,
UC_ARM64_REG_S31,
UC_ARM64_REG_W0,
UC_ARM64_REG_W1,
UC_ARM64_REG_W2,
UC_ARM64_REG_W3,
UC_ARM64_REG_W4,
UC_ARM64_REG_W5,
UC_ARM64_REG_W6,
UC_ARM64_REG_W7,
UC_ARM64_REG_W8,
UC_ARM64_REG_W9,
UC_ARM64_REG_W10,
UC_ARM64_REG_W11,
UC_ARM64_REG_W12,
UC_ARM64_REG_W13,
UC_ARM64_REG_W14,
UC_ARM64_REG_W15,
UC_ARM64_REG_W16,
UC_ARM64_REG_W17,
UC_ARM64_REG_W18,
UC_ARM64_REG_W19,
UC_ARM64_REG_W20,
UC_ARM64_REG_W21,
UC_ARM64_REG_W22,
UC_ARM64_REG_W23,
UC_ARM64_REG_W24,
UC_ARM64_REG_W25,
UC_ARM64_REG_W26,
UC_ARM64_REG_W27,
UC_ARM64_REG_W28,
UC_ARM64_REG_W29,
UC_ARM64_REG_W30,
UC_ARM64_REG_X0,
UC_ARM64_REG_X1,
UC_ARM64_REG_X2,
UC_ARM64_REG_X3,
UC_ARM64_REG_X4,
UC_ARM64_REG_X5,
UC_ARM64_REG_X6,
UC_ARM64_REG_X7,
UC_ARM64_REG_X8,
UC_ARM64_REG_X9,
UC_ARM64_REG_X10,
UC_ARM64_REG_X11,
UC_ARM64_REG_X12,
UC_ARM64_REG_X13,
UC_ARM64_REG_X14,
UC_ARM64_REG_X15,
UC_ARM64_REG_X16,
UC_ARM64_REG_X17,
UC_ARM64_REG_X18,
UC_ARM64_REG_X19,
UC_ARM64_REG_X20,
UC_ARM64_REG_X21,
UC_ARM64_REG_X22,
UC_ARM64_REG_X23,
UC_ARM64_REG_X24,
UC_ARM64_REG_X25,
UC_ARM64_REG_X26,
UC_ARM64_REG_X27,
UC_ARM64_REG_X28,
ARM64_REG_V0,
ARM64_REG_V1,
ARM64_REG_V2,
ARM64_REG_V3,
ARM64_REG_V4,
ARM64_REG_V5,
ARM64_REG_V6,
ARM64_REG_V7,
ARM64_REG_V8,
ARM64_REG_V9,
ARM64_REG_V10,
ARM64_REG_V11,
ARM64_REG_V12,
ARM64_REG_V13,
ARM64_REG_V14,
ARM64_REG_V15,
ARM64_REG_V16,
ARM64_REG_V17,
ARM64_REG_V18,
ARM64_REG_V19,
ARM64_REG_V20,
ARM64_REG_V21,
ARM64_REG_V22,
ARM64_REG_V23,
ARM64_REG_V24,
ARM64_REG_V25,
ARM64_REG_V26,
ARM64_REG_V27,
ARM64_REG_V28,
ARM64_REG_V29,
ARM64_REG_V30,
ARM64_REG_V31,
UC_ARM64_REG_V0,
UC_ARM64_REG_V1,
UC_ARM64_REG_V2,
UC_ARM64_REG_V3,
UC_ARM64_REG_V4,
UC_ARM64_REG_V5,
UC_ARM64_REG_V6,
UC_ARM64_REG_V7,
UC_ARM64_REG_V8,
UC_ARM64_REG_V9,
UC_ARM64_REG_V10,
UC_ARM64_REG_V11,
UC_ARM64_REG_V12,
UC_ARM64_REG_V13,
UC_ARM64_REG_V14,
UC_ARM64_REG_V15,
UC_ARM64_REG_V16,
UC_ARM64_REG_V17,
UC_ARM64_REG_V18,
UC_ARM64_REG_V19,
UC_ARM64_REG_V20,
UC_ARM64_REG_V21,
UC_ARM64_REG_V22,
UC_ARM64_REG_V23,
UC_ARM64_REG_V24,
UC_ARM64_REG_V25,
UC_ARM64_REG_V26,
UC_ARM64_REG_V27,
UC_ARM64_REG_V28,
UC_ARM64_REG_V29,
UC_ARM64_REG_V30,
UC_ARM64_REG_V31,
//> pseudo registers
ARM64_REG_PC, // program counter register
UC_ARM64_REG_PC, // program counter register
ARM64_REG_ENDING, // <-- mark the end of the list of registers
UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
//> alias registers
ARM64_REG_IP1 = ARM64_REG_X16,
ARM64_REG_IP0 = ARM64_REG_X17,
ARM64_REG_FP = ARM64_REG_X29,
ARM64_REG_LR = ARM64_REG_X30,
} arm64_reg;
UC_ARM64_REG_IP1 = UC_ARM64_REG_X16,
UC_ARM64_REG_IP0 = UC_ARM64_REG_X17,
UC_ARM64_REG_FP = UC_ARM64_REG_X29,
UC_ARM64_REG_LR = UC_ARM64_REG_X30,
} uc_arm64_reg;
#ifdef __cplusplus
}

360
include/unicorn/mips.h
View File

@ -17,207 +17,207 @@ extern "C" {
#endif
//> MIPS registers
typedef enum mips_reg {
MIPS_REG_INVALID = 0,
typedef enum UC_MIPS_REG {
UC_MIPS_REG_INVALID = 0,
//> General purpose registers
MIPS_REG_PC,
UC_MIPS_REG_PC,
MIPS_REG_0,
MIPS_REG_1,
MIPS_REG_2,
MIPS_REG_3,
MIPS_REG_4,
MIPS_REG_5,
MIPS_REG_6,
MIPS_REG_7,
MIPS_REG_8,
MIPS_REG_9,
MIPS_REG_10,
MIPS_REG_11,
MIPS_REG_12,
MIPS_REG_13,
MIPS_REG_14,
MIPS_REG_15,
MIPS_REG_16,
MIPS_REG_17,
MIPS_REG_18,
MIPS_REG_19,
MIPS_REG_20,
MIPS_REG_21,
MIPS_REG_22,
MIPS_REG_23,
MIPS_REG_24,
MIPS_REG_25,
MIPS_REG_26,
MIPS_REG_27,
MIPS_REG_28,
MIPS_REG_29,
MIPS_REG_30,
MIPS_REG_31,
UC_MIPS_REG_0,
UC_MIPS_REG_1,
UC_MIPS_REG_2,
UC_MIPS_REG_3,
UC_MIPS_REG_4,
UC_MIPS_REG_5,
UC_MIPS_REG_6,
UC_MIPS_REG_7,
UC_MIPS_REG_8,
UC_MIPS_REG_9,
UC_MIPS_REG_10,
UC_MIPS_REG_11,
UC_MIPS_REG_12,
UC_MIPS_REG_13,
UC_MIPS_REG_14,
UC_MIPS_REG_15,
UC_MIPS_REG_16,
UC_MIPS_REG_17,
UC_MIPS_REG_18,
UC_MIPS_REG_19,
UC_MIPS_REG_20,
UC_MIPS_REG_21,
UC_MIPS_REG_22,
UC_MIPS_REG_23,
UC_MIPS_REG_24,
UC_MIPS_REG_25,
UC_MIPS_REG_26,
UC_MIPS_REG_27,
UC_MIPS_REG_28,
UC_MIPS_REG_29,
UC_MIPS_REG_30,
UC_MIPS_REG_31,
//> DSP registers
MIPS_REG_DSPCCOND,
MIPS_REG_DSPCARRY,
MIPS_REG_DSPEFI,
MIPS_REG_DSPOUTFLAG,
MIPS_REG_DSPOUTFLAG16_19,
MIPS_REG_DSPOUTFLAG20,
MIPS_REG_DSPOUTFLAG21,
MIPS_REG_DSPOUTFLAG22,
MIPS_REG_DSPOUTFLAG23,
MIPS_REG_DSPPOS,
MIPS_REG_DSPSCOUNT,
UC_MIPS_REG_DSPCCOND,
UC_MIPS_REG_DSPCARRY,
UC_MIPS_REG_DSPEFI,
UC_MIPS_REG_DSPOUTFLAG,
UC_MIPS_REG_DSPOUTFLAG16_19,
UC_MIPS_REG_DSPOUTFLAG20,
UC_MIPS_REG_DSPOUTFLAG21,
UC_MIPS_REG_DSPOUTFLAG22,
UC_MIPS_REG_DSPOUTFLAG23,
UC_MIPS_REG_DSPPOS,
UC_MIPS_REG_DSPSCOUNT,
//> ACC registers
MIPS_REG_AC0,
MIPS_REG_AC1,
MIPS_REG_AC2,
MIPS_REG_AC3,
UC_MIPS_REG_AC0,
UC_MIPS_REG_AC1,
UC_MIPS_REG_AC2,
UC_MIPS_REG_AC3,
//> COP registers
MIPS_REG_CC0,
MIPS_REG_CC1,
MIPS_REG_CC2,
MIPS_REG_CC3,
MIPS_REG_CC4,
MIPS_REG_CC5,
MIPS_REG_CC6,
MIPS_REG_CC7,
UC_MIPS_REG_CC0,
UC_MIPS_REG_CC1,
UC_MIPS_REG_CC2,
UC_MIPS_REG_CC3,
UC_MIPS_REG_CC4,
UC_MIPS_REG_CC5,
UC_MIPS_REG_CC6,
UC_MIPS_REG_CC7,
//> FPU registers
MIPS_REG_F0,
MIPS_REG_F1,
MIPS_REG_F2,
MIPS_REG_F3,
MIPS_REG_F4,
MIPS_REG_F5,
MIPS_REG_F6,
MIPS_REG_F7,
MIPS_REG_F8,
MIPS_REG_F9,
MIPS_REG_F10,
MIPS_REG_F11,
MIPS_REG_F12,
MIPS_REG_F13,
MIPS_REG_F14,
MIPS_REG_F15,
MIPS_REG_F16,
MIPS_REG_F17,
MIPS_REG_F18,
MIPS_REG_F19,
MIPS_REG_F20,
MIPS_REG_F21,
MIPS_REG_F22,
MIPS_REG_F23,
MIPS_REG_F24,
MIPS_REG_F25,
MIPS_REG_F26,
MIPS_REG_F27,
MIPS_REG_F28,
MIPS_REG_F29,
MIPS_REG_F30,
MIPS_REG_F31,
UC_MIPS_REG_F0,
UC_MIPS_REG_F1,
UC_MIPS_REG_F2,
UC_MIPS_REG_F3,
UC_MIPS_REG_F4,
UC_MIPS_REG_F5,
UC_MIPS_REG_F6,
UC_MIPS_REG_F7,
UC_MIPS_REG_F8,
UC_MIPS_REG_F9,
UC_MIPS_REG_F10,
UC_MIPS_REG_F11,
UC_MIPS_REG_F12,
UC_MIPS_REG_F13,
UC_MIPS_REG_F14,
UC_MIPS_REG_F15,
UC_MIPS_REG_F16,
UC_MIPS_REG_F17,
UC_MIPS_REG_F18,
UC_MIPS_REG_F19,
UC_MIPS_REG_F20,
UC_MIPS_REG_F21,
UC_MIPS_REG_F22,
UC_MIPS_REG_F23,
UC_MIPS_REG_F24,
UC_MIPS_REG_F25,
UC_MIPS_REG_F26,
UC_MIPS_REG_F27,
UC_MIPS_REG_F28,
UC_MIPS_REG_F29,
UC_MIPS_REG_F30,
UC_MIPS_REG_F31,
MIPS_REG_FCC0,
MIPS_REG_FCC1,
MIPS_REG_FCC2,
MIPS_REG_FCC3,
MIPS_REG_FCC4,
MIPS_REG_FCC5,
MIPS_REG_FCC6,
MIPS_REG_FCC7,
UC_MIPS_REG_FCC0,
UC_MIPS_REG_FCC1,
UC_MIPS_REG_FCC2,
UC_MIPS_REG_FCC3,
UC_MIPS_REG_FCC4,
UC_MIPS_REG_FCC5,
UC_MIPS_REG_FCC6,
UC_MIPS_REG_FCC7,
//> AFPR128
MIPS_REG_W0,
MIPS_REG_W1,
MIPS_REG_W2,
MIPS_REG_W3,
MIPS_REG_W4,
MIPS_REG_W5,
MIPS_REG_W6,
MIPS_REG_W7,
MIPS_REG_W8,
MIPS_REG_W9,
MIPS_REG_W10,
MIPS_REG_W11,
MIPS_REG_W12,
MIPS_REG_W13,
MIPS_REG_W14,
MIPS_REG_W15,
MIPS_REG_W16,
MIPS_REG_W17,
MIPS_REG_W18,
MIPS_REG_W19,
MIPS_REG_W20,
MIPS_REG_W21,
MIPS_REG_W22,
MIPS_REG_W23,
MIPS_REG_W24,
MIPS_REG_W25,
MIPS_REG_W26,
MIPS_REG_W27,
MIPS_REG_W28,
MIPS_REG_W29,
MIPS_REG_W30,
MIPS_REG_W31,
UC_MIPS_REG_W0,
UC_MIPS_REG_W1,
UC_MIPS_REG_W2,
UC_MIPS_REG_W3,
UC_MIPS_REG_W4,
UC_MIPS_REG_W5,
UC_MIPS_REG_W6,
UC_MIPS_REG_W7,
UC_MIPS_REG_W8,
UC_MIPS_REG_W9,
UC_MIPS_REG_W10,
UC_MIPS_REG_W11,
UC_MIPS_REG_W12,
UC_MIPS_REG_W13,
UC_MIPS_REG_W14,
UC_MIPS_REG_W15,
UC_MIPS_REG_W16,
UC_MIPS_REG_W17,
UC_MIPS_REG_W18,
UC_MIPS_REG_W19,
UC_MIPS_REG_W20,
UC_MIPS_REG_W21,
UC_MIPS_REG_W22,
UC_MIPS_REG_W23,
UC_MIPS_REG_W24,
UC_MIPS_REG_W25,
UC_MIPS_REG_W26,
UC_MIPS_REG_W27,
UC_MIPS_REG_W28,
UC_MIPS_REG_W29,
UC_MIPS_REG_W30,
UC_MIPS_REG_W31,
MIPS_REG_HI,
MIPS_REG_LO,
UC_MIPS_REG_HI,
UC_MIPS_REG_LO,
MIPS_REG_P0,
MIPS_REG_P1,
MIPS_REG_P2,
UC_MIPS_REG_P0,
UC_MIPS_REG_P1,
UC_MIPS_REG_P2,
MIPS_REG_MPL0,
MIPS_REG_MPL1,
MIPS_REG_MPL2,
UC_MIPS_REG_MPL0,
UC_MIPS_REG_MPL1,
UC_MIPS_REG_MPL2,
MIPS_REG_ENDING, // <-- mark the end of the list or registers
UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
// alias registers
MIPS_REG_ZERO = MIPS_REG_0,
MIPS_REG_AT = MIPS_REG_1,
MIPS_REG_V0 = MIPS_REG_2,
MIPS_REG_V1 = MIPS_REG_3,
MIPS_REG_A0 = MIPS_REG_4,
MIPS_REG_A1 = MIPS_REG_5,
MIPS_REG_A2 = MIPS_REG_6,
MIPS_REG_A3 = MIPS_REG_7,
MIPS_REG_T0 = MIPS_REG_8,
MIPS_REG_T1 = MIPS_REG_9,
MIPS_REG_T2 = MIPS_REG_10,
MIPS_REG_T3 = MIPS_REG_11,
MIPS_REG_T4 = MIPS_REG_12,
MIPS_REG_T5 = MIPS_REG_13,
MIPS_REG_T6 = MIPS_REG_14,
MIPS_REG_T7 = MIPS_REG_15,
MIPS_REG_S0 = MIPS_REG_16,
MIPS_REG_S1 = MIPS_REG_17,
MIPS_REG_S2 = MIPS_REG_18,
MIPS_REG_S3 = MIPS_REG_19,
MIPS_REG_S4 = MIPS_REG_20,
MIPS_REG_S5 = MIPS_REG_21,
MIPS_REG_S6 = MIPS_REG_22,
MIPS_REG_S7 = MIPS_REG_23,
MIPS_REG_T8 = MIPS_REG_24,
MIPS_REG_T9 = MIPS_REG_25,
MIPS_REG_K0 = MIPS_REG_26,
MIPS_REG_K1 = MIPS_REG_27,
MIPS_REG_GP = MIPS_REG_28,
MIPS_REG_SP = MIPS_REG_29,
MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
MIPS_REG_RA = MIPS_REG_31,
UC_MIPS_REG_ZERO = UC_MIPS_REG_0,
UC_MIPS_REG_AT = UC_MIPS_REG_1,
UC_MIPS_REG_V0 = UC_MIPS_REG_2,
UC_MIPS_REG_V1 = UC_MIPS_REG_3,
UC_MIPS_REG_A0 = UC_MIPS_REG_4,
UC_MIPS_REG_A1 = UC_MIPS_REG_5,
UC_MIPS_REG_A2 = UC_MIPS_REG_6,
UC_MIPS_REG_A3 = UC_MIPS_REG_7,
UC_MIPS_REG_T0 = UC_MIPS_REG_8,
UC_MIPS_REG_T1 = UC_MIPS_REG_9,
UC_MIPS_REG_T2 = UC_MIPS_REG_10,
UC_MIPS_REG_T3 = UC_MIPS_REG_11,
UC_MIPS_REG_T4 = UC_MIPS_REG_12,
UC_MIPS_REG_T5 = UC_MIPS_REG_13,
UC_MIPS_REG_T6 = UC_MIPS_REG_14,
UC_MIPS_REG_T7 = UC_MIPS_REG_15,
UC_MIPS_REG_S0 = UC_MIPS_REG_16,
UC_MIPS_REG_S1 = UC_MIPS_REG_17,
UC_MIPS_REG_S2 = UC_MIPS_REG_18,
UC_MIPS_REG_S3 = UC_MIPS_REG_19,
UC_MIPS_REG_S4 = UC_MIPS_REG_20,
UC_MIPS_REG_S5 = UC_MIPS_REG_21,
UC_MIPS_REG_S6 = UC_MIPS_REG_22,
UC_MIPS_REG_S7 = UC_MIPS_REG_23,
UC_MIPS_REG_T8 = UC_MIPS_REG_24,
UC_MIPS_REG_T9 = UC_MIPS_REG_25,
UC_MIPS_REG_K0 = UC_MIPS_REG_26,
UC_MIPS_REG_K1 = UC_MIPS_REG_27,
UC_MIPS_REG_GP = UC_MIPS_REG_28,
UC_MIPS_REG_SP = UC_MIPS_REG_29,
UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30,
UC_MIPS_REG_RA = UC_MIPS_REG_31,
MIPS_REG_HI0 = MIPS_REG_AC0,
MIPS_REG_HI1 = MIPS_REG_AC1,
MIPS_REG_HI2 = MIPS_REG_AC2,
MIPS_REG_HI3 = MIPS_REG_AC3,
UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0,
UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1,
UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2,
UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3,
MIPS_REG_LO0 = MIPS_REG_HI0,
MIPS_REG_LO1 = MIPS_REG_HI1,
MIPS_REG_LO2 = MIPS_REG_HI2,
MIPS_REG_LO3 = MIPS_REG_HI3,
} mips_reg;
UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0,
UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1,
UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2,
UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3,
} UC_MIPS_REG;
#ifdef __cplusplus
}

188
include/unicorn/sparc.h
View File

@ -20,108 +20,108 @@ extern "C" {
#endif
//> SPARC registers
typedef enum sparc_reg {
SPARC_REG_INVALID = 0,
typedef enum uc_sparc_reg {
UC_SPARC_REG_INVALID = 0,
SPARC_REG_F0,
SPARC_REG_F1,
SPARC_REG_F2,
SPARC_REG_F3,
SPARC_REG_F4,
SPARC_REG_F5,
SPARC_REG_F6,
SPARC_REG_F7,
SPARC_REG_F8,
SPARC_REG_F9,
SPARC_REG_F10,
SPARC_REG_F11,
SPARC_REG_F12,
SPARC_REG_F13,
SPARC_REG_F14,
SPARC_REG_F15,
SPARC_REG_F16,
SPARC_REG_F17,
SPARC_REG_F18,
SPARC_REG_F19,
SPARC_REG_F20,
SPARC_REG_F21,
SPARC_REG_F22,
SPARC_REG_F23,
SPARC_REG_F24,
SPARC_REG_F25,
SPARC_REG_F26,
SPARC_REG_F27,
SPARC_REG_F28,
SPARC_REG_F29,
SPARC_REG_F30,
SPARC_REG_F31,
SPARC_REG_F32,
SPARC_REG_F34,
SPARC_REG_F36,
SPARC_REG_F38,
SPARC_REG_F40,
SPARC_REG_F42,
SPARC_REG_F44,
SPARC_REG_F46,
SPARC_REG_F48,
SPARC_REG_F50,
SPARC_REG_F52,
SPARC_REG_F54,
SPARC_REG_F56,
SPARC_REG_F58,
SPARC_REG_F60,
SPARC_REG_F62,
SPARC_REG_FCC0, // Floating condition codes
SPARC_REG_FCC1,
SPARC_REG_FCC2,
SPARC_REG_FCC3,
SPARC_REG_FP,
SPARC_REG_G0,
SPARC_REG_G1,
SPARC_REG_G2,
SPARC_REG_G3,
SPARC_REG_G4,
SPARC_REG_G5,
SPARC_REG_G6,
SPARC_REG_G7,
SPARC_REG_I0,
SPARC_REG_I1,
SPARC_REG_I2,
SPARC_REG_I3,
SPARC_REG_I4,
SPARC_REG_I5,
SPARC_REG_I7,
SPARC_REG_ICC, // Integer condition codes
SPARC_REG_L0,
SPARC_REG_L1,
SPARC_REG_L2,
SPARC_REG_L3,
SPARC_REG_L4,
SPARC_REG_L5,
SPARC_REG_L6,
SPARC_REG_L7,
SPARC_REG_O0,
SPARC_REG_O1,
SPARC_REG_O2,
SPARC_REG_O3,
SPARC_REG_O4,
SPARC_REG_O5,
SPARC_REG_O7,
SPARC_REG_SP,
SPARC_REG_Y,
UC_SPARC_REG_F0,
UC_SPARC_REG_F1,
UC_SPARC_REG_F2,
UC_SPARC_REG_F3,
UC_SPARC_REG_F4,
UC_SPARC_REG_F5,
UC_SPARC_REG_F6,
UC_SPARC_REG_F7,
UC_SPARC_REG_F8,
UC_SPARC_REG_F9,
UC_SPARC_REG_F10,
UC_SPARC_REG_F11,
UC_SPARC_REG_F12,
UC_SPARC_REG_F13,
UC_SPARC_REG_F14,
UC_SPARC_REG_F15,
UC_SPARC_REG_F16,
UC_SPARC_REG_F17,
UC_SPARC_REG_F18,
UC_SPARC_REG_F19,
UC_SPARC_REG_F20,
UC_SPARC_REG_F21,
UC_SPARC_REG_F22,
UC_SPARC_REG_F23,
UC_SPARC_REG_F24,
UC_SPARC_REG_F25,
UC_SPARC_REG_F26,
UC_SPARC_REG_F27,
UC_SPARC_REG_F28,
UC_SPARC_REG_F29,
UC_SPARC_REG_F30,
UC_SPARC_REG_F31,
UC_SPARC_REG_F32,
UC_SPARC_REG_F34,
UC_SPARC_REG_F36,
UC_SPARC_REG_F38,
UC_SPARC_REG_F40,
UC_SPARC_REG_F42,
UC_SPARC_REG_F44,
UC_SPARC_REG_F46,
UC_SPARC_REG_F48,
UC_SPARC_REG_F50,
UC_SPARC_REG_F52,
UC_SPARC_REG_F54,
UC_SPARC_REG_F56,
UC_SPARC_REG_F58,
UC_SPARC_REG_F60,
UC_SPARC_REG_F62,
UC_SPARC_REG_FCC0, // Floating condition codes
UC_SPARC_REG_FCC1,
UC_SPARC_REG_FCC2,
UC_SPARC_REG_FCC3,
UC_SPARC_REG_FP,
UC_SPARC_REG_G0,
UC_SPARC_REG_G1,
UC_SPARC_REG_G2,
UC_SPARC_REG_G3,
UC_SPARC_REG_G4,
UC_SPARC_REG_G5,
UC_SPARC_REG_G6,
UC_SPARC_REG_G7,
UC_SPARC_REG_I0,
UC_SPARC_REG_I1,
UC_SPARC_REG_I2,
UC_SPARC_REG_I3,
UC_SPARC_REG_I4,
UC_SPARC_REG_I5,
UC_SPARC_REG_I7,
UC_SPARC_REG_ICC, // Integer condition codes
UC_SPARC_REG_L0,
UC_SPARC_REG_L1,
UC_SPARC_REG_L2,
UC_SPARC_REG_L3,
UC_SPARC_REG_L4,
UC_SPARC_REG_L5,
UC_SPARC_REG_L6,
UC_SPARC_REG_L7,
UC_SPARC_REG_O0,
UC_SPARC_REG_O1,
UC_SPARC_REG_O2,
UC_SPARC_REG_O3,
UC_SPARC_REG_O4,
UC_SPARC_REG_O5,
UC_SPARC_REG_O7,
UC_SPARC_REG_SP,
UC_SPARC_REG_Y,
// special register
SPARC_REG_XCC,
UC_SPARC_REG_XCC,
// pseudo register
SPARC_REG_PC, // program counter register
UC_SPARC_REG_PC, // program counter register
SPARC_REG_ENDING, // <-- mark the end of the list of registers
UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers
// extras
SPARC_REG_O6 = SPARC_REG_SP,
SPARC_REG_I6 = SPARC_REG_FP,
} sparc_reg;
UC_SPARC_REG_O6 = UC_SPARC_REG_SP,
UC_SPARC_REG_I6 = UC_SPARC_REG_FP,
} uc_sparc_reg;
#ifdef __cplusplus
}

2788
include/unicorn/x86.h
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