Unhandled interrupt will halt execution
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@ -13,15 +13,12 @@ class VldrPcInsn(regress.RegressTest):
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# mov gs, eax; mov eax, 1
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code = '8ee8b801000000'.decode('hex')
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uc.mem_write(0x1000, code)
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uc.reg_write(UC_X86_REG_EAX, 0xFFFFFFFF)
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# this should throw an error
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# the eax test is just to prove the second instruction doesn't execute
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try:
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with self.assertRaises(UcError) as ex_ctx:
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uc.emu_start(0x1000, 0x1000 + len(code))
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except UcError:
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return
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self.assertEqual(uc.reg_read(UC_X86_REG_EAX), 1)
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self.assertEquals(ex_ctx.exception.errno, UC_ERR_UNHANDLED_INTERRUPT)
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if __name__ == '__main__':
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regress.main()
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