diff --git a/tests/regress/mips_kernel_mmu.py b/tests/regress/mips_kernel_mmu.py
index 09991770..51602fa3 100755
--- a/tests/regress/mips_kernel_mmu.py
+++ b/tests/regress/mips_kernel_mmu.py
@@ -17,7 +17,6 @@ class MipsSyscall(regress.RegressTest):
 
         uc.emu_start(addr, addr + len(code))
 
-        #self.assertEqual(addr + len(code), uc.reg_read(UC_MIPS_REG_PC))
         self.assertEqual(uc.reg_read(UC_MIPS_REG_AT), 0x3456)