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renames the register constants so unicorn and capstone can compile together

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mothran
2015-08-23 21:36:33 -07:00
parent 3e5ebc58a0
commit a167f7c456
29 changed files with 4130 additions and 4128 deletions
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188
include/unicorn/sparc.h
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@ -20,108 +20,108 @@ extern "C" {
#endif
//> SPARC registers
typedef enum sparc_reg {
SPARC_REG_INVALID = 0,
typedef enum uc_sparc_reg {
UC_SPARC_REG_INVALID = 0,
SPARC_REG_F0,
SPARC_REG_F1,
SPARC_REG_F2,
SPARC_REG_F3,
SPARC_REG_F4,
SPARC_REG_F5,
SPARC_REG_F6,
SPARC_REG_F7,
SPARC_REG_F8,
SPARC_REG_F9,
SPARC_REG_F10,
SPARC_REG_F11,
SPARC_REG_F12,
SPARC_REG_F13,
SPARC_REG_F14,
SPARC_REG_F15,
SPARC_REG_F16,
SPARC_REG_F17,
SPARC_REG_F18,
SPARC_REG_F19,
SPARC_REG_F20,
SPARC_REG_F21,
SPARC_REG_F22,
SPARC_REG_F23,
SPARC_REG_F24,
SPARC_REG_F25,
SPARC_REG_F26,
SPARC_REG_F27,
SPARC_REG_F28,
SPARC_REG_F29,
SPARC_REG_F30,
SPARC_REG_F31,
SPARC_REG_F32,
SPARC_REG_F34,
SPARC_REG_F36,
SPARC_REG_F38,
SPARC_REG_F40,
SPARC_REG_F42,
SPARC_REG_F44,
SPARC_REG_F46,
SPARC_REG_F48,
SPARC_REG_F50,
SPARC_REG_F52,
SPARC_REG_F54,
SPARC_REG_F56,
SPARC_REG_F58,
SPARC_REG_F60,
SPARC_REG_F62,
SPARC_REG_FCC0, // Floating condition codes
SPARC_REG_FCC1,
SPARC_REG_FCC2,
SPARC_REG_FCC3,
SPARC_REG_FP,
SPARC_REG_G0,
SPARC_REG_G1,
SPARC_REG_G2,
SPARC_REG_G3,
SPARC_REG_G4,
SPARC_REG_G5,
SPARC_REG_G6,
SPARC_REG_G7,
SPARC_REG_I0,
SPARC_REG_I1,
SPARC_REG_I2,
SPARC_REG_I3,
SPARC_REG_I4,
SPARC_REG_I5,
SPARC_REG_I7,
SPARC_REG_ICC, // Integer condition codes
SPARC_REG_L0,
SPARC_REG_L1,
SPARC_REG_L2,
SPARC_REG_L3,
SPARC_REG_L4,
SPARC_REG_L5,
SPARC_REG_L6,
SPARC_REG_L7,
SPARC_REG_O0,
SPARC_REG_O1,
SPARC_REG_O2,
SPARC_REG_O3,
SPARC_REG_O4,
SPARC_REG_O5,
SPARC_REG_O7,
SPARC_REG_SP,
SPARC_REG_Y,
UC_SPARC_REG_F0,
UC_SPARC_REG_F1,
UC_SPARC_REG_F2,
UC_SPARC_REG_F3,
UC_SPARC_REG_F4,
UC_SPARC_REG_F5,
UC_SPARC_REG_F6,
UC_SPARC_REG_F7,
UC_SPARC_REG_F8,
UC_SPARC_REG_F9,
UC_SPARC_REG_F10,
UC_SPARC_REG_F11,
UC_SPARC_REG_F12,
UC_SPARC_REG_F13,
UC_SPARC_REG_F14,
UC_SPARC_REG_F15,
UC_SPARC_REG_F16,
UC_SPARC_REG_F17,
UC_SPARC_REG_F18,
UC_SPARC_REG_F19,
UC_SPARC_REG_F20,
UC_SPARC_REG_F21,
UC_SPARC_REG_F22,
UC_SPARC_REG_F23,
UC_SPARC_REG_F24,
UC_SPARC_REG_F25,
UC_SPARC_REG_F26,
UC_SPARC_REG_F27,
UC_SPARC_REG_F28,
UC_SPARC_REG_F29,
UC_SPARC_REG_F30,
UC_SPARC_REG_F31,
UC_SPARC_REG_F32,
UC_SPARC_REG_F34,
UC_SPARC_REG_F36,
UC_SPARC_REG_F38,
UC_SPARC_REG_F40,
UC_SPARC_REG_F42,
UC_SPARC_REG_F44,
UC_SPARC_REG_F46,
UC_SPARC_REG_F48,
UC_SPARC_REG_F50,
UC_SPARC_REG_F52,
UC_SPARC_REG_F54,
UC_SPARC_REG_F56,
UC_SPARC_REG_F58,
UC_SPARC_REG_F60,
UC_SPARC_REG_F62,
UC_SPARC_REG_FCC0, // Floating condition codes
UC_SPARC_REG_FCC1,
UC_SPARC_REG_FCC2,
UC_SPARC_REG_FCC3,
UC_SPARC_REG_FP,
UC_SPARC_REG_G0,
UC_SPARC_REG_G1,
UC_SPARC_REG_G2,
UC_SPARC_REG_G3,
UC_SPARC_REG_G4,
UC_SPARC_REG_G5,
UC_SPARC_REG_G6,
UC_SPARC_REG_G7,
UC_SPARC_REG_I0,
UC_SPARC_REG_I1,
UC_SPARC_REG_I2,
UC_SPARC_REG_I3,
UC_SPARC_REG_I4,
UC_SPARC_REG_I5,
UC_SPARC_REG_I7,
UC_SPARC_REG_ICC, // Integer condition codes
UC_SPARC_REG_L0,
UC_SPARC_REG_L1,
UC_SPARC_REG_L2,
UC_SPARC_REG_L3,
UC_SPARC_REG_L4,
UC_SPARC_REG_L5,
UC_SPARC_REG_L6,
UC_SPARC_REG_L7,
UC_SPARC_REG_O0,
UC_SPARC_REG_O1,
UC_SPARC_REG_O2,
UC_SPARC_REG_O3,
UC_SPARC_REG_O4,
UC_SPARC_REG_O5,
UC_SPARC_REG_O7,
UC_SPARC_REG_SP,
UC_SPARC_REG_Y,
// special register
SPARC_REG_XCC,
UC_SPARC_REG_XCC,
// pseudo register
SPARC_REG_PC, // program counter register
UC_SPARC_REG_PC, // program counter register
SPARC_REG_ENDING, // <-- mark the end of the list of registers
UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers
// extras
SPARC_REG_O6 = SPARC_REG_SP,
SPARC_REG_I6 = SPARC_REG_FP,
} sparc_reg;
UC_SPARC_REG_O6 = UC_SPARC_REG_SP,
UC_SPARC_REG_I6 = UC_SPARC_REG_FP,
} uc_sparc_reg;
#ifdef __cplusplus
}