From a3e139847dacc93cf922ba2bcb297ef58be7673e Mon Sep 17 00:00:00 2001 From: Dominik Maier Date: Tue, 9 Nov 2021 16:04:59 +0100 Subject: [PATCH] reapply missing changes --- bindings/rust/README.md | 12 ++++++------ bindings/rust/src/lib.rs | 4 +++- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/bindings/rust/README.md b/bindings/rust/README.md index dba1d53c..d855cea3 100644 --- a/bindings/rust/README.md +++ b/bindings/rust/README.md @@ -5,23 +5,23 @@ Rust bindings for the [Unicorn](http://www.unicorn-engine.org/) emulator with ut Checkout Unicorn2 source code at [dev branch](https://github.com/unicorn-engine/unicorn/tree/dev). ```rust -use unicorn_engine::RegisterARM; +use unicorn_engine::{Unicorn, RegisterARM}; use unicorn_engine::unicorn_const::{Arch, Mode, Permission, SECOND_SCALE}; fn main() { let arm_code32: Vec = vec![0x17, 0x00, 0x40, 0xe2]; // sub r0, #23 - let mut unicorn = unicorn-engine::Unicorn::new(Arch::ARM, Mode::LITTLE_ENDIAN).expect("failed to initialize Unicorn instance"); + let mut unicorn = Unicorn::new(Arch::ARM, Mode::LITTLE_ENDIAN).expect("failed to initialize Unicorn instance"); let mut emu = unicorn.borrow(); emu.mem_map(0x1000, 0x4000, Permission::ALL).expect("failed to map code page"); emu.mem_write(0x1000, &arm_code32).expect("failed to write instructions"); - emu.reg_write(RegisterARM::R0 as i32, 123).expect("failed write R0"); - emu.reg_write(RegisterARM::R5 as i32, 1337).expect("failed write R5"); + emu.reg_write(RegisterARM::R0, 123).expect("failed write R0"); + emu.reg_write(RegisterARM::R5, 1337).expect("failed write R5"); let _ = emu.emu_start(0x1000, (0x1000 + arm_code32.len()) as u64, 10 * SECOND_SCALE, 1000); - assert_eq!(emu.reg_read(RegisterARM::R0 as i32), Ok(100)); - assert_eq!(emu.reg_read(RegisterARM::R5 as i32), Ok(1337)); + assert_eq!(emu.reg_read(RegisterARM::R0, Ok(100)); + assert_eq!(emu.reg_read(RegisterARM::R5, Ok(1337)); } ``` Further sample code can be found in ```tests/unicorn.rs```. diff --git a/bindings/rust/src/lib.rs b/bindings/rust/src/lib.rs index 5ffbc2de..4663b42c 100644 --- a/bindings/rust/src/lib.rs +++ b/bindings/rust/src/lib.rs @@ -289,7 +289,7 @@ impl<'a, D> Unicorn<'a, D> { /// Write variable sized values into registers. /// /// The user has to make sure that the buffer length matches the register size. - /// This adds support for registers >64 bit (GDTR/IDTR, XMM, YMM, ZMM (x86); Q, V (arm64)). + /// This adds support for registers >64 bit (GDTR/IDTR, XMM, YMM, ZMM, ST (x86); Q, V (arm64)). pub fn reg_write_long>(&self, regid: T, value: &[u8]) -> Result<(), uc_error> { let err = unsafe { ffi::uc_reg_write(self.uc, regid.into(), value.as_ptr() as _) }; if err == uc_error::OK { @@ -337,6 +337,8 @@ impl<'a, D> Unicorn<'a, D> { value = vec![0; 64]; } else if curr_reg_id == x86::RegisterX86::GDTR as i32 || curr_reg_id == x86::RegisterX86::IDTR as i32 + || (curr_reg_id >= x86::RegisterX86::ST0 as i32 + && curr_reg_id <= x86::RegisterX86::ST7 as i32) { value = vec![0; 10]; // 64 bit base address in IA-32e mode } else {