diff --git a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj index 02be713f..2e8dbc0b 100644 --- a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj +++ b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj @@ -18,6 +18,50 @@ x64 + + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + + + + + + + + + + + + + + + + {698C2D54-475C-446F-B879-F629BBEF75FE} Win32Proj diff --git a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters index 9cd85105..de4c9bfc 100644 --- a/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters +++ b/msvc/unicorn/sparc-softmmu/sparc-softmmu.vcxproj.filters @@ -1,2 +1,110 @@  - \ No newline at end of file + + + + {d424a094-0a26-4db6-85e9-e75f81c6e142} + + + {dec3e9f1-0fc3-454e-ae70-78d866b5c3f8} + + + {b229bf2b-cc40-4135-b3b7-40c73bd9f597} + + + {133a0d6a-6f71-4d4b-be6d-f90636aa02a2} + + + {0a04b798-735c-4115-ab62-b6cfc772efed} + + + {10f0c533-e16b-4e31-b979-812af068bb36} + + + + + fpu + + + tcg + + + tcg + + + tcg\i386 + + + + + + + + + + + hw\sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + + + + \ No newline at end of file diff --git a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj index 8d68a3b2..8bc2c504 100644 --- a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj +++ b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj @@ -18,6 +18,51 @@ x64 + + + + + + + + + + + + + + + + + + + + + + + true + true + true + true + + + + + + + + + + + + + + + + + + + {8804AD29-E398-480C-AC0F-98EC1B7A51CB} Win32Proj diff --git a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters index 9cd85105..0e5b0c35 100644 --- a/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters +++ b/msvc/unicorn/sparc64-softmmu/sparc64-softmmu.vcxproj.filters @@ -1,2 +1,113 @@  - \ No newline at end of file + + + + {1f15e2b2-fae3-41e5-b787-70c44beb828c} + + + {ee6a3abf-6f14-47ab-8b40-f859d030230a} + + + {4a271b0a-7736-4457-98f8-8c21ad4d2601} + + + {7c7b0370-fe65-4c21-94e6-f4561470087d} + + + {51a4ddc6-4078-4db0-9b29-c68c558b2f93} + + + {46e355ab-da0b-431b-929b-8d77b3ab90bc} + + + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + target-sparc + + + fpu + + + tcg + + + tcg + + + tcg\i386 + + + + + + + + + + + hw\sparc64 + + + + + fpu + + + fpu + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg + + + tcg\i386 + + + + + + \ No newline at end of file diff --git a/msvc/unicorn/unicorn/unicorn.vcxproj b/msvc/unicorn/unicorn/unicorn.vcxproj index a501538b..cb955f45 100644 --- a/msvc/unicorn/unicorn/unicorn.vcxproj +++ b/msvc/unicorn/unicorn/unicorn.vcxproj @@ -237,7 +237,7 @@ Level3 Disabled - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86 MultiThreadedDebug .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -249,7 +249,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -261,7 +261,7 @@ Level3 Disabled - WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 + WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86 MultiThreadedDebug .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -273,7 +273,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -287,7 +287,7 @@ MaxSpeed true true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86 MultiThreaded .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -301,7 +301,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat @@ -315,7 +315,7 @@ MaxSpeed true true - WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_X86 + WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86 MultiThreaded .;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg /wd4018 /wd4244 /wd4267 %(AdditionalOptions) @@ -329,7 +329,7 @@ $(SolutionDir)$(Platform)\$(Configuration)\ - ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;x86_64-softmmu.lib + ws2_32.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib ..\prebuild_script.bat diff --git a/qemu/hw/sparc/leon3.c b/qemu/hw/sparc/leon3.c index d0e359aa..150aaed1 100644 --- a/qemu/hw/sparc/leon3.c +++ b/qemu/hw/sparc/leon3.c @@ -58,10 +58,13 @@ static int leon3_generic_hw_init(struct uc_struct *uc, MachineState *machine) void leon3_machine_init(struct uc_struct *uc) { static QEMUMachine leon3_generic_machine = { - .name = "leon3_generic", - .init = leon3_generic_hw_init, - .is_default = 1, - .arch = UC_ARCH_SPARC, + NULL, + "leon3_generic", + leon3_generic_hw_init, + NULL, + 0, + 1, + UC_ARCH_SPARC, }; //printf(">>> leon3_machine_init\n"); diff --git a/qemu/hw/sparc64/sun4u.c b/qemu/hw/sparc64/sun4u.c index 7e85a4a4..1995d311 100644 --- a/qemu/hw/sparc64/sun4u.c +++ b/qemu/hw/sparc64/sun4u.c @@ -50,11 +50,13 @@ static int sun4u_init(struct uc_struct *uc, MachineState *machine) void sun4u_machine_init(struct uc_struct *uc) { static QEMUMachine sun4u_machine = { - .name = "sun4u", - .init = sun4u_init, - .max_cpus = 1, // XXX for now - .is_default = 1, - .arch = UC_ARCH_SPARC, + NULL, + "sun4u", + sun4u_init, + NULL, + 1, // XXX for now + 1, + UC_ARCH_SPARC, }; qemu_register_machine(uc, &sun4u_machine, TYPE_MACHINE, NULL); diff --git a/qemu/target-sparc/cc_helper.c b/qemu/target-sparc/cc_helper.c index 66ec0e61..69823b70 100644 --- a/qemu/target-sparc/cc_helper.c +++ b/qemu/target-sparc/cc_helper.c @@ -438,35 +438,35 @@ typedef struct CCTable { static const CCTable icc_table[CC_OP_NB] = { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_DYNAMIC] = { compute_null, compute_null }, - [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags }, - [CC_OP_DIV] = { compute_all_div, compute_C_div }, - [CC_OP_ADD] = { compute_all_add, compute_C_add }, - [CC_OP_ADDX] = { compute_all_addx, compute_C_addx }, - [CC_OP_TADD] = { compute_all_tadd, compute_C_add }, - [CC_OP_TADDTV] = { compute_all_taddtv, compute_C_add }, - [CC_OP_SUB] = { compute_all_sub, compute_C_sub }, - [CC_OP_SUBX] = { compute_all_subx, compute_C_subx }, - [CC_OP_TSUB] = { compute_all_tsub, compute_C_sub }, - [CC_OP_TSUBTV] = { compute_all_tsubtv, compute_C_sub }, - [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic }, + { compute_null, compute_null }, + { compute_all_flags, compute_C_flags }, + { compute_all_div, compute_C_div }, + { compute_all_add, compute_C_add }, + { compute_all_addx, compute_C_addx }, + { compute_all_tadd, compute_C_add }, + { compute_all_taddtv, compute_C_add }, + { compute_all_sub, compute_C_sub }, + { compute_all_subx, compute_C_subx }, + { compute_all_tsub, compute_C_sub }, + { compute_all_tsubtv, compute_C_sub }, + { compute_all_logic, compute_C_logic }, }; #ifdef TARGET_SPARC64 static const CCTable xcc_table[CC_OP_NB] = { /* CC_OP_DYNAMIC should never happen */ - [CC_OP_DYNAMIC] = { compute_null, compute_null }, - [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc }, - [CC_OP_DIV] = { compute_all_logic_xcc, compute_C_logic }, - [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc }, - [CC_OP_TADD] = { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_TADDTV] = { compute_all_add_xcc, compute_C_add_xcc }, - [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, - [CC_OP_SUBX] = { compute_all_subx_xcc, compute_C_subx_xcc }, - [CC_OP_TSUB] = { compute_all_sub_xcc, compute_C_sub_xcc }, - [CC_OP_TSUBTV] = { compute_all_sub_xcc, compute_C_sub_xcc }, - [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic }, + { compute_null, compute_null }, + { compute_all_flags_xcc, compute_C_flags_xcc }, + { compute_all_logic_xcc, compute_C_logic }, + { compute_all_add_xcc, compute_C_add_xcc }, + { compute_all_addx_xcc, compute_C_addx_xcc }, + { compute_all_add_xcc, compute_C_add_xcc }, + { compute_all_add_xcc, compute_C_add_xcc }, + { compute_all_sub_xcc, compute_C_sub_xcc }, + { compute_all_subx_xcc, compute_C_subx_xcc }, + { compute_all_sub_xcc, compute_C_sub_xcc }, + { compute_all_sub_xcc, compute_C_sub_xcc }, + { compute_all_logic_xcc, compute_C_logic }, }; #endif diff --git a/qemu/target-sparc/cpu.c b/qemu/target-sparc/cpu.c index c3f779b7..9c9c5ead 100644 --- a/qemu/target-sparc/cpu.c +++ b/qemu/target-sparc/cpu.c @@ -158,338 +158,378 @@ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) static const sparc_def_t sparc_defs[] = { #ifdef TARGET_SPARC64 { - .name = "Fujitsu Sparc64", - .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 4, - .maxtl = 4, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu Sparc64", + ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 4, + 4, }, { - .name = "Fujitsu Sparc64 III", - .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 5, - .maxtl = 4, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu Sparc64 III", + ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 5, + 4, }, { - .name = "Fujitsu Sparc64 IV", - .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu Sparc64 IV", + ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Fujitsu Sparc64 V", - .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu Sparc64 V", + ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "TI UltraSparc I", - .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "TI UltraSparc I", + ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "TI UltraSparc II", - .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "TI UltraSparc II", + ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "TI UltraSparc IIi", - .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "TI UltraSparc IIi", + ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "TI UltraSparc IIe", - .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "TI UltraSparc IIe", + ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc III", - .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Sun UltraSparc III", + ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc III Cu", - .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_3, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Sun UltraSparc III Cu", + ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), + 0x00000000, + mmu_us_3, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc IIIi", - .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Sun UltraSparc IIIi", + ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc IV", - .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_4, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Sun UltraSparc IV", + ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), + 0x00000000, + mmu_us_4, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc IV+", - .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, + "Sun UltraSparc IV+", + ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, + 8, + 5, }, { - .name = "Sun UltraSparc IIIi+", - .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_3, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "Sun UltraSparc IIIi+", + ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), + 0x00000000, + mmu_us_3, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, { - .name = "Sun UltraSparc T1", + "Sun UltraSparc T1", /* defined in sparc_ifu_fdp.v and ctu.h */ - .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_sun4v, - .nwindows = 8, - .maxtl = 6, - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT - | CPU_FEATURE_GL, + ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), + 0x00000000, + mmu_sun4v, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT + | CPU_FEATURE_GL, + 8, + 6, }, { - .name = "Sun UltraSparc T2", + "Sun UltraSparc T2", /* defined in tlu_asi_ctl.v and n2_revid_cust.v */ - .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_sun4v, - .nwindows = 8, - .maxtl = 6, - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT - | CPU_FEATURE_GL, + ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), + 0x00000000, + mmu_sun4v, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT + | CPU_FEATURE_GL, + 8, + 6, }, { - .name = "NEC UltraSparc I", - .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), - .fpu_version = 0x00000000, - .mmu_version = mmu_us_12, - .nwindows = 8, - .maxtl = 5, - .features = CPU_DEFAULT_FEATURES, + "NEC UltraSparc I", + ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), + 0x00000000, + mmu_us_12, + 0,0,0,0,0,0, + CPU_DEFAULT_FEATURES, + 8, + 5, }, #else { - .name = "Fujitsu MB86904", - .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ - .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0x00ffffc0, - .mmu_cxr_mask = 0x000000ff, - .mmu_sfsr_mask = 0x00016fff, - .mmu_trcr_mask = 0x00ffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu MB86904", + 0x04 << 24, /* Impl 0, ver 4 */ + 4 << 17, /* FPU version 4 (Meiko) */ + 0x04 << 24, /* Impl 0, ver 4 */ + 0x00004000, + 0x00ffffc0, + 0x000000ff, + 0x00016fff, + 0x00ffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "Fujitsu MB86907", - .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ - .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x000000ff, - .mmu_sfsr_mask = 0x00016fff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "Fujitsu MB86907", + 0x05 << 24, /* Impl 0, ver 5 */ + 4 << 17, /* FPU version 4 (Meiko) */ + 0x05 << 24, /* Impl 0, ver 5 */ + 0x00004000, + 0xffffffc0, + 0x000000ff, + 0x00016fff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI MicroSparc I", - .iu_version = 0x41000000, - .fpu_version = 4 << 17, - .mmu_version = 0x41000000, - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0x007ffff0, - .mmu_cxr_mask = 0x0000003f, - .mmu_sfsr_mask = 0x00016fff, - .mmu_trcr_mask = 0x0000003f, - .nwindows = 7, - .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | - CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | - CPU_FEATURE_FMUL, + "TI MicroSparc I", + 0x41000000, + 4 << 17, + 0x41000000, + 0x00004000, + 0x007ffff0, + 0x0000003f, + 0x00016fff, + 0x0000003f, + 0, + CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | + CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | + CPU_FEATURE_FMUL, + 7, + 0, }, { - .name = "TI MicroSparc II", - .iu_version = 0x42000000, - .fpu_version = 4 << 17, - .mmu_version = 0x02000000, - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0x00ffffc0, - .mmu_cxr_mask = 0x000000ff, - .mmu_sfsr_mask = 0x00016fff, - .mmu_trcr_mask = 0x00ffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI MicroSparc II", + 0x42000000, + 4 << 17, + 0x02000000, + 0x00004000, + 0x00ffffc0, + 0x000000ff, + 0x00016fff, + 0x00ffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI MicroSparc IIep", - .iu_version = 0x42000000, - .fpu_version = 4 << 17, - .mmu_version = 0x04000000, - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0x00ffffc0, - .mmu_cxr_mask = 0x000000ff, - .mmu_sfsr_mask = 0x00016bff, - .mmu_trcr_mask = 0x00ffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI MicroSparc IIep", + 0x42000000, + 4 << 17, + 0x04000000, + 0x00004000, + 0x00ffffc0, + 0x000000ff, + 0x00016bff, + 0x00ffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc 40", /* STP1020NPGA */ - .iu_version = 0x41000000, /* SuperSPARC 2.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc 40", /* STP1020NPGA */ + 0x41000000, /* SuperSPARC 2.x */ + 0 << 17, + 0x00000800, /* SuperSPARC 2.x, no MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc 50", /* STP1020PGA */ - .iu_version = 0x40000000, /* SuperSPARC 3.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc 50", /* STP1020PGA */ + 0x40000000, /* SuperSPARC 3.x */ + 0 << 17, + 0x01000800, /* SuperSPARC 3.x, no MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc 51", - .iu_version = 0x40000000, /* SuperSPARC 3.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .mxcc_version = 0x00000104, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc 51", + 0x40000000, /* SuperSPARC 3.x */ + 0 << 17, + 0x01000000, /* SuperSPARC 3.x, MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0x00000104, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc 60", /* STP1020APGA */ - .iu_version = 0x40000000, /* SuperSPARC 3.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc 60", /* STP1020APGA */ + 0x40000000, /* SuperSPARC 3.x */ + 0 << 17, + 0x01000800, /* SuperSPARC 3.x, no MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc 61", - .iu_version = 0x44000000, /* SuperSPARC 3.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .mxcc_version = 0x00000104, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc 61", + 0x44000000, /* SuperSPARC 3.x */ + 0 << 17, + 0x01000000, /* SuperSPARC 3.x, MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0x00000104, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "TI SuperSparc II", - .iu_version = 0x40000000, /* SuperSPARC II 1.x */ - .fpu_version = 0 << 17, - .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */ - .mmu_bm = 0x00002000, - .mmu_ctpr_mask = 0xffffffc0, - .mmu_cxr_mask = 0x0000ffff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .mxcc_version = 0x00000104, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES, + "TI SuperSparc II", + 0x40000000, /* SuperSPARC II 1.x */ + 0 << 17, + 0x08000000, /* SuperSPARC II 1.x, MXCC */ + 0x00002000, + 0xffffffc0, + 0x0000ffff, + 0xffffffff, + 0xffffffff, + 0x00000104, + CPU_DEFAULT_FEATURES, + 8, + 0, }, { - .name = "LEON2", - .iu_version = 0xf2000000, - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ - .mmu_version = 0xf2000000, - .mmu_bm = 0x00004000, - .mmu_ctpr_mask = 0x007ffff0, - .mmu_cxr_mask = 0x0000003f, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, + "LEON2", + 0xf2000000, + 4 << 17, /* FPU version 4 (Meiko) */ + 0xf2000000, + 0x00004000, + 0x007ffff0, + 0x0000003f, + 0xffffffff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN, + 8, + 0, }, { - .name = "LEON3", - .iu_version = 0xf3000000, - .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ - .mmu_version = 0xf3000000, - .mmu_bm = 0x00000000, - .mmu_ctpr_mask = 0xfffffffc, - .mmu_cxr_mask = 0x000000ff, - .mmu_sfsr_mask = 0xffffffff, - .mmu_trcr_mask = 0xffffffff, - .nwindows = 8, - .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | - CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | - CPU_FEATURE_CASA, + "LEON3", + 0xf3000000, + 4 << 17, /* FPU version 4 (Meiko) */ + 0xf3000000, + 0x00000000, + 0xfffffffc, + 0x000000ff, + 0xffffffff, + 0xffffffff, + 0, + CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN | + CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN | + CPU_FEATURE_CASA, + 8, + 0, }, #endif }; @@ -857,16 +897,25 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da void sparc_cpu_register_types(void *opaque) { - TypeInfo sparc_cpu_type_info = { - .name = TYPE_SPARC_CPU, - .parent = TYPE_CPU, - .instance_userdata = opaque, - .instance_size = sizeof(SPARCCPU), - .instance_init = sparc_cpu_initfn, - .instance_finalize = sparc_cpu_uninitfn, - .abstract = false, - .class_size = sizeof(SPARCCPUClass), - .class_init = sparc_cpu_class_init, + const TypeInfo sparc_cpu_type_info = { + TYPE_SPARC_CPU, + TYPE_CPU, + + sizeof(SPARCCPUClass), + sizeof(SPARCCPU), + opaque, + + sparc_cpu_initfn, + NULL, + sparc_cpu_uninitfn, + + NULL, + + sparc_cpu_class_init, + NULL, + NULL, + + false, }; //printf(">>> sparc_cpu_register_types\n"); diff --git a/qemu/target-sparc/int64_helper.c b/qemu/target-sparc/int64_helper.c index 9421f0a0..7eba49c3 100644 --- a/qemu/target-sparc/int64_helper.c +++ b/qemu/target-sparc/int64_helper.c @@ -63,9 +63,9 @@ void sparc_cpu_do_interrupt(CPUState *cs) break; case TT_TFAULT: case TT_DFAULT: - case TT_TMISS ... TT_TMISS + 3: - case TT_DMISS ... TT_DMISS + 3: - case TT_DPROT ... TT_DPROT + 3: + case TT_TMISS: case TT_TMISS+1: case TT_TMISS+2: case TT_TMISS+3: + case TT_DMISS: case TT_DMISS+1: case TT_DMISS+2: case TT_DMISS+3: + case TT_DPROT: case TT_DPROT+1: case TT_DPROT+2: case TT_DPROT+3: cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG); break; default: diff --git a/qemu/target-sparc/ldst_helper.c b/qemu/target-sparc/ldst_helper.c index 95bf42e1..94f75d02 100644 --- a/qemu/target-sparc/ldst_helper.c +++ b/qemu/target-sparc/ldst_helper.c @@ -558,7 +558,9 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, break; } break; - case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ + /* MMU passthrough, 0x100000000 to 0xfffffffff */ + case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: switch (size) { case 1: ret = ldub_phys(cs->as, (hwaddr)addr @@ -964,7 +966,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi, } } break; - case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ + /* MMU passthrough, 0x100000000 to 0xfffffffff */ + case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: { switch (size) { case 1: @@ -1052,17 +1056,18 @@ static inline int is_translating_asi(int asi) /* Ultrasparc IIi translating asi - note this list is defined by cpu implementation */ - switch (asi) { - case 0x04 ... 0x11: - case 0x16 ... 0x19: - case 0x1E ... 0x1F: - case 0x24 ... 0x2C: - case 0x70 ... 0x73: - case 0x78 ... 0x79: - case 0x80 ... 0xFF: + if( (asi >= 0x04 && asi <= 0x11) || + (asi >= 0x16 && asi <= 0x19) || + (asi >= 0x1E && asi <= 0x1F) || + (asi >= 0x24 && asi <= 0x2C) || + (asi >= 0x70 && asi <= 0x73) || + (asi >= 0x78 && asi <= 0x79) || + (asi >= 0x80 && asi <= 0xFF) ) + { return 1; - - default: + } + else + { return 0; } #else @@ -1303,7 +1308,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size, mmu_idx = (asi & 1) ? MMU_USER_SECONDARY_IDX : MMU_USER_IDX; } - if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == -1ULL) { + if (cpu_get_phys_page_nofault(env, addr, mmu_idx) == (0-1ULL)) { #ifdef DEBUG_ASI dump_asi("read ", last_addr, asi, size, ret); #endif diff --git a/qemu/target-sparc/translate.c b/qemu/target-sparc/translate.c index 4a6fabe7..56df1845 100644 --- a/qemu/target-sparc/translate.c +++ b/qemu/target-sparc/translate.c @@ -2833,14 +2833,14 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins switch(rs1) { case 0: /* rdy */ #ifndef TARGET_SPARC64 - case 0x01 ... 0x0e: /* undefined in the SPARCv8 - manual, rdy on the microSPARC - II */ - case 0x0f: /* stbar in the SPARCv8 manual, - rdy on the microSPARC II */ - case 0x10 ... 0x1f: /* implementation-dependent in the - SPARCv8 manual, rdy on the - microSPARC II */ + /* undefined in the SPARCv8 manual, rdy on the microSPARC II */ + case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: + /* stbar in the SPARCv8 manual, rdy on the microSPARC II */ + case 0x0f: + /* implementation-dependent in the SPARCv8 manual, rdy on the microSPARC II */ + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: /* Read Asr17 */ if (rs1 == 0x11 && dc->def->features & CPU_FEATURE_ASR17) { TCGv t = gen_dest_gpr(dc, rd); @@ -3747,14 +3747,13 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins tcg_gen_andi_tl(tcg_ctx, *(TCGv *)tcg_ctx->cpu_y, cpu_tmp0, 0xffffffff); break; #ifndef TARGET_SPARC64 - case 0x01 ... 0x0f: /* undefined in the - SPARCv8 manual, nop - on the microSPARC - II */ - case 0x10 ... 0x1f: /* implementation-dependent - in the SPARCv8 - manual, nop on the - microSPARC II */ + /* undefined in the SPARCv8 manual, nop on the microSPARC II */ + case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: + + /* implementation-dependent in the SPARCv8 manual, nop on the microSPARC II */ + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17: + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: if ((rd == 0x13) && (dc->def->features & CPU_FEATURE_POWERDOWN)) { /* LEON3 power-down */