import Unicorn2
This commit is contained in:
Nguyen Anh Quynh
@ -19,22 +19,29 @@
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#include "qemu-common.h"
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#include "exec/cpu-common.h"
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#include "exec/memory.h"
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#include "qemu/thread.h"
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#include "qom/cpu.h"
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#include "hw/core/cpu.h"
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#include <uc_priv.h>
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#if 0
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#include "qemu/rcu.h"
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#endif
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#define EXCP_INTERRUPT 0x10000 /* async interruption */
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#define EXCP_HLT 0x10001 /* hlt instruction reached */
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#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
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#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
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#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
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#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
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/* some important defines:
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*
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* WORDS_ALIGNED : if defined, the host cpu can only make word aligned
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* memory accesses.
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*
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* HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
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* otherwise little endian.
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*
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* (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
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*
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* TARGET_WORDS_BIGENDIAN : same for target cpu
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*/
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@ -115,43 +122,9 @@ static inline void tswap64s(uint64_t *s)
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#define bswaptls(s) bswap64s(s)
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#endif
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/* CPU memory access without any memory or io remapping */
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/*
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* the generic syntax for the memory accesses is:
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*
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* load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
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*
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* store: st{type}{size}{endian}_{access_type}(ptr, val)
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*
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* type is:
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* (empty): integer access
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* f : float access
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*
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* sign is:
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* (empty): for floats or 32 bit size
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* endian is:
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* (empty): target cpu endianness or 8 bit access
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* r : reversed target cpu endianness (not implemented yet)
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* be : big endian (not implemented yet)
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* le : little endian (not implemented yet)
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*
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* access_type is:
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* raw : host memory access
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* user : user mode access using soft MMU
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* kernel : kernel mode access using soft MMU
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/* Target-endianness CPU memory access functions. These fit into the
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* {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h.
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*/
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/* target-endianness CPU memory access functions */
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#if defined(TARGET_WORDS_BIGENDIAN)
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#define lduw_p(p) lduw_be_p(p)
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#define ldsw_p(p) ldsw_be_p(p)
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@ -164,6 +137,8 @@ static inline void tswap64s(uint64_t *s)
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#define stq_p(p, v) stq_be_p(p, v)
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#define stfl_p(p, v) stfl_be_p(p, v)
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#define stfq_p(p, v) stfq_be_p(p, v)
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#define ldn_p(p, sz) ldn_be_p(p, sz)
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#define stn_p(p, sz, v) stn_be_p(p, sz, v)
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#else
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#define lduw_p(p) lduw_le_p(p)
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#define ldsw_p(p) ldsw_le_p(p)
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@ -176,39 +151,102 @@ static inline void tswap64s(uint64_t *s)
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#define stq_p(p, v) stq_le_p(p, v)
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#define stfl_p(p, v) stfl_le_p(p, v)
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#define stfq_p(p, v) stfq_le_p(p, v)
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#define ldn_p(p, sz) ldn_le_p(p, sz)
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#define stn_p(p, sz, v) stn_le_p(p, sz, v)
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#endif
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/* MMU memory access macros */
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#include "exec/hwaddr.h"
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#if defined(CONFIG_USER_ONLY)
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#include <assert.h>
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#include "exec/user/abitypes.h"
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/* On some host systems the guest address space is reserved on the host.
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* This allows the guest address space to be offset to a convenient location.
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*/
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#if defined(CONFIG_USE_GUEST_BASE)
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extern unsigned long guest_base;
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extern int have_guest_base;
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extern unsigned long reserved_va;
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#define GUEST_BASE guest_base
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#define RESERVED_VA reserved_va
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#ifdef UNICORN_ARCH_POSTFIX
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#define SUFFIX UNICORN_ARCH_POSTFIX
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#else
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#define GUEST_BASE 0ul
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#define RESERVED_VA 0ul
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#define SUFFIX
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#endif
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.inc.h"
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#define GUEST_ADDR_MAX (RESERVED_VA ? RESERVED_VA : \
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(1ul << TARGET_VIRT_ADDR_SPACE_BITS) - 1)
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#ifdef UNICORN_ARCH_POSTFIX
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#define SUFFIX glue(_cached_slow, UNICORN_ARCH_POSTFIX)
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#else
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#define SUFFIX _cached_slow
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#endif
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst.inc.h"
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static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val)
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{
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#ifdef UNICORN_ARCH_POSTFIX
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glue(address_space_stl_notdirty, UNICORN_ARCH_POSTFIX)
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(as->uc, as, addr, val, MEMTXATTRS_UNSPECIFIED, NULL);
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#else
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address_space_stl_notdirty(as->uc, as, addr, val,
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MEMTXATTRS_UNSPECIFIED, NULL);
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#endif
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}
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#ifdef UNICORN_ARCH_POSTFIX
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#define SUFFIX UNICORN_ARCH_POSTFIX
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#else
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#define SUFFIX
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#endif
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#define ARG1 as
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#define ARG1_DECL AddressSpace *as
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.inc.h"
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/* Inline fast path for direct RAM access. */
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#define ENDIANNESS
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#include "exec/memory_ldst_cached.inc.h"
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#ifdef UNICORN_ARCH_POSTFIX
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#define SUFFIX glue(_cached, UNICORN_ARCH_POSTFIX)
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#else
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#define SUFFIX _cached
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#endif
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#define ARG1 cache
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#define ARG1_DECL MemoryRegionCache *cache
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#define TARGET_ENDIANNESS
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#include "exec/memory_ldst_phys.inc.h"
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/* page related stuff */
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
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#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
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#ifdef TARGET_PAGE_BITS_VARY
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typedef struct TargetPageBits {
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bool decided;
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int bits;
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target_long mask;
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} TargetPageBits;
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#if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY)
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extern const TargetPageBits target_page;
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#else
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extern TargetPageBits target_page;
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#endif
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#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
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#ifdef CONFIG_DEBUG_TCG
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#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
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#define TARGET_PAGE_MASK ({ assert(target_page.decided); target_page.mask; })
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#else
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#define TARGET_PAGE_BITS uc->init_target_page->bits
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#define TARGET_PAGE_MASK uc->init_target_page->mask
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#endif
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#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) // qq
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#else
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#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
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#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
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#define TARGET_PAGE_MASK ((target_ulong)-1 << TARGET_PAGE_BITS)
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#endif
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#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
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#define HOST_PAGE_ALIGN(uc, addr) ROUND_UP((addr), uc->qemu_host_page_size)
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#if 0
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#define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), uc->qemu_real_host_page_size)
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#endif
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/* same as PROT_xxx */
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#define PAGE_READ 0x0001
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@ -219,16 +257,9 @@ extern unsigned long reserved_va;
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/* original state of the write flag (used when tracking self-modifying
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code */
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#define PAGE_WRITE_ORG 0x0010
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#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
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/* FIXME: Code that sets/uses this is broken and needs to go away. */
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#define PAGE_RESERVED 0x0020
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#endif
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#if defined(CONFIG_USER_ONLY)
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//void page_dump(FILE *f);
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int page_get_flags(target_ulong address);
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#endif
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/* Invalidate the TLB entry immediately, helpful for s390x
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* Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */
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#define PAGE_WRITE_INV 0x0040
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CPUArchState *cpu_copy(CPUArchState *env);
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@ -284,26 +315,131 @@ CPUArchState *cpu_copy(CPUArchState *env);
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| CPU_INTERRUPT_TGT_EXT_3 \
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| CPU_INTERRUPT_TGT_EXT_4)
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#if !defined(CONFIG_USER_ONLY)
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/* memory API */
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/* Flags stored in the low bits of the TLB virtual address. These are
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defined so that fast path ram access is all zeros. */
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/*
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* Flags stored in the low bits of the TLB virtual address.
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* These are defined so that fast path ram access is all zeros.
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* The flags all must be between TARGET_PAGE_BITS and
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* maximum address alignment bit.
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*
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* Use TARGET_PAGE_BITS_MIN so that these bits are constant
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* when TARGET_PAGE_BITS_VARY is in effect.
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*/
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/* Zero if TLB entry is valid. */
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#define TLB_INVALID_MASK (1 << 3)
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#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
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/* Set if TLB entry references a clean RAM page. The iotlb entry will
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contain the page physical address. */
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#define TLB_NOTDIRTY (1 << 4)
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#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
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/* Set if TLB entry is an IO callback. */
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#define TLB_MMIO (1 << 5)
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#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
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/* Set if TLB entry contains a watchpoint. */
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#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4))
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/* Set if TLB entry requires byte swap. */
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#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5))
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/* Set if TLB entry writes ignored. */
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#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6))
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ram_addr_t last_ram_offset(struct uc_struct *uc);
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void qemu_mutex_lock_ramlist(struct uc_struct *uc);
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void qemu_mutex_unlock_ramlist(struct uc_struct *uc);
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#endif /* !CONFIG_USER_ONLY */
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/* Use this mask to check interception with an alignment mask
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* in a TCG backend.
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*/
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#define TLB_FLAGS_MASK \
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(TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
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| TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE)
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/**
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* tlb_hit_page: return true if page aligned @addr is a hit against the
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* TLB entry @tlb_addr
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*
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* @addr: virtual address to test (must be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit_page(struct uc_struct *uc, target_ulong tlb_addr, target_ulong addr)
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{
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return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
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}
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/**
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* tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
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*
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* @addr: virtual address to test (need not be page aligned)
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* @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
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*/
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static inline bool tlb_hit(struct uc_struct *uc, target_ulong tlb_addr, target_ulong addr)
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{
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return tlb_hit_page(uc, tlb_addr, addr & TARGET_PAGE_MASK);
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}
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int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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uint8_t *buf, int len, int is_write);
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void *ptr, target_ulong len, bool is_write);
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int cpu_exec(struct uc_struct *uc, CPUState *cpu);
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/**
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* cpu_set_cpustate_pointers(cpu)
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* @cpu: The cpu object
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*
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* Set the generic pointers in CPUState into the outer object.
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*/
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static inline void cpu_set_cpustate_pointers(ArchCPU *cpu)
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{
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cpu->parent_obj.env_ptr = &cpu->env;
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cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr;
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}
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/**
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* env_archcpu(env)
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* @env: The architecture environment
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*
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* Return the ArchCPU associated with the environment.
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*/
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static inline ArchCPU *env_archcpu(CPUArchState *env)
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{
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return container_of(env, ArchCPU, env);
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}
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/**
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* env_cpu(env)
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* @env: The architecture environment
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*
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* Return the CPUState associated with the environment.
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*/
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static inline CPUState *env_cpu(CPUArchState *env)
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{
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return &env_archcpu(env)->parent_obj;
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}
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/**
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* env_neg(env)
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* @env: The architecture environment
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*
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* Return the CPUNegativeOffsetState associated with the environment.
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*/
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static inline CPUNegativeOffsetState *env_neg(CPUArchState *env)
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{
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ArchCPU *arch_cpu = container_of(env, ArchCPU, env);
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return &arch_cpu->neg;
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}
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/**
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* cpu_neg(cpu)
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* @cpu: The generic CPUState
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*
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* Return the CPUNegativeOffsetState associated with the cpu.
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*/
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static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu)
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{
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ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj);
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return &arch_cpu->neg;
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}
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/**
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* env_tlb(env)
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* @env: The architecture environment
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*
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* Return the CPUTLB state associated with the environment.
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*/
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static inline CPUTLB *env_tlb(CPUArchState *env)
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{
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return &env_neg(env)->tlb;
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}
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#endif /* CPU_ALL_H */
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