import Unicorn2
This commit is contained in:
Nguyen Anh Quynh
@ -8,227 +8,251 @@
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* See docs/atomics.txt for discussion about the guarantees each
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* atomic primitive is meant to provide.
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*/
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#ifndef __QEMU_ATOMIC_H
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#define __QEMU_ATOMIC_H 1
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#ifndef QEMU_ATOMIC_H
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#define QEMU_ATOMIC_H
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#include "qemu/compiler.h"
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// we do not really support multiple CPUs, so we dont care
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#define smp_mb()
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#define smp_wmb()
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#define smp_rmb()
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#define barrier()
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/* The variable that receives the old value of an atomically-accessed
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* variable must be non-qualified, because atomic builtins return values
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* through a pointer-type argument as in __atomic_load(&var, &old, MODEL).
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*
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* This macro has to handle types smaller than int manually, because of
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* implicit promotion. int and larger types, as well as pointers, can be
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* converted to a non-qualified type just by applying a binary operator.
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*/
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#define typeof_strip_qual(expr) \
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typeof( \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), bool) || \
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__builtin_types_compatible_p(typeof(expr), const bool) || \
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__builtin_types_compatible_p(typeof(expr), volatile bool) || \
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__builtin_types_compatible_p(typeof(expr), const volatile bool), \
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(bool)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed char) || \
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__builtin_types_compatible_p(typeof(expr), const signed char) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed char), \
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(signed char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned char) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned char), \
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(unsigned char)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), signed short) || \
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__builtin_types_compatible_p(typeof(expr), const signed short) || \
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__builtin_types_compatible_p(typeof(expr), volatile signed short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile signed short), \
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(signed short)1, \
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__builtin_choose_expr( \
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__builtin_types_compatible_p(typeof(expr), unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), volatile unsigned short) || \
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__builtin_types_compatible_p(typeof(expr), const volatile unsigned short), \
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(unsigned short)1, \
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(expr)+0))))))
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#ifdef __ATOMIC_RELAXED
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/* For C11 atomic ops */
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/* Compiler barrier */
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#ifdef _MSC_VER
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void _ReadWriteBarrier(void);
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#pragma intrinsic(_ReadWriteBarrier)
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#define barrier() do { _ReadWriteBarrier(); } while (0)
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#else
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#define barrier() ({ asm volatile("" ::: "memory"); (void)0; })
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#endif
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#ifndef __ATOMIC_RELAXED
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/*
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* We use GCC builtin if it's available, as that can use mfence on
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* 32-bit as well, e.g. if built with -march=pentium-m. However, on
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* i386 the spec is buggy, and the implementation followed it until
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* 4.3 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=36793).
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/* Sanity check that the size of an atomic operation isn't "overly large".
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* Despite the fact that e.g. i686 has 64-bit atomic operations, we do not
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* want to use them because we ought not need them, and this lets us do a
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* bit of sanity checking that other 32-bit hosts might build.
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*
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* That said, we have a problem on 64-bit ILP32 hosts in that in order to
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* sync with TCG_OVERSIZED_GUEST, this must match TCG_TARGET_REG_BITS.
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* We'd prefer not want to pull in everything else TCG related, so handle
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* those few cases by hand.
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*
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* Note that x32 is fully detected with __x86_64__ + _ILP32, and that for
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* Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) &
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* n64 (LP64) ABIs are both detected using __mips64.
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*/
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#if defined(__i386__) || defined(__x86_64__)
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#if !QEMU_GNUC_PREREQ(4, 4)
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#if defined __x86_64__
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# ifdef _MSC_VER
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// TODO: fix me!!!
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# define smp_mb() //{ __asm volatile("mfence" ::: "memory"); (void)0; }
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# else
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# define smp_mb() ({ asm volatile("mfence" ::: "memory"); (void)0; })
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# endif
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#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64)
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# define ATOMIC_REG_SIZE 8
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#else
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# ifdef _MSC_VER
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// TODO: fix me!!!
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# define smp_mb() //{ __asm volatile("lock; addl $0,0(%esp) " ::: "memory"); (void)0; }
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# else
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# define smp_mb() ({ asm volatile("lock; addl $0,0(%%esp) " ::: "memory"); (void)0; })
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# endif
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#endif
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#endif
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# define ATOMIC_REG_SIZE sizeof(void *)
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#endif
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/* Weak atomic operations prevent the compiler moving other
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* loads/stores past the atomic operation load/store. However there is
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* no explicit memory barrier for the processor.
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*
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* The C11 memory model says that variables that are accessed from
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* different threads should at least be done with __ATOMIC_RELAXED
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* primitives or the result is undefined. Generally this has little to
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* no effect on the generated code but not using the atomic primitives
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* will get flagged by sanitizers as a violation.
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*/
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#define atomic_read__nocheck(ptr) \
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__atomic_load_n(ptr, __ATOMIC_RELAXED)
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#ifdef __alpha__
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#define smp_read_barrier_depends() asm volatile("mb":::"memory")
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#endif
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#define atomic_read(ptr) \
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({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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atomic_read__nocheck(ptr); \
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})
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#define atomic_set__nocheck(ptr, i) \
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__atomic_store_n(ptr, i, __ATOMIC_RELAXED)
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#define atomic_set(ptr, i) do { \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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atomic_set__nocheck(ptr, i); \
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} while(0)
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/* All the remaining operations are fully sequentially consistent */
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#define atomic_xchg__nocheck(ptr, i) ({ \
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__atomic_exchange_n(ptr, (i), __ATOMIC_SEQ_CST); \
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})
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#define atomic_xchg(ptr, i) ({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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atomic_xchg__nocheck(ptr, i); \
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})
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/* Returns the eventual value, failed or not */
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#define atomic_cmpxchg__nocheck(ptr, old, new) ({ \
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typeof_strip_qual(*ptr) _old = (old); \
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(void)__atomic_compare_exchange_n(ptr, &_old, new, false, \
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__ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); \
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_old; \
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})
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#define atomic_cmpxchg(ptr, old, new) ({ \
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QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE); \
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atomic_cmpxchg__nocheck(ptr, old, new); \
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})
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/* Provide shorter names for GCC atomic builtins, return old value */
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#define atomic_fetch_inc(ptr) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_dec(ptr) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_fetch_add(ptr, n) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_sub(ptr, n) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_and(ptr, n) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_or(ptr, n) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_fetch_xor(ptr, n) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_inc_fetch(ptr) __atomic_add_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_dec_fetch(ptr) __atomic_sub_fetch(ptr, 1, __ATOMIC_SEQ_CST)
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#define atomic_add_fetch(ptr, n) __atomic_add_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_sub_fetch(ptr, n) __atomic_sub_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_and_fetch(ptr, n) __atomic_and_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_or_fetch(ptr, n) __atomic_or_fetch(ptr, n, __ATOMIC_SEQ_CST)
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#define atomic_xor_fetch(ptr, n) __atomic_xor_fetch(ptr, n, __ATOMIC_SEQ_CST)
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/* And even shorter names that return void. */
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#define atomic_inc(ptr) ((void) __atomic_fetch_add(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_dec(ptr) ((void) __atomic_fetch_sub(ptr, 1, __ATOMIC_SEQ_CST))
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#define atomic_add(ptr, n) ((void) __atomic_fetch_add(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_sub(ptr, n) ((void) __atomic_fetch_sub(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_and(ptr, n) ((void) __atomic_fetch_and(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_or(ptr, n) ((void) __atomic_fetch_or(ptr, n, __ATOMIC_SEQ_CST))
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#define atomic_xor(ptr, n) ((void) __atomic_fetch_xor(ptr, n, __ATOMIC_SEQ_CST))
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#else /* __ATOMIC_RELAXED */
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390x__)
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/*
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* Because of the strongly ordered storage model, wmb() and rmb() are nops
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* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
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* qemu memory or non-temporal load/stores from C code.
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*/
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#define smp_wmb() barrier()
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#define smp_rmb() barrier()
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/*
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* __sync_lock_test_and_set() is documented to be an acquire barrier only,
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* but it is a full barrier at the hardware level. Add a compiler barrier
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* to make it a full barrier also at the compiler level.
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*/
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#define atomic_xchg(ptr, i) (barrier(), __sync_lock_test_and_set(ptr, i))
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/*
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* Load/store with Java volatile semantics.
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*/
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#define atomic_mb_set(ptr, i) ((void)atomic_xchg(ptr, i))
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#elif defined(_ARCH_PPC)
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/*
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* We use an eieio() for wmb() on powerpc. This assumes we don't
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* need to order cacheable and non-cacheable stores with respect to
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* each other.
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*
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* smp_mb has the same problem as on x86 for not-very-new GCC
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* (http://patchwork.ozlabs.org/patch/126184/, Nov 2011).
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*/
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#define smp_wmb() ({ asm volatile("eieio" ::: "memory"); (void)0; })
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#if defined(__powerpc64__)
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#define smp_rmb() ({ asm volatile("lwsync" ::: "memory"); (void)0; })
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#else
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#define smp_rmb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif
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#define smp_mb() ({ asm volatile("sync" ::: "memory"); (void)0; })
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#endif /* _ARCH_PPC */
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#endif /* C11 atomics */
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/*
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* For (host) platforms we don't have explicit barrier definitions
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* for, we use the gcc __sync_synchronize() primitive to generate a
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* full barrier. This should be safe on all platforms, though it may
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* be overkill for smp_wmb() and smp_rmb().
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||||
*/
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#ifndef smp_mb
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||||
#define smp_mb() __sync_synchronize()
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#endif
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#ifndef smp_wmb
|
||||
#ifdef __ATOMIC_RELEASE
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||||
#define smp_wmb() __atomic_thread_fence(__ATOMIC_RELEASE)
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#else
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#define smp_wmb() __sync_synchronize()
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||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef smp_rmb
|
||||
#ifdef __ATOMIC_ACQUIRE
|
||||
#define smp_rmb() __atomic_thread_fence(__ATOMIC_ACQUIRE)
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||||
#else
|
||||
#define smp_rmb() __sync_synchronize()
|
||||
#endif
|
||||
#endif
|
||||
|
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#ifndef smp_read_barrier_depends
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||||
#ifdef __ATOMIC_CONSUME
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#define smp_read_barrier_depends() __atomic_thread_fence(__ATOMIC_CONSUME)
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#else
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#define smp_read_barrier_depends() barrier()
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||||
#endif
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||||
#endif
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||||
|
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#ifndef atomic_read
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#define atomic_read(ptr) (*(__typeof__(*ptr) *volatile) (ptr))
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#endif
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||||
|
||||
#ifndef atomic_set
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||||
#define atomic_set(ptr, i) ((*(__typeof__(*ptr) *volatile) (ptr)) = (i))
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||||
#endif
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|
||||
/* These have the same semantics as Java volatile variables.
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* See http://gee.cs.oswego.edu/dl/jmm/cookbook.html:
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||||
* "1. Issue a StoreStore barrier (wmb) before each volatile store."
|
||||
* 2. Issue a StoreLoad barrier after each volatile store.
|
||||
* Note that you could instead issue one before each volatile load, but
|
||||
* this would be slower for typical programs using volatiles in which
|
||||
* reads greatly outnumber writes. Alternatively, if available, you
|
||||
* can implement volatile store as an atomic instruction (for example
|
||||
* XCHG on x86) and omit the barrier. This may be more efficient if
|
||||
* atomic instructions are cheaper than StoreLoad barriers.
|
||||
* 3. Issue LoadLoad and LoadStore barriers after each volatile load."
|
||||
*
|
||||
* If you prefer to think in terms of "pairing" of memory barriers,
|
||||
* an atomic_mb_read pairs with an atomic_mb_set.
|
||||
*
|
||||
* And for the few ia64 lovers that exist, an atomic_mb_read is a ld.acq,
|
||||
* while an atomic_mb_set is a st.rel followed by a memory barrier.
|
||||
*
|
||||
* These are a bit weaker than __atomic_load/store with __ATOMIC_SEQ_CST
|
||||
* (see docs/atomics.txt), and I'm not sure that __ATOMIC_ACQ_REL is enough.
|
||||
* Just always use the barriers manually by the rules above.
|
||||
*/
|
||||
#ifndef atomic_mb_read
|
||||
#define atomic_mb_read(ptr) ({ \
|
||||
typeof(*ptr) _val = atomic_read(ptr); \
|
||||
smp_rmb(); \
|
||||
_val; \
|
||||
})
|
||||
#endif
|
||||
|
||||
#ifndef atomic_mb_set
|
||||
#define atomic_mb_set(ptr, i) do { \
|
||||
smp_wmb(); \
|
||||
atomic_set(ptr, i); \
|
||||
smp_mb(); \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
#ifndef atomic_xchg
|
||||
#ifndef _MSC_VER
|
||||
#if defined(__clang__)
|
||||
#define atomic_xchg(ptr, i) __sync_swap(ptr, i)
|
||||
#elif defined(__ATOMIC_SEQ_CST)
|
||||
#define atomic_xchg(ptr, i) ({ \
|
||||
typeof(*ptr) _new = (i), _old; \
|
||||
__atomic_exchange(ptr, &_new, &_old, __ATOMIC_SEQ_CST); \
|
||||
_old; \
|
||||
})
|
||||
#else
|
||||
/* __sync_lock_test_and_set() is documented to be an acquire barrier only. */
|
||||
#define atomic_xchg(ptr, i) (smp_mb(), __sync_lock_test_and_set(ptr, i))
|
||||
#define atomic_xchg(ptr, i) (__sync_lock_test_and_set(ptr, i))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* These will only be atomic if the processor does the fetch or store
|
||||
* in a single issue memory operation
|
||||
*/
|
||||
#define atomic_read__nocheck(p) (*(__typeof__(*(p)) volatile*) (p))
|
||||
#define atomic_set__nocheck(p, i) ((*(__typeof__(*(p)) volatile*) (p)) = (i))
|
||||
|
||||
#define atomic_read(ptr) atomic_read__nocheck(ptr)
|
||||
#define atomic_set(ptr, i) atomic_set__nocheck(ptr,i)
|
||||
|
||||
#define atomic_xchg__nocheck atomic_xchg
|
||||
|
||||
/* Provide shorter names for GCC atomic builtins. */
|
||||
#ifdef _MSC_VER
|
||||
// these return the new value (so we make it return the previous value)
|
||||
#define atomic_fetch_inc(ptr) ((InterlockedIncrement(ptr))-1)
|
||||
#define atomic_fetch_dec(ptr) ((InterlockedDecrement(ptr))+1)
|
||||
#define atomic_fetch_add(ptr, n) ((InterlockedAdd(ptr, n))-n)
|
||||
#define atomic_fetch_sub(ptr, n) ((InterlockedAdd(ptr, -n))+n)
|
||||
#else
|
||||
// these return the previous value
|
||||
#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
|
||||
#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
|
||||
#define atomic_fetch_add __sync_fetch_and_add
|
||||
#define atomic_fetch_sub __sync_fetch_and_sub
|
||||
#define atomic_fetch_and __sync_fetch_and_and
|
||||
#define atomic_fetch_or __sync_fetch_and_or
|
||||
#define atomic_cmpxchg __sync_val_compare_and_swap
|
||||
#endif
|
||||
#define atomic_fetch_inc(ptr) ((InterlockedIncrement(ptr))-1)
|
||||
#define atomic_fetch_dec(ptr) ((InterlockedDecrement(ptr))+1)
|
||||
#define atomic_fetch_add(ptr, n) ((InterlockedAdd(ptr, n))-n)
|
||||
#define atomic_fetch_sub(ptr, n) ((InterlockedAdd(ptr, -n))+n)
|
||||
#define atomic_fetch_and(ptr, n) ((InterlockedAnd(ptr, n)))
|
||||
#define atomic_fetch_or(ptr, n) ((InterlockedOr(ptr, n)))
|
||||
#define atomic_fetch_xor(ptr, n) ((InterlockedXor(ptr, n)))
|
||||
|
||||
#define atomic_inc_fetch(ptr) (InterlockedIncrement((long*)(ptr)))
|
||||
#define atomic_dec_fetch(ptr) (InterlockedDecrement((long*)(ptr)))
|
||||
#define atomic_add_fetch(ptr, n) (InterlockedExchangeAdd((long*)ptr, n) + n)
|
||||
#define atomic_sub_fetch(ptr, n) (InterlockedExchangeAdd((long*)ptr, n) - n)
|
||||
#define atomic_and_fetch(ptr, n) (InterlockedAnd((long*)ptr, n) & n)
|
||||
#define atomic_or_fetch(ptr, n) (InterlockedOr((long*)ptr, n) | n)
|
||||
#define atomic_xor_fetch(ptr, n) (InterlockedXor((long*)ptr, n) ^ n)
|
||||
|
||||
#define atomic_cmpxchg(ptr, old, new) ((InterlockedCompareExchange(ptr, old, new)))
|
||||
#define atomic_cmpxchg__nocheck(ptr, old, new) atomic_cmpxchg(ptr, old, new)
|
||||
|
||||
/* And even shorter names that return void. */
|
||||
#ifdef _MSC_VER
|
||||
#define atomic_inc(ptr) ((void) InterlockedIncrement(ptr))
|
||||
#define atomic_dec(ptr) ((void) InterlockedDecrement(ptr))
|
||||
#define atomic_add(ptr, n) ((void) InterlockedAdd(ptr, n))
|
||||
#define atomic_sub(ptr, n) ((void) InterlockedAdd(ptr, -n))
|
||||
#else
|
||||
#define atomic_and(ptr, n) ((void) InterlockedAnd(ptr, n))
|
||||
#define atomic_or(ptr, n) ((void) InterlockedOr(ptr, n))
|
||||
#define atomic_xor(ptr, n) ((void) InterlockedXor(ptr, n))
|
||||
#else // GCC/clang
|
||||
// these return the previous value
|
||||
#define atomic_fetch_inc(ptr) __sync_fetch_and_add(ptr, 1)
|
||||
#define atomic_fetch_dec(ptr) __sync_fetch_and_add(ptr, -1)
|
||||
#define atomic_fetch_add(ptr, n) __sync_fetch_and_add(ptr, n)
|
||||
#define atomic_fetch_sub(ptr, n) __sync_fetch_and_sub(ptr, n)
|
||||
#define atomic_fetch_and(ptr, n) __sync_fetch_and_and(ptr, n)
|
||||
#define atomic_fetch_or(ptr, n) __sync_fetch_and_or(ptr, n)
|
||||
#define atomic_fetch_xor(ptr, n) __sync_fetch_and_xor(ptr, n)
|
||||
|
||||
#define atomic_inc_fetch(ptr) __sync_add_and_fetch(ptr, 1)
|
||||
#define atomic_dec_fetch(ptr) __sync_add_and_fetch(ptr, -1)
|
||||
#define atomic_add_fetch(ptr, n) __sync_add_and_fetch(ptr, n)
|
||||
#define atomic_sub_fetch(ptr, n) __sync_sub_and_fetch(ptr, n)
|
||||
#define atomic_and_fetch(ptr, n) __sync_and_and_fetch(ptr, n)
|
||||
#define atomic_or_fetch(ptr, n) __sync_or_and_fetch(ptr, n)
|
||||
#define atomic_xor_fetch(ptr, n) __sync_xor_and_fetch(ptr, n)
|
||||
|
||||
#define atomic_cmpxchg(ptr, old, new) __sync_val_compare_and_swap(ptr, old, new)
|
||||
#define atomic_cmpxchg__nocheck(ptr, old, new) atomic_cmpxchg(ptr, old, new)
|
||||
|
||||
#define atomic_inc(ptr) ((void) __sync_fetch_and_add(ptr, 1))
|
||||
#define atomic_dec(ptr) ((void) __sync_fetch_and_add(ptr, -1))
|
||||
#define atomic_add(ptr, n) ((void) __sync_fetch_and_add(ptr, n))
|
||||
#define atomic_sub(ptr, n) ((void) __sync_fetch_and_sub(ptr, n))
|
||||
#define atomic_and(ptr, n) ((void) __sync_fetch_and_and(ptr, n))
|
||||
#define atomic_or(ptr, n) ((void) __sync_fetch_and_or(ptr, n))
|
||||
#define atomic_xor(ptr, n) ((void) __sync_fetch_and_xor(ptr, n))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
#endif /* __ATOMIC_RELAXED */
|
||||
|
||||
#endif /* QEMU_ATOMIC_H */
|
||||
|
||||
Reference in New Issue
Block a user