Support building on Android arm aarch64 x86 x86_64

1. Add cmake support in CMakeLists.txt according to https://developer.android.com/ndk/guides/other_build_systems

2. Resolve symbols errors

3. Backport fixes from 438ed42311

   > QEMU relies on two optimization for ppc64 and arm:
   >
   > 1. if(0) /* optimized code */
   > 2. assert(0); /* optimized code */
   >
   > But the assert on mingw32 doesn't have noreturn attribute which prevents
   > the second optimization and some code is reverted to the original code
   > to fit in the first optimization.
   >
   > The assert implementation is copied from glib as qemu did.

   Unfortunately, NDK also doesn't have an assert implementation qemu prefers.

CMakeLists.txt

@@ -88,6 +88,20 @@ else()
             set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} -m64")
             set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} -m64")
         endif()
+    elseif(ANDROID_ABI)
+        string(FIND "${ANDROID_ABI}" "arm64" UC_RET)
+
+        if (${UC_RET} GREATER_EQUAL "0")
+            set(UNICORN_TARGET_ARCH "aarch64")
+        else()
+            string(FIND "${ANDROID_ABI}" "armeabi" UC_RET)
+
+            if (${UC_RET} GREATER_EQUAL "0")
+                set(UNICORN_TARGET_ARCH "arm")
+            else()
+                set(UNICORN_TARGET_ARCH "i386")
+            endif()
+        endif()
     else()
         execute_process(COMMAND ${CMAKE_C_COMPILER} -dM -E -
             INPUT_FILE /dev/null
@@ -185,6 +199,10 @@ else()
     endif()
 
     set (EXTRA_CFLAGS "${EXTRA_CFLAGS}-fPIC")
+    if(ANDROID_ABI)
+        set (EXTRA_CFLAGS "${EXTRA_CFLAGS} --target=${CMAKE_C_COMPILER_TARGET}")
+        set (EXTRA_CFLAGS "${EXTRA_CFLAGS} --sysroot=${CMAKE_SYSROOT}")
+    endif()
 
     set(TARGET_LIST "--target-list=")
     if (UNICORN_HAS_X86)
@@ -994,7 +1012,7 @@ add_library(unicorn-common
     ${UNICORN_COMMON_SRCS}
 )
 
-if (NOT MSVC)
+if (NOT MSVC AND NOT ANDROID_ABI)
     target_link_libraries(unicorn-common pthread)
 endif()
 
@@ -1112,11 +1130,15 @@ if(MSVC)
     set(SAMPLES_LIB
         unicorn
     )
-else()
+elseif(NOT ANDROID_ABI)
     set(SAMPLES_LIB
         unicorn
         pthread
     )
+else()
+    set(SAMPLES_LIB
+        unicorn
+    )
 endif()
 
 foreach(SAMPLE_FILE ${UNICORN_SAMPLE_FILE})

qemu/aarch64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _aarch64
 #endif
+#define use_idiv_instructions use_idiv_instructions_aarch64
 #define arm_arch arm_arch_aarch64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64
 #define have_bmi1 have_bmi1_aarch64

qemu/aarch64eb.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _aarch64eb
 #endif
+#define use_idiv_instructions use_idiv_instructions_aarch64eb
 #define arm_arch arm_arch_aarch64eb
 #define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64eb
 #define have_bmi1 have_bmi1_aarch64eb

qemu/accel/tcg/cputlb.c

@@ -963,10 +963,10 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
      * should result in exception + longjmp to the cpu loop.
      */
     ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
+    assert(ok);
 #else
     cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr);
 #endif
-    assert(ok);
 }
 
 static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,

qemu/arm.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _arm
 #endif
+#define use_idiv_instructions use_idiv_instructions_arm
 #define arm_arch arm_arch_arm
 #define tb_target_set_jmp_target tb_target_set_jmp_target_arm
 #define have_bmi1 have_bmi1_arm

qemu/armeb.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _armeb
 #endif
+#define use_idiv_instructions use_idiv_instructions_armeb
 #define arm_arch arm_arch_armeb
 #define tb_target_set_jmp_target tb_target_set_jmp_target_armeb
 #define have_bmi1 have_bmi1_armeb

qemu/exec.c

@@ -1404,10 +1404,10 @@ AddressSpaceDispatch *address_space_dispatch_new(struct uc_struct *uc, FlatView
     uint16_t n;
 
     n = dummy_section(uc, &d->map, fv, &(uc->io_mem_unassigned));
+    assert(n == PHYS_SECTION_UNASSIGNED);
 #else
     dummy_section(uc, &d->map, fv, &(uc->io_mem_unassigned));
 #endif
-    assert(n == PHYS_SECTION_UNASSIGNED);
 
     d->phys_map  = (PhysPageEntry) { .ptr = PHYS_MAP_NODE_NIL, .skip = 1 };
     d->uc = uc;

qemu/include/qemu/osdep.h

@@ -154,7 +154,8 @@ struct uc_struct;
  * code that is unreachable when features are disabled.
  * All supported versions of Glib's g_assert() satisfy this requirement.
  */
-#ifdef __MINGW32__
+// Unfortunately, NDK also has this problem.
+#if defined(__MINGW32__ ) || defined(__ANDROID__)
 #undef assert
 #define assert(x)  g_assert(x)
 #endif

qemu/m68k.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _m68k
 #endif
+#define use_idiv_instructions use_idiv_instructions_m68k
 #define arm_arch arm_arch_m68k
 #define tb_target_set_jmp_target tb_target_set_jmp_target_m68k
 #define have_bmi1 have_bmi1_m68k

qemu/mips.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips
 #endif
+#define use_idiv_instructions use_idiv_instructions_mips
 #define arm_arch arm_arch_mips
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips
 #define have_bmi1 have_bmi1_mips

qemu/mips64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips64
 #endif
+#define use_idiv_instructions use_idiv_instructions_mips64
 #define arm_arch arm_arch_mips64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips64
 #define have_bmi1 have_bmi1_mips64

qemu/mips64el.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips64el
 #endif
+#define use_idiv_instructions use_idiv_instructions_mips64el
 #define arm_arch arm_arch_mips64el
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips64el
 #define have_bmi1 have_bmi1_mips64el

qemu/mipsel.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mipsel
 #endif
+#define use_idiv_instructions use_idiv_instructions_mipsel
 #define arm_arch arm_arch_mipsel
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mipsel
 #define have_bmi1 have_bmi1_mipsel

qemu/ppc.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _ppc
 #endif
+#define use_idiv_instructions use_idiv_instructions_ppc
 #define arm_arch arm_arch_ppc
 #define tb_target_set_jmp_target tb_target_set_jmp_target_ppc
 #define have_bmi1 have_bmi1_ppc

qemu/ppc64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _ppc64
 #endif
+#define use_idiv_instructions use_idiv_instructions_ppc64
 #define arm_arch arm_arch_ppc64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_ppc64
 #define have_bmi1 have_bmi1_ppc64

qemu/riscv32.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _riscv32
 #endif
+#define use_idiv_instructions use_idiv_instructions_riscv32
 #define arm_arch arm_arch_riscv32
 #define tb_target_set_jmp_target tb_target_set_jmp_target_riscv32
 #define have_bmi1 have_bmi1_riscv32

qemu/riscv64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _riscv64
 #endif
+#define use_idiv_instructions use_idiv_instructions_riscv64
 #define arm_arch arm_arch_riscv64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_riscv64
 #define have_bmi1 have_bmi1_riscv64

qemu/sparc.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _sparc
 #endif
+#define use_idiv_instructions use_idiv_instructions_sparc
 #define arm_arch arm_arch_sparc
 #define tb_target_set_jmp_target tb_target_set_jmp_target_sparc
 #define have_bmi1 have_bmi1_sparc

qemu/sparc64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _sparc64
 #endif
+#define use_idiv_instructions use_idiv_instructions_sparc64
 #define arm_arch arm_arch_sparc64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_sparc64
 #define have_bmi1 have_bmi1_sparc64

qemu/target/arm/cpu.c

@@ -143,8 +143,8 @@ static void cp_reg_check_reset(gpointer key, gpointer value,  gpointer opaque)
     cp_reg_reset(key, value, opaque);
 #ifndef NDEBUG
     newvalue = read_raw_cp_reg(&cpu->env, ri);
-#endif
     assert(oldvalue == newvalue);
+#endif
 }
 
 static void arm_cpu_reset(CPUState *dev)
@@ -919,7 +919,9 @@ void arm_cpu_realizefn(struct uc_struct *uc, CPUState *dev)
          * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
          * Security Extensions is ARM_FEATURE_EL3.
          */
+#ifndef NDEBUG
         assert(no_aa32 || cpu_isar_feature(aa32_arm_div, cpu));
+#endif
         set_feature(env, ARM_FEATURE_LPAE);
         set_feature(env, ARM_FEATURE_V7);
     }
@@ -945,7 +947,9 @@ void arm_cpu_realizefn(struct uc_struct *uc, CPUState *dev)
     if (arm_feature(env, ARM_FEATURE_V6)) {
         set_feature(env, ARM_FEATURE_V5);
         if (!arm_feature(env, ARM_FEATURE_M)) {
+#ifndef NDEBUG
             assert(no_aa32 || cpu_isar_feature(aa32_jazelle, cpu));
+#endif
             set_feature(env, ARM_FEATURE_AUXCR);
         }
     }

qemu/target/arm/helper.c

@@ -6027,12 +6027,11 @@ static void define_debug_regs(ARMCPU *cpu)
     wrps = arm_num_wrps(cpu);
 #ifndef NDEBUG
     ctx_cmps = arm_num_ctx_cmps(cpu);
+    assert(ctx_cmps <= brps);
 #else
     arm_num_ctx_cmps(cpu);
 #endif
 
-    assert(ctx_cmps <= brps);
-
     define_one_arm_cp_reg(cpu, &dbgdidr);
     define_arm_cp_regs(cpu, debug_cp_reginfo);
 

qemu/target/ppc/mmu-hash64.c

@@ -1172,7 +1172,9 @@ void ppc_hash64_init(PowerPCCPU *cpu)
     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
 
     if (!pcc->hash64_opts) {
+#ifndef NDEBUG
         assert(!(env->mmu_model & POWERPC_MMU_64));
+#endif
         return;
     }
 

qemu/tcg/arm/tcg-target.h

@@ -82,10 +82,8 @@ typedef enum {
 
 #define TCG_TARGET_NB_REGS 16
 
-#ifdef __ARM_ARCH_EXT_IDIV__
+#ifndef __ARM_ARCH_EXT_IDIV__
-#define use_idiv_instructions  1
+extern bool use_idiv_instructions;  // Unicorn: Don't have the same name with macro
-#else
-extern bool use_idiv_instructions;
 #endif
 
 
@@ -122,7 +120,11 @@ extern bool use_idiv_instructions;
 #define TCG_TARGET_HAS_muls2_i32        1
 #define TCG_TARGET_HAS_muluh_i32        0
 #define TCG_TARGET_HAS_mulsh_i32        0
+#ifdef __ARM_ARCH_EXT_IDIV__
+#define TCG_TARGET_HAS_div_i32          1
+#else
 #define TCG_TARGET_HAS_div_i32          use_idiv_instructions
+#endif
 #define TCG_TARGET_HAS_rem_i32          0
 #define TCG_TARGET_HAS_goto_ptr         1
 #define TCG_TARGET_HAS_direct_jump      0

qemu/tcg/arm/tcg-target.inc.c

@@ -27,7 +27,7 @@
 
 int arm_arch = __ARM_ARCH;
 
-#ifndef use_idiv_instructions
+#ifndef __ARM_ARCH_EXT_IDIV__
 bool use_idiv_instructions;
 #endif
 
@@ -2201,7 +2201,7 @@ static void tcg_target_init(TCGContext *s)
 {
     /* Only probe for the platform and capabilities if we havn't already
        determined maximum values at compile time.  */
-#ifndef use_idiv_instructions
+#ifndef __ARM_ARCH_EXT_IDIV__
     {
         unsigned long hwcap = qemu_getauxval(AT_HWCAP);
         use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;

qemu/util/range.c

@@ -68,10 +68,10 @@ GList *range_list_insert(GList *list, Range *data)
         g_free(l->next->data);
 #ifndef NDEBUG
         new_l = g_list_delete_link(list, l->next);
+        assert(new_l == list);
 #else
         g_list_delete_link(list, l->next);
 #endif
-        assert(new_l == list);
     }
 
     return list;

qemu/x86_64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _x86_64
 #endif
+#define use_idiv_instructions use_idiv_instructions_x86_64
 #define arm_arch arm_arch_x86_64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_x86_64
 #define have_bmi1 have_bmi1_x86_64

symbols.sh

@@ -4,6 +4,7 @@ CMD_PATH=$(realpath $0)
 SOURCE_DIR=$(dirname ${CMD_PATH})
 
 COMMON_SYMBOLS="
+use_idiv_instructions \
 arm_arch \
 tb_target_set_jmp_target \
 have_bmi1 \