add missing files
This commit is contained in:
Nguyen Anh Quynh
554
qemu/target/s390x/mmu_helper.c
Normal file
554
qemu/target/s390x/mmu_helper.c
Normal file
@ -0,0 +1,554 @@
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/*
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* S390x MMU related functions
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*
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* Copyright (c) 2011 Alexander Graf
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* Copyright (c) 2015 Thomas Huth, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "qemu/osdep.h"
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//#include "exec/address-spaces.h"
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#include "cpu.h"
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#include "internal.h"
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#include "sysemu/tcg.h"
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#include "exec/exec-all.h"
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//#include "hw/hw.h"
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#include "hw/s390x/storage-keys.h"
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/* Fetch/store bits in the translation exception code: */
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#define FS_READ 0x800
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#define FS_WRITE 0x400
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static void trigger_access_exception(CPUS390XState *env, uint32_t type,
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uint64_t tec)
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{
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CPUState *cs = env_cpu(env);
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if (type != PGM_ADDRESSING) {
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#ifdef UNICORN_ARCH_POSTFIX
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glue(stq_phys, UNICORN_ARCH_POSTFIX)(env->uc, cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
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#else
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stq_phys(env->uc, cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
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#endif
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}
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trigger_pgm_exception(env, type);
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}
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/* check whether the address would be proteted by Low-Address Protection */
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static bool is_low_address(uint64_t addr)
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{
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return addr <= 511 || (addr >= 4096 && addr <= 4607);
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}
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/* check whether Low-Address Protection is enabled for mmu_translate() */
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static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
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{
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if (!(env->cregs[0] & CR0_LOWPROT)) {
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return false;
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}
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if (!(env->psw.mask & PSW_MASK_DAT)) {
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return true;
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}
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/* Check the private-space control bit */
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switch (asc) {
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case PSW_ASC_PRIMARY:
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return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
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case PSW_ASC_SECONDARY:
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return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
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case PSW_ASC_HOME:
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return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
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default:
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/* We don't support access register mode */
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// error_report("unsupported addressing mode");
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exit(1);
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}
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}
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/**
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* Translate real address to absolute (= physical)
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* address by taking care of the prefix mapping.
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*/
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target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
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{
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if (raddr < 0x2000) {
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return raddr + env->psa; /* Map the lowcore. */
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} else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
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return raddr - env->psa; /* Map the 0 page. */
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}
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return raddr;
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}
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static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
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uint64_t *entry)
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{
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CPUState *cs = env_cpu(env);
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/*
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* According to the PoP, these table addresses are "unpredictably real
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* or absolute". Also, "it is unpredictable whether the address wraps
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* or an addressing exception is recognized".
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*
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* We treat them as absolute addresses and don't wrap them.
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*/
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if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
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entry, sizeof(*entry)) !=
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MEMTX_OK)) {
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return false;
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}
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*entry = be64_to_cpu(*entry);
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return true;
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}
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static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
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uint64_t asc, uint64_t asce, target_ulong *raddr,
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int *flags, int rw)
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{
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const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
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s390_has_feat(env->uc, S390_FEAT_EDAT);
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const bool edat2 = edat1 && s390_has_feat(env->uc, S390_FEAT_EDAT_2);
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const bool iep = (env->cregs[0] & CR0_IEP) &&
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s390_has_feat(env->uc, S390_FEAT_INSTRUCTION_EXEC_PROT);
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const int asce_tl = asce & ASCE_TABLE_LENGTH;
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const int asce_p = asce & ASCE_PRIVATE_SPACE;
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hwaddr gaddr = asce & ASCE_ORIGIN;
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uint64_t entry;
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if (asce & ASCE_REAL_SPACE) {
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/* direct mapping */
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*raddr = vaddr;
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return 0;
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}
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switch (asce & ASCE_TYPE_MASK) {
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case ASCE_TYPE_REGION1:
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if (VADDR_REGION1_TL(vaddr) > asce_tl) {
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return PGM_REG_FIRST_TRANS;
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}
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gaddr += VADDR_REGION1_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_REGION2:
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if (VADDR_REGION1_TX(vaddr)) {
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return PGM_ASCE_TYPE;
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}
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if (VADDR_REGION2_TL(vaddr) > asce_tl) {
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return PGM_REG_SEC_TRANS;
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}
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gaddr += VADDR_REGION2_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_REGION3:
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if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
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return PGM_ASCE_TYPE;
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}
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if (VADDR_REGION3_TL(vaddr) > asce_tl) {
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return PGM_REG_THIRD_TRANS;
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}
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gaddr += VADDR_REGION3_TX(vaddr) * 8;
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break;
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case ASCE_TYPE_SEGMENT:
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if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
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VADDR_REGION3_TX(vaddr)) {
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return PGM_ASCE_TYPE;
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}
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if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
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return PGM_SEGMENT_TRANS;
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}
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gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
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break;
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}
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switch (asce & ASCE_TYPE_MASK) {
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case ASCE_TYPE_REGION1:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_FIRST_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
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return PGM_TRANS_SPEC;
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}
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if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_REG_SEC_TRANS;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_REGION2:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_SEC_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
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return PGM_TRANS_SPEC;
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}
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if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_REG_THIRD_TRANS;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_REGION3:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & REGION_ENTRY_I) {
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return PGM_REG_THIRD_TRANS;
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}
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if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
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return PGM_TRANS_SPEC;
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}
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if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
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return PGM_TRANS_SPEC;
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}
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if (edat1 && (entry & REGION_ENTRY_P)) {
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*flags &= ~PAGE_WRITE;
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}
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if (edat2 && (entry & REGION3_ENTRY_FC)) {
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if (iep && (entry & REGION3_ENTRY_IEP)) {
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*flags &= ~PAGE_EXEC;
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}
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*raddr = (entry & REGION3_ENTRY_RFAA) |
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(vaddr & ~REGION3_ENTRY_RFAA);
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return 0;
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}
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if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
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VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
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return PGM_SEGMENT_TRANS;
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}
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gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
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/* fall through */
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case ASCE_TYPE_SEGMENT:
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & SEGMENT_ENTRY_I) {
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return PGM_SEGMENT_TRANS;
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}
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if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
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return PGM_TRANS_SPEC;
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}
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if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
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return PGM_TRANS_SPEC;
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}
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if (entry & SEGMENT_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
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if (iep && (entry & SEGMENT_ENTRY_IEP)) {
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*flags &= ~PAGE_EXEC;
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}
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*raddr = (entry & SEGMENT_ENTRY_SFAA) |
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(vaddr & ~SEGMENT_ENTRY_SFAA);
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return 0;
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}
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gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
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break;
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}
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if (!read_table_entry(env, gaddr, &entry)) {
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return PGM_ADDRESSING;
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}
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if (entry & PAGE_ENTRY_I) {
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return PGM_PAGE_TRANS;
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}
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if (entry & PAGE_ENTRY_0) {
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return PGM_TRANS_SPEC;
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}
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if (entry & PAGE_ENTRY_P) {
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*flags &= ~PAGE_WRITE;
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}
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if (iep && (entry & PAGE_ENTRY_IEP)) {
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*flags &= ~PAGE_EXEC;
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}
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*raddr = entry & TARGET_PAGE_MASK;
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return 0;
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}
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static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
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{
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static S390SKeysClass *skeyclass;
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static S390SKeysState *ss;
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uint8_t key;
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int rc;
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#if 0
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if (unlikely(addr >= ram_size)) {
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return;
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}
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#endif
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if (unlikely(!ss)) {
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// ss = s390_get_skeys_device();
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// skeyclass = S390_SKEYS_GET_CLASS(ss);
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}
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/*
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* Whenever we create a new TLB entry, we set the storage key reference
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* bit. In case we allow write accesses, we set the storage key change
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* bit. Whenever the guest changes the storage key, we have to flush the
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* TLBs of all CPUs (the whole TLB or all affected entries), so that the
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* next reference/change will result in an MMU fault and make us properly
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* update the storage key here.
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*
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* Note 1: "record of references ... is not necessarily accurate",
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* "change bit may be set in case no storing has occurred".
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* -> We can set reference/change bits even on exceptions.
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* Note 2: certain accesses seem to ignore storage keys. For example,
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* DAT translation does not set reference bits for table accesses.
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*
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* TODO: key-controlled protection. Only CPU accesses make use of the
|
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* PSW key. CSS accesses are different - we have to pass in the key.
|
||||
*
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||||
* TODO: we have races between getting and setting the key.
|
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*/
|
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rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
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||||
if (rc) {
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||||
// trace_get_skeys_nonzero(rc);
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return;
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}
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||||
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switch (rw) {
|
||||
case MMU_DATA_LOAD:
|
||||
case MMU_INST_FETCH:
|
||||
/*
|
||||
* The TLB entry has to remain write-protected on read-faults if
|
||||
* the storage key does not indicate a change already. Otherwise
|
||||
* we might miss setting the change bit on write accesses.
|
||||
*/
|
||||
if (!(key & SK_C)) {
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*flags &= ~PAGE_WRITE;
|
||||
}
|
||||
break;
|
||||
case MMU_DATA_STORE:
|
||||
key |= SK_C;
|
||||
break;
|
||||
default:
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
||||
/* Any store/fetch sets the reference bit */
|
||||
key |= SK_R;
|
||||
|
||||
rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
|
||||
if (rc) {
|
||||
// trace_set_skeys_nonzero(rc);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Translate a virtual (logical) address into a physical (absolute) address.
|
||||
* @param vaddr the virtual address
|
||||
* @param rw 0 = read, 1 = write, 2 = code fetch
|
||||
* @param asc address space control (one of the PSW_ASC_* modes)
|
||||
* @param raddr the translated address is stored to this pointer
|
||||
* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
|
||||
* @param exc true = inject a program check if a fault occurred
|
||||
* @return 0 = success, != 0, the exception to raise
|
||||
*/
|
||||
int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
|
||||
target_ulong *raddr, int *flags, uint64_t *tec)
|
||||
{
|
||||
uint64_t asce;
|
||||
int r;
|
||||
|
||||
*tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
|
||||
(rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
|
||||
*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
|
||||
if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
|
||||
/*
|
||||
* If any part of this page is currently protected, make sure the
|
||||
* TLB entry will not be reused.
|
||||
*
|
||||
* As the protected range is always the first 512 bytes of the
|
||||
* two first pages, we are able to catch all writes to these areas
|
||||
* just by looking at the start address (triggering the tlb miss).
|
||||
*/
|
||||
*flags |= PAGE_WRITE_INV;
|
||||
if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
|
||||
/* LAP sets bit 56 */
|
||||
*tec |= 0x80;
|
||||
return PGM_PROTECTION;
|
||||
}
|
||||
}
|
||||
|
||||
vaddr &= TARGET_PAGE_MASK;
|
||||
|
||||
if (!(env->psw.mask & PSW_MASK_DAT)) {
|
||||
*raddr = vaddr;
|
||||
goto nodat;
|
||||
}
|
||||
|
||||
switch (asc) {
|
||||
case PSW_ASC_PRIMARY:
|
||||
asce = env->cregs[1];
|
||||
break;
|
||||
case PSW_ASC_HOME:
|
||||
asce = env->cregs[13];
|
||||
break;
|
||||
case PSW_ASC_SECONDARY:
|
||||
asce = env->cregs[7];
|
||||
break;
|
||||
case PSW_ASC_ACCREG:
|
||||
default:
|
||||
// hw_error("guest switched to unknown asc mode\n");
|
||||
break;
|
||||
}
|
||||
|
||||
/* perform the DAT translation */
|
||||
r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw);
|
||||
if (unlikely(r)) {
|
||||
return r;
|
||||
}
|
||||
|
||||
/* check for DAT protection */
|
||||
if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
|
||||
/* DAT sets bit 61 only */
|
||||
*tec |= 0x4;
|
||||
return PGM_PROTECTION;
|
||||
}
|
||||
|
||||
/* check for Instruction-Execution-Protection */
|
||||
if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
|
||||
/* IEP sets bit 56 and 61 */
|
||||
*tec |= 0x84;
|
||||
return PGM_PROTECTION;
|
||||
}
|
||||
|
||||
nodat:
|
||||
/* Convert real address -> absolute address */
|
||||
*raddr = mmu_real2abs(env, *raddr);
|
||||
|
||||
mmu_handle_skey(*raddr, rw, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* translate_pages: Translate a set of consecutive logical page addresses
|
||||
* to absolute addresses. This function is used for TCG and old KVM without
|
||||
* the MEMOP interface.
|
||||
*/
|
||||
static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
|
||||
target_ulong *pages, bool is_write, uint64_t *tec)
|
||||
{
|
||||
uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
|
||||
CPUS390XState *env = &cpu->env;
|
||||
int ret, i, pflags;
|
||||
|
||||
for (i = 0; i < nr_pages; i++) {
|
||||
ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, tec);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
if (!address_space_access_valid(env_cpu(env)->as, pages[i],
|
||||
TARGET_PAGE_SIZE, is_write,
|
||||
MEMTXATTRS_UNSPECIFIED)) {
|
||||
*tec = 0; /* unused */
|
||||
return PGM_ADDRESSING;
|
||||
}
|
||||
addr += TARGET_PAGE_SIZE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* s390_cpu_virt_mem_rw:
|
||||
* @laddr: the logical start address
|
||||
* @ar: the access register number
|
||||
* @hostbuf: buffer in host memory. NULL = do only checks w/o copying
|
||||
* @len: length that should be transferred
|
||||
* @is_write: true = write, false = read
|
||||
* Returns: 0 on success, non-zero if an exception occurred
|
||||
*
|
||||
* Copy from/to guest memory using logical addresses. Note that we inject a
|
||||
* program interrupt in case there is an error while accessing the memory.
|
||||
*
|
||||
* This function will always return (also for TCG), make sure to call
|
||||
* s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
|
||||
*/
|
||||
int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
|
||||
int len, bool is_write)
|
||||
{
|
||||
int currlen, nr_pages, i;
|
||||
target_ulong *pages;
|
||||
uint64_t tec;
|
||||
int ret;
|
||||
CPUS390XState *env = &cpu->env;
|
||||
|
||||
nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
|
||||
+ 1;
|
||||
pages = g_malloc(nr_pages * sizeof(*pages));
|
||||
|
||||
ret = translate_pages(cpu, laddr, nr_pages, pages, is_write, &tec);
|
||||
if (ret) {
|
||||
trigger_access_exception(&cpu->env, ret, tec);
|
||||
} else if (hostbuf != NULL) {
|
||||
/* Copy data by stepping through the area page by page */
|
||||
for (i = 0; i < nr_pages; i++) {
|
||||
currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
|
||||
cpu_physical_memory_rw(env_cpu(env)->as, pages[i] | (laddr & ~TARGET_PAGE_MASK),
|
||||
hostbuf, currlen, is_write);
|
||||
laddr += currlen;
|
||||
hostbuf += currlen;
|
||||
len -= currlen;
|
||||
}
|
||||
}
|
||||
|
||||
g_free(pages);
|
||||
return ret;
|
||||
}
|
||||
|
||||
void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
|
||||
{
|
||||
/* KVM will handle the interrupt automatically, TCG has to exit the TB */
|
||||
cpu_loop_exit_restore(CPU(cpu), ra);
|
||||
}
|
||||
|
||||
/**
|
||||
* Translate a real address into a physical (absolute) address.
|
||||
* @param raddr the real address
|
||||
* @param rw 0 = read, 1 = write, 2 = code fetch
|
||||
* @param addr the translated address is stored to this pointer
|
||||
* @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
|
||||
* @return 0 = success, != 0, the exception to raise
|
||||
*/
|
||||
int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
|
||||
target_ulong *addr, int *flags, uint64_t *tec)
|
||||
{
|
||||
const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
|
||||
|
||||
*flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
|
||||
if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
|
||||
/* see comment in mmu_translate() how this works */
|
||||
*flags |= PAGE_WRITE_INV;
|
||||
if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
|
||||
/* LAP sets bit 56 */
|
||||
*tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80;
|
||||
return PGM_PROTECTION;
|
||||
}
|
||||
}
|
||||
|
||||
*addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
|
||||
|
||||
mmu_handle_skey(*addr, rw, flags);
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user