diff --git a/qemu/target-arm/neon_helper.c b/qemu/target-arm/neon_helper.c
index 308fd713..dc8fb3fd 100644
--- a/qemu/target-arm/neon_helper.c
+++ b/qemu/target-arm/neon_helper.c
@@ -698,7 +698,7 @@ NEON_VOP(rshl_s16, neon_s16, 2)
  * intermediate 64 bit accumulator.  */
 uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)
 {
-    int32_t dest;
+    uint32_t dest;
     int32_t val = (int32_t)valop;
     int8_t shift = (int8_t)shiftop;
     if ((shift >= 32) || (shift <= -32)) {
@@ -707,7 +707,7 @@ uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)
         int64_t big_dest = ((int64_t)val + (1ULL << (-1 - shift)));
         dest = big_dest >> -shift;
     } else {
-        dest = val << shift;
+        dest = (uint32_t)val << shift;
     }
     return dest;
 }
diff --git a/qemu/target-i386/ops_sse.h b/qemu/target-i386/ops_sse.h
index 3d49fcc7..916f83e9 100644
--- a/qemu/target-i386/ops_sse.h
+++ b/qemu/target-i386/ops_sse.h
@@ -1499,7 +1499,7 @@ SSE_HELPER_W(helper_pmulhrsw, FMULHRSW)
 
 #define FSIGNB(d, s) (s <= INT8_MAX  ? s ? d : 0 : -(int8_t)d)
 #define FSIGNW(d, s) (s <= INT16_MAX ? s ? d : 0 : -(int16_t)d)
-#define FSIGNL(d, s) (s <= INT32_MAX ? s ? d : 0 : -(int32_t)d)
+#define FSIGNL(d, s) (s <= INT32_MAX ? s ? d && d != 0x80000000 : 0 : -(int32_t)d)
 SSE_HELPER_B(helper_psignb, FSIGNB)
 SSE_HELPER_W(helper_psignw, FSIGNW)
 SSE_HELPER_L(helper_psignd, FSIGNL)