diff --git a/include/uc_priv.h b/include/uc_priv.h
index 0cb354c1..56973157 100644
--- a/include/uc_priv.h
+++ b/include/uc_priv.h
@@ -13,7 +13,8 @@
 
 // These are masks of supported modes for each cpu/arch.
 // They should be updated when changes are made to the uc_mode enum typedef.
-#define UC_MODE_ARM_MASK    (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS|UC_MODE_BIG_ENDIAN)
+#define UC_MODE_ARM_MASK    (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS \
+				|UC_MODE_ARM926|UC_MODE_ARM946|UC_MODE_ARM1176|UC_MODE_BIG_ENDIAN)
 #define UC_MODE_MIPS_MASK   (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
 #define UC_MODE_X86_MASK    (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN)
 #define UC_MODE_PPC_MASK    (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
diff --git a/include/unicorn/unicorn.h b/include/unicorn/unicorn.h
index f906dee0..9c08eea3 100644
--- a/include/unicorn/unicorn.h
+++ b/include/unicorn/unicorn.h
@@ -102,29 +102,40 @@ typedef enum uc_arch {
 typedef enum uc_mode {
     UC_MODE_LITTLE_ENDIAN = 0,    // little-endian mode (default mode)
     UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
+
     // arm / arm64
     UC_MODE_ARM = 0,              // ARM mode
     UC_MODE_THUMB = 1 << 4,       // THUMB mode (including Thumb-2)
     UC_MODE_MCLASS = 1 << 5,      // ARM's Cortex-M series (currently unsupported)
     UC_MODE_V8 = 1 << 6,          // ARMv8 A32 encodings for ARM (currently unsupported)
+
+    // arm (32bit) cpu types
+    UC_MODE_ARM926 = 1 << 7,	  // ARM926 CPU type
+    UC_MODE_ARM946 = 1 << 8,	  // ARM946 CPU type
+    UC_MODE_ARM1176 = 1 << 9,	  // ARM1176 CPU type
+
     // mips
     UC_MODE_MICRO = 1 << 4,       // MicroMips mode (currently unsupported)
     UC_MODE_MIPS3 = 1 << 5,       // Mips III ISA (currently unsupported)
     UC_MODE_MIPS32R6 = 1 << 6,    // Mips32r6 ISA (currently unsupported)
     UC_MODE_MIPS32 = 1 << 2,      // Mips32 ISA
     UC_MODE_MIPS64 = 1 << 3,      // Mips64 ISA
+
     // x86 / x64
     UC_MODE_16 = 1 << 1,          // 16-bit mode
     UC_MODE_32 = 1 << 2,          // 32-bit mode
     UC_MODE_64 = 1 << 3,          // 64-bit mode
+
     // ppc 
     UC_MODE_PPC32 = 1 << 2,       // 32-bit mode (currently unsupported)
     UC_MODE_PPC64 = 1 << 3,       // 64-bit mode (currently unsupported)
     UC_MODE_QPX = 1 << 4,         // Quad Processing eXtensions mode (currently unsupported)
+
     // sparc
     UC_MODE_SPARC32 = 1 << 2,     // 32-bit mode
     UC_MODE_SPARC64 = 1 << 3,     // 64-bit mode
     UC_MODE_V9 = 1 << 4,          // SparcV9 mode (currently unsupported)
+
     // m68k
 } uc_mode;
 
diff --git a/qemu/hw/arm/tosa.c b/qemu/hw/arm/tosa.c
index 4a79e127..7004fc87 100644
--- a/qemu/hw/arm/tosa.c
+++ b/qemu/hw/arm/tosa.c
@@ -19,11 +19,16 @@
 
 static int tosa_init(struct uc_struct *uc, MachineState *machine)
 {
-    if (uc->mode & UC_MODE_MCLASS) {
+    if (uc->mode & UC_MODE_MCLASS)
         uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-m3");
-    } else {
+    else if (uc->mode & UC_MODE_ARM926)
+        uc->cpu = (CPUState *)cpu_arm_init(uc, "arm926");
+    else if (uc->mode & UC_MODE_ARM946)
+        uc->cpu = (CPUState *)cpu_arm_init(uc, "arm946");
+    else if (uc->mode & UC_MODE_ARM1176)
+        uc->cpu = (CPUState *)cpu_arm_init(uc, "arm1176");
+    else
         uc->cpu = (CPUState *)cpu_arm_init(uc, "cortex-a15");
-    }
 
     return 0;
 }