yizhi-js-lib/favicon-trap
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

fix merge conflicts

Browse Source
This commit is contained in:
Nguyen Anh Quynh
2017-03-10 21:04:33 +08:00
parent f3ada41b99 f2e75422e8
commit c01dcf0a14
41 changed files with 543 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
qemu/target-mips/unicorn.c
View File

@ -18,6 +18,12 @@ const int MIPS_REGS_STORAGE_SIZE = offsetof(CPUMIPSState, tlb_table);
#endif
#endif
#ifdef TARGET_MIPS64
typedef uint64_t mipsreg_t;
#else
typedef uint32_t mipsreg_t;
#endif
static uint64_t mips_mem_redirect(uint64_t address)
{
// kseg0 range masks off high address bit
@ -91,7 +97,7 @@ int mips_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int cou
switch(regid) {
default: break;
case UC_MIPS_REG_PC:
*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
*(mipsreg_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
break;
}
}
@ -109,12 +115,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals,
unsigned int regid = regs[i];
const void *value = vals[i];
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(uint32_t *)value;
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(mipsreg_t *)value;
else {
switch(regid) {
default: break;
case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(uint32_t *)value;
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(mipsreg_t *)value;
// force to quit execution and flush TB
uc->quit_request = true;
uc_emu_stop(uc);