From ca6516ff790f2c6b2bc59a6b7472cb25be0f82b8 Mon Sep 17 00:00:00 2001
From: Chen Huitao <h980501427@163.com>
Date: Sun, 8 Sep 2019 16:44:16 +0800
Subject: [PATCH] Remove warnings (#1140)

* remove warnings on windows with vs2019.

* remove warnings.
---
 qemu/glib_compat.c            | 7 +++++--
 qemu/target-arm/unicorn_arm.c | 5 +++++
 qemu/target-i386/translate.c  | 4 ++--
 qemu/target-m68k/helper.c     | 5 +++--
 qemu/target-m68k/translate.c  | 2 --
 qemu/target-mips/helper.c     | 3 ++-
 6 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/qemu/glib_compat.c b/qemu/glib_compat.c
index 13225524..946e4f0c 100644
--- a/qemu/glib_compat.c
+++ b/qemu/glib_compat.c
@@ -566,7 +566,7 @@ static inline guint g_hash_table_lookup_node_for_insertion (GHashTable    *hash_
   GHashNode *node;
   guint node_index;
   guint hash_value;
-  guint first_tombstone;
+  guint first_tombstone = 0;
   gboolean have_tombstone = FALSE;
   guint step = 0;
 
@@ -1282,7 +1282,10 @@ char *g_strdup_vprintf(const char *format, va_list ap)
        return NULL;
    vsnprintf(str_res, len+1, format, ap);
 #else
-   vasprintf(&str_res, format, ap);
+    int ret = vasprintf(&str_res, format, ap);
+    if (ret == -1) {
+        return NULL;
+    }
 #endif
    return str_res;
 }
diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c
index c5f6e1b8..8e1fa115 100644
--- a/qemu/target-arm/unicorn_arm.c
+++ b/qemu/target-arm/unicorn_arm.c
@@ -47,6 +47,11 @@ void arm_reg_reset(struct uc_struct *uc)
     env->pc = 0;
 }
 
+/* these functions are implemented in helper.c. */
+#include "exec/helper-head.h"
+uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg);
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val);
+
 int arm_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
 {
     CPUState *mycpu;
diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c
index 36fae092..a630c1bb 100644
--- a/qemu/target-i386/translate.c
+++ b/qemu/target-i386/translate.c
@@ -8594,7 +8594,8 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
     target_ulong pc_ptr;
     uint16_t *gen_opc_end;
     CPUBreakpoint *bp;
-    int j, lj;
+    int j;
+    int lj = -1;
     uint64_t flags;
     target_ulong pc_start;
     target_ulong cs_base;
@@ -8698,7 +8699,6 @@ static inline void gen_intermediate_code_internal(uint8_t *gen_opc_cc_op,
     gen_opc_end = tcg_ctx->gen_opc_buf + OPC_MAX_SIZE;
 
     dc->is_jmp = DISAS_NEXT;
-    lj = -1;
     max_insns = tb->cflags & CF_COUNT_MASK;
     if (max_insns == 0)
         max_insns = CF_COUNT_MASK;
diff --git a/qemu/target-m68k/helper.c b/qemu/target-m68k/helper.c
index 78bdd5e6..6e3efc10 100644
--- a/qemu/target-m68k/helper.c
+++ b/qemu/target-m68k/helper.c
@@ -125,10 +125,11 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
     env->cc_dest = flags;
 }
 
+/* this function is implemented in op_helper.c: void HELPER(raise_exception) */
+void raise_exception(CPUM68KState *env, uint32_t tt);
+
 void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
 {
-    M68kCPU *cpu = m68k_env_get_cpu(env);
-
     switch (reg) {
     case 0x02: /* CACR */
         env->cacr = val;
diff --git a/qemu/target-m68k/translate.c b/qemu/target-m68k/translate.c
index a7e4e237..2f4ad1da 100644
--- a/qemu/target-m68k/translate.c
+++ b/qemu/target-m68k/translate.c
@@ -2142,8 +2142,6 @@ DISAS_INSN(wddata)
 
 DISAS_INSN(wdebug)
 {
-    M68kCPU *cpu = m68k_env_get_cpu(env);
-
     if (IS_USER(s)) {
         gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
         return;
diff --git a/qemu/target-mips/helper.c b/qemu/target-mips/helper.c
index 9bf3c0c6..679b793b 100644
--- a/qemu/target-mips/helper.c
+++ b/qemu/target-mips/helper.c
@@ -527,7 +527,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
         break;
     case EXCP_SRESET:
         env->CP0_Status |= (1 << CP0St_SR);
-        memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
+        /* memset CP0_WatchLo which is fixed size array. */
+        memset(env->CP0_WatchLo, 0, sizeof(env->CP0_WatchLo));
         goto set_error_EPC;
     case EXCP_NMI:
         env->CP0_Status |= (1 << CP0St_NMI);