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Regress python testcases must define expected value via unittest

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danghvu
2015-09-17 15:45:15 -05:00
parent 8c163706e4
commit cbb2cf3618
29 changed files with 501 additions and 471 deletions
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33
regress/crash_tb.py
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@ -3,30 +3,35 @@
from unicorn import *
from unicorn.x86_const import *
import regress
CODE_ADDR = 0x0
binary1 = b'\xb8\x02\x00\x00\x00'
binary2 = b'\xb8\x01\x00\x00\x00'
mu = Uc(UC_ARCH_X86, UC_MODE_64)
class CrashTB(regress.RegressTest):
mu.mem_map(CODE_ADDR, 2 * 1024 * 1024)
def runTest(self):
mu = Uc(UC_ARCH_X86, UC_MODE_64)
# write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary1)
mu.mem_map(CODE_ADDR, 2 * 1024 * 1024)
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary1), UC_SECOND_SCALE)
# write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary1)
print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary1), UC_SECOND_SCALE)
# write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary2)
self.assertEqual(0x2, mu.reg_read(UC_X86_REG_RAX))
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary2), UC_SECOND_SCALE)
# write machine code to be emulated to memory
mu.mem_write(CODE_ADDR, binary2)
print("RAX = %x" %mu.reg_read(UC_X86_REG_RAX))
# emu for maximum 1 sec.
mu.emu_start(CODE_ADDR, len(binary2), UC_SECOND_SCALE)
self.assertEqual(0x1, mu.reg_read(UC_X86_REG_RAX))
if __name__ == '__main__':
regress.main()