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python: update consts after the latest change in the core

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This commit is contained in:
Nguyen Anh Quynh
2015-08-24 13:16:22 +08:00
parent 2516de7ed8
commit d64ef59871
9 changed files with 677 additions and 677 deletions
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4
bindings/const_generator.py
View File

@ -50,7 +50,7 @@ def gen(lang):
if line == '' or line.startswith('//'): if line == '' or line.startswith('//'):
continue continue
if not line.startswith(prefix.upper()): if not line.startswith("UC_" + prefix.upper()):
continue continue
tmp = line.strip().split(',') tmp = line.strip().split(',')
@ -59,7 +59,7 @@ def gen(lang):
if not t or t.startswith('//'): continue if not t or t.startswith('//'): continue
f = re.split('\s+', t) f = re.split('\s+', t)
if f[0].startswith(prefix.upper()): if f[0].startswith("UC_" + prefix.upper()):
if len(f) > 1 and f[1] not in '//=': if len(f) > 1 and f[1] not in '//=':
print("Error: Unable to convert %s" % f) print("Error: Unable to convert %s" % f)
continue continue

10
bindings/python/sample_arm.py
View File

@ -38,9 +38,9 @@ def test_arm():
mu.mem_write(ADDRESS, ARM_CODE) mu.mem_write(ADDRESS, ARM_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM_REG_R0, 0x1234) mu.reg_write(UC_ARM_REG_R0, 0x1234)
mu.reg_write(ARM_REG_R2, 0x6789) mu.reg_write(UC_ARM_REG_R2, 0x6789)
mu.reg_write(ARM_REG_R3, 0x3333) mu.reg_write(UC_ARM_REG_R3, 0x3333)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -54,8 +54,8 @@ def test_arm():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r0 = mu.reg_read(ARM_REG_R0) r0 = mu.reg_read(UC_ARM_REG_R0)
r1 = mu.reg_read(ARM_REG_R1) r1 = mu.reg_read(UC_ARM_REG_R1)
print(">>> R0 = 0x%x" %r0) print(">>> R0 = 0x%x" %r0)
print(">>> R1 = 0x%x" %r1) print(">>> R1 = 0x%x" %r1)

12
bindings/python/sample_arm64.py
View File

@ -38,9 +38,9 @@ def test_arm64():
mu.mem_write(ADDRESS, ARM64_CODE) mu.mem_write(ADDRESS, ARM64_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(ARM64_REG_X11, 0x1234) mu.reg_write(UC_ARM64_REG_X11, 0x1234)
mu.reg_write(ARM64_REG_X13, 0x6789) mu.reg_write(UC_ARM64_REG_X13, 0x6789)
mu.reg_write(ARM64_REG_X15, 0x3333) mu.reg_write(UC_ARM64_REG_X15, 0x3333)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -54,9 +54,9 @@ def test_arm64():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
x11 = mu.reg_read(ARM64_REG_X11) x11 = mu.reg_read(UC_ARM64_REG_X11)
x13 = mu.reg_read(ARM64_REG_X13) x13 = mu.reg_read(UC_ARM64_REG_X13)
x15 = mu.reg_read(ARM64_REG_X15) x15 = mu.reg_read(UC_ARM64_REG_X15)
print(">>> X11 = 0x%x" %x11) print(">>> X11 = 0x%x" %x11)
except UcError as e: except UcError as e:

8
bindings/python/sample_mips.py
View File

@ -39,7 +39,7 @@ def test_mips_eb():
mu.mem_write(ADDRESS, MIPS_CODE_EB) mu.mem_write(ADDRESS, MIPS_CODE_EB)
# initialize machine registers # initialize machine registers
mu.reg_write(MIPS_REG_1, 0x6789) mu.reg_write(UC_MIPS_REG_1, 0x6789)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -53,7 +53,7 @@ def test_mips_eb():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r1 = mu.reg_read(MIPS_REG_1) r1 = mu.reg_read(UC_MIPS_REG_1)
print(">>> r1 = 0x%x" %r1) print(">>> r1 = 0x%x" %r1)
except UcError as e: except UcError as e:
@ -74,7 +74,7 @@ def test_mips_el():
mu.mem_write(ADDRESS, MIPS_CODE_EL) mu.mem_write(ADDRESS, MIPS_CODE_EL)
# initialize machine registers # initialize machine registers
mu.reg_write(MIPS_REG_1, 0x6789) mu.reg_write(UC_MIPS_REG_1, 0x6789)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -88,7 +88,7 @@ def test_mips_el():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
r1 = mu.reg_read(MIPS_REG_1) r1 = mu.reg_read(UC_MIPS_REG_1)
print(">>> r1 = 0x%x" %r1) print(">>> r1 = 0x%x" %r1)
except UcError as e: except UcError as e:

8
bindings/python/sample_sparc.py
View File

@ -37,9 +37,9 @@ def test_sparc():
mu.mem_write(ADDRESS, SPARC_CODE) mu.mem_write(ADDRESS, SPARC_CODE)
# initialize machine registers # initialize machine registers
mu.reg_write(SPARC_REG_G1, 0x1230) mu.reg_write(UC_SPARC_REG_G1, 0x1230)
mu.reg_write(SPARC_REG_G2, 0x6789) mu.reg_write(UC_SPARC_REG_G2, 0x6789)
mu.reg_write(SPARC_REG_G3, 0x5555) mu.reg_write(UC_SPARC_REG_G3, 0x5555)
# tracing all basic blocks with customized callback # tracing all basic blocks with customized callback
mu.hook_add(UC_HOOK_BLOCK, hook_block) mu.hook_add(UC_HOOK_BLOCK, hook_block)
@ -53,7 +53,7 @@ def test_sparc():
# now print out some registers # now print out some registers
print(">>> Emulation done. Below is the CPU context") print(">>> Emulation done. Below is the CPU context")
g3 = mu.reg_read(SPARC_REG_G3) g3 = mu.reg_read(UC_SPARC_REG_G3)
print(">>> G3 = 0x%x" %g3) print(">>> G3 = 0x%x" %g3)
except UcError as e: except UcError as e:

532
bindings/python/unicorn/arm64_const.py
View File

@ -2,273 +2,273 @@
# ARM64 registers # ARM64 registers
ARM64_REG_INVALID = 0 UC_ARM64_REG_INVALID = 0
ARM64_REG_X29 = 1 UC_ARM64_REG_X29 = 1
ARM64_REG_X30 = 2 UC_ARM64_REG_X30 = 2
ARM64_REG_NZCV = 3 UC_ARM64_REG_NZCV = 3
ARM64_REG_SP = 4 UC_ARM64_REG_SP = 4
ARM64_REG_WSP = 5 UC_ARM64_REG_WSP = 5
ARM64_REG_WZR = 6 UC_ARM64_REG_WZR = 6
ARM64_REG_XZR = 7 UC_ARM64_REG_XZR = 7
ARM64_REG_B0 = 8 UC_ARM64_REG_B0 = 8
ARM64_REG_B1 = 9 UC_ARM64_REG_B1 = 9
ARM64_REG_B2 = 10 UC_ARM64_REG_B2 = 10
ARM64_REG_B3 = 11 UC_ARM64_REG_B3 = 11
ARM64_REG_B4 = 12 UC_ARM64_REG_B4 = 12
ARM64_REG_B5 = 13 UC_ARM64_REG_B5 = 13
ARM64_REG_B6 = 14 UC_ARM64_REG_B6 = 14
ARM64_REG_B7 = 15 UC_ARM64_REG_B7 = 15
ARM64_REG_B8 = 16 UC_ARM64_REG_B8 = 16
ARM64_REG_B9 = 17 UC_ARM64_REG_B9 = 17
ARM64_REG_B10 = 18 UC_ARM64_REG_B10 = 18
ARM64_REG_B11 = 19 UC_ARM64_REG_B11 = 19
ARM64_REG_B12 = 20 UC_ARM64_REG_B12 = 20
ARM64_REG_B13 = 21 UC_ARM64_REG_B13 = 21
ARM64_REG_B14 = 22 UC_ARM64_REG_B14 = 22
ARM64_REG_B15 = 23 UC_ARM64_REG_B15 = 23
ARM64_REG_B16 = 24 UC_ARM64_REG_B16 = 24
ARM64_REG_B17 = 25 UC_ARM64_REG_B17 = 25
ARM64_REG_B18 = 26 UC_ARM64_REG_B18 = 26
ARM64_REG_B19 = 27 UC_ARM64_REG_B19 = 27
ARM64_REG_B20 = 28 UC_ARM64_REG_B20 = 28
ARM64_REG_B21 = 29 UC_ARM64_REG_B21 = 29
ARM64_REG_B22 = 30 UC_ARM64_REG_B22 = 30
ARM64_REG_B23 = 31 UC_ARM64_REG_B23 = 31
ARM64_REG_B24 = 32 UC_ARM64_REG_B24 = 32
ARM64_REG_B25 = 33 UC_ARM64_REG_B25 = 33
ARM64_REG_B26 = 34 UC_ARM64_REG_B26 = 34
ARM64_REG_B27 = 35 UC_ARM64_REG_B27 = 35
ARM64_REG_B28 = 36 UC_ARM64_REG_B28 = 36
ARM64_REG_B29 = 37 UC_ARM64_REG_B29 = 37
ARM64_REG_B30 = 38 UC_ARM64_REG_B30 = 38
ARM64_REG_B31 = 39 UC_ARM64_REG_B31 = 39
ARM64_REG_D0 = 40 UC_ARM64_REG_D0 = 40
ARM64_REG_D1 = 41 UC_ARM64_REG_D1 = 41
ARM64_REG_D2 = 42 UC_ARM64_REG_D2 = 42
ARM64_REG_D3 = 43 UC_ARM64_REG_D3 = 43
ARM64_REG_D4 = 44 UC_ARM64_REG_D4 = 44
ARM64_REG_D5 = 45 UC_ARM64_REG_D5 = 45
ARM64_REG_D6 = 46 UC_ARM64_REG_D6 = 46
ARM64_REG_D7 = 47 UC_ARM64_REG_D7 = 47
ARM64_REG_D8 = 48 UC_ARM64_REG_D8 = 48
ARM64_REG_D9 = 49 UC_ARM64_REG_D9 = 49
ARM64_REG_D10 = 50 UC_ARM64_REG_D10 = 50
ARM64_REG_D11 = 51 UC_ARM64_REG_D11 = 51
ARM64_REG_D12 = 52 UC_ARM64_REG_D12 = 52
ARM64_REG_D13 = 53 UC_ARM64_REG_D13 = 53
ARM64_REG_D14 = 54 UC_ARM64_REG_D14 = 54
ARM64_REG_D15 = 55 UC_ARM64_REG_D15 = 55
ARM64_REG_D16 = 56 UC_ARM64_REG_D16 = 56
ARM64_REG_D17 = 57 UC_ARM64_REG_D17 = 57
ARM64_REG_D18 = 58 UC_ARM64_REG_D18 = 58
ARM64_REG_D19 = 59 UC_ARM64_REG_D19 = 59
ARM64_REG_D20 = 60 UC_ARM64_REG_D20 = 60
ARM64_REG_D21 = 61 UC_ARM64_REG_D21 = 61
ARM64_REG_D22 = 62 UC_ARM64_REG_D22 = 62
ARM64_REG_D23 = 63 UC_ARM64_REG_D23 = 63
ARM64_REG_D24 = 64 UC_ARM64_REG_D24 = 64
ARM64_REG_D25 = 65 UC_ARM64_REG_D25 = 65
ARM64_REG_D26 = 66 UC_ARM64_REG_D26 = 66
ARM64_REG_D27 = 67 UC_ARM64_REG_D27 = 67
ARM64_REG_D28 = 68 UC_ARM64_REG_D28 = 68
ARM64_REG_D29 = 69 UC_ARM64_REG_D29 = 69
ARM64_REG_D30 = 70 UC_ARM64_REG_D30 = 70
ARM64_REG_D31 = 71 UC_ARM64_REG_D31 = 71
ARM64_REG_H0 = 72 UC_ARM64_REG_H0 = 72
ARM64_REG_H1 = 73 UC_ARM64_REG_H1 = 73
ARM64_REG_H2 = 74 UC_ARM64_REG_H2 = 74
ARM64_REG_H3 = 75 UC_ARM64_REG_H3 = 75
ARM64_REG_H4 = 76 UC_ARM64_REG_H4 = 76
ARM64_REG_H5 = 77 UC_ARM64_REG_H5 = 77
ARM64_REG_H6 = 78 UC_ARM64_REG_H6 = 78
ARM64_REG_H7 = 79 UC_ARM64_REG_H7 = 79
ARM64_REG_H8 = 80 UC_ARM64_REG_H8 = 80
ARM64_REG_H9 = 81 UC_ARM64_REG_H9 = 81
ARM64_REG_H10 = 82 UC_ARM64_REG_H10 = 82
ARM64_REG_H11 = 83 UC_ARM64_REG_H11 = 83
ARM64_REG_H12 = 84 UC_ARM64_REG_H12 = 84
ARM64_REG_H13 = 85 UC_ARM64_REG_H13 = 85
ARM64_REG_H14 = 86 UC_ARM64_REG_H14 = 86
ARM64_REG_H15 = 87 UC_ARM64_REG_H15 = 87
ARM64_REG_H16 = 88 UC_ARM64_REG_H16 = 88
ARM64_REG_H17 = 89 UC_ARM64_REG_H17 = 89
ARM64_REG_H18 = 90 UC_ARM64_REG_H18 = 90
ARM64_REG_H19 = 91 UC_ARM64_REG_H19 = 91
ARM64_REG_H20 = 92 UC_ARM64_REG_H20 = 92
ARM64_REG_H21 = 93 UC_ARM64_REG_H21 = 93
ARM64_REG_H22 = 94 UC_ARM64_REG_H22 = 94
ARM64_REG_H23 = 95 UC_ARM64_REG_H23 = 95
ARM64_REG_H24 = 96 UC_ARM64_REG_H24 = 96
ARM64_REG_H25 = 97 UC_ARM64_REG_H25 = 97
ARM64_REG_H26 = 98 UC_ARM64_REG_H26 = 98
ARM64_REG_H27 = 99 UC_ARM64_REG_H27 = 99
ARM64_REG_H28 = 100 UC_ARM64_REG_H28 = 100
ARM64_REG_H29 = 101 UC_ARM64_REG_H29 = 101
ARM64_REG_H30 = 102 UC_ARM64_REG_H30 = 102
ARM64_REG_H31 = 103 UC_ARM64_REG_H31 = 103
ARM64_REG_Q0 = 104 UC_ARM64_REG_Q0 = 104
ARM64_REG_Q1 = 105 UC_ARM64_REG_Q1 = 105
ARM64_REG_Q2 = 106 UC_ARM64_REG_Q2 = 106
ARM64_REG_Q3 = 107 UC_ARM64_REG_Q3 = 107
ARM64_REG_Q4 = 108 UC_ARM64_REG_Q4 = 108
ARM64_REG_Q5 = 109 UC_ARM64_REG_Q5 = 109
ARM64_REG_Q6 = 110 UC_ARM64_REG_Q6 = 110
ARM64_REG_Q7 = 111 UC_ARM64_REG_Q7 = 111
ARM64_REG_Q8 = 112 UC_ARM64_REG_Q8 = 112
ARM64_REG_Q9 = 113 UC_ARM64_REG_Q9 = 113
ARM64_REG_Q10 = 114 UC_ARM64_REG_Q10 = 114
ARM64_REG_Q11 = 115 UC_ARM64_REG_Q11 = 115
ARM64_REG_Q12 = 116 UC_ARM64_REG_Q12 = 116
ARM64_REG_Q13 = 117 UC_ARM64_REG_Q13 = 117
ARM64_REG_Q14 = 118 UC_ARM64_REG_Q14 = 118
ARM64_REG_Q15 = 119 UC_ARM64_REG_Q15 = 119
ARM64_REG_Q16 = 120 UC_ARM64_REG_Q16 = 120
ARM64_REG_Q17 = 121 UC_ARM64_REG_Q17 = 121
ARM64_REG_Q18 = 122 UC_ARM64_REG_Q18 = 122
ARM64_REG_Q19 = 123 UC_ARM64_REG_Q19 = 123
ARM64_REG_Q20 = 124 UC_ARM64_REG_Q20 = 124
ARM64_REG_Q21 = 125 UC_ARM64_REG_Q21 = 125
ARM64_REG_Q22 = 126 UC_ARM64_REG_Q22 = 126
ARM64_REG_Q23 = 127 UC_ARM64_REG_Q23 = 127
ARM64_REG_Q24 = 128 UC_ARM64_REG_Q24 = 128
ARM64_REG_Q25 = 129 UC_ARM64_REG_Q25 = 129
ARM64_REG_Q26 = 130 UC_ARM64_REG_Q26 = 130
ARM64_REG_Q27 = 131 UC_ARM64_REG_Q27 = 131
ARM64_REG_Q28 = 132 UC_ARM64_REG_Q28 = 132
ARM64_REG_Q29 = 133 UC_ARM64_REG_Q29 = 133
ARM64_REG_Q30 = 134 UC_ARM64_REG_Q30 = 134
ARM64_REG_Q31 = 135 UC_ARM64_REG_Q31 = 135
ARM64_REG_S0 = 136 UC_ARM64_REG_S0 = 136
ARM64_REG_S1 = 137 UC_ARM64_REG_S1 = 137
ARM64_REG_S2 = 138 UC_ARM64_REG_S2 = 138
ARM64_REG_S3 = 139 UC_ARM64_REG_S3 = 139
ARM64_REG_S4 = 140 UC_ARM64_REG_S4 = 140
ARM64_REG_S5 = 141 UC_ARM64_REG_S5 = 141
ARM64_REG_S6 = 142 UC_ARM64_REG_S6 = 142
ARM64_REG_S7 = 143 UC_ARM64_REG_S7 = 143
ARM64_REG_S8 = 144 UC_ARM64_REG_S8 = 144
ARM64_REG_S9 = 145 UC_ARM64_REG_S9 = 145
ARM64_REG_S10 = 146 UC_ARM64_REG_S10 = 146
ARM64_REG_S11 = 147 UC_ARM64_REG_S11 = 147
ARM64_REG_S12 = 148 UC_ARM64_REG_S12 = 148
ARM64_REG_S13 = 149 UC_ARM64_REG_S13 = 149
ARM64_REG_S14 = 150 UC_ARM64_REG_S14 = 150
ARM64_REG_S15 = 151 UC_ARM64_REG_S15 = 151
ARM64_REG_S16 = 152 UC_ARM64_REG_S16 = 152
ARM64_REG_S17 = 153 UC_ARM64_REG_S17 = 153
ARM64_REG_S18 = 154 UC_ARM64_REG_S18 = 154
ARM64_REG_S19 = 155 UC_ARM64_REG_S19 = 155
ARM64_REG_S20 = 156 UC_ARM64_REG_S20 = 156
ARM64_REG_S21 = 157 UC_ARM64_REG_S21 = 157
ARM64_REG_S22 = 158 UC_ARM64_REG_S22 = 158
ARM64_REG_S23 = 159 UC_ARM64_REG_S23 = 159
ARM64_REG_S24 = 160 UC_ARM64_REG_S24 = 160
ARM64_REG_S25 = 161 UC_ARM64_REG_S25 = 161
ARM64_REG_S26 = 162 UC_ARM64_REG_S26 = 162
ARM64_REG_S27 = 163 UC_ARM64_REG_S27 = 163
ARM64_REG_S28 = 164 UC_ARM64_REG_S28 = 164
ARM64_REG_S29 = 165 UC_ARM64_REG_S29 = 165
ARM64_REG_S30 = 166 UC_ARM64_REG_S30 = 166
ARM64_REG_S31 = 167 UC_ARM64_REG_S31 = 167
ARM64_REG_W0 = 168 UC_ARM64_REG_W0 = 168
ARM64_REG_W1 = 169 UC_ARM64_REG_W1 = 169
ARM64_REG_W2 = 170 UC_ARM64_REG_W2 = 170
ARM64_REG_W3 = 171 UC_ARM64_REG_W3 = 171
ARM64_REG_W4 = 172 UC_ARM64_REG_W4 = 172
ARM64_REG_W5 = 173 UC_ARM64_REG_W5 = 173
ARM64_REG_W6 = 174 UC_ARM64_REG_W6 = 174
ARM64_REG_W7 = 175 UC_ARM64_REG_W7 = 175
ARM64_REG_W8 = 176 UC_ARM64_REG_W8 = 176
ARM64_REG_W9 = 177 UC_ARM64_REG_W9 = 177
ARM64_REG_W10 = 178 UC_ARM64_REG_W10 = 178
ARM64_REG_W11 = 179 UC_ARM64_REG_W11 = 179
ARM64_REG_W12 = 180 UC_ARM64_REG_W12 = 180
ARM64_REG_W13 = 181 UC_ARM64_REG_W13 = 181
ARM64_REG_W14 = 182 UC_ARM64_REG_W14 = 182
ARM64_REG_W15 = 183 UC_ARM64_REG_W15 = 183
ARM64_REG_W16 = 184 UC_ARM64_REG_W16 = 184
ARM64_REG_W17 = 185 UC_ARM64_REG_W17 = 185
ARM64_REG_W18 = 186 UC_ARM64_REG_W18 = 186
ARM64_REG_W19 = 187 UC_ARM64_REG_W19 = 187
ARM64_REG_W20 = 188 UC_ARM64_REG_W20 = 188
ARM64_REG_W21 = 189 UC_ARM64_REG_W21 = 189
ARM64_REG_W22 = 190 UC_ARM64_REG_W22 = 190
ARM64_REG_W23 = 191 UC_ARM64_REG_W23 = 191
ARM64_REG_W24 = 192 UC_ARM64_REG_W24 = 192
ARM64_REG_W25 = 193 UC_ARM64_REG_W25 = 193
ARM64_REG_W26 = 194 UC_ARM64_REG_W26 = 194
ARM64_REG_W27 = 195 UC_ARM64_REG_W27 = 195
ARM64_REG_W28 = 196 UC_ARM64_REG_W28 = 196
ARM64_REG_W29 = 197 UC_ARM64_REG_W29 = 197
ARM64_REG_W30 = 198 UC_ARM64_REG_W30 = 198
ARM64_REG_X0 = 199 UC_ARM64_REG_X0 = 199
ARM64_REG_X1 = 200 UC_ARM64_REG_X1 = 200
ARM64_REG_X2 = 201 UC_ARM64_REG_X2 = 201
ARM64_REG_X3 = 202 UC_ARM64_REG_X3 = 202
ARM64_REG_X4 = 203 UC_ARM64_REG_X4 = 203
ARM64_REG_X5 = 204 UC_ARM64_REG_X5 = 204
ARM64_REG_X6 = 205 UC_ARM64_REG_X6 = 205
ARM64_REG_X7 = 206 UC_ARM64_REG_X7 = 206
ARM64_REG_X8 = 207 UC_ARM64_REG_X8 = 207
ARM64_REG_X9 = 208 UC_ARM64_REG_X9 = 208
ARM64_REG_X10 = 209 UC_ARM64_REG_X10 = 209
ARM64_REG_X11 = 210 UC_ARM64_REG_X11 = 210
ARM64_REG_X12 = 211 UC_ARM64_REG_X12 = 211
ARM64_REG_X13 = 212 UC_ARM64_REG_X13 = 212
ARM64_REG_X14 = 213 UC_ARM64_REG_X14 = 213
ARM64_REG_X15 = 214 UC_ARM64_REG_X15 = 214
ARM64_REG_X16 = 215 UC_ARM64_REG_X16 = 215
ARM64_REG_X17 = 216 UC_ARM64_REG_X17 = 216
ARM64_REG_X18 = 217 UC_ARM64_REG_X18 = 217
ARM64_REG_X19 = 218 UC_ARM64_REG_X19 = 218
ARM64_REG_X20 = 219 UC_ARM64_REG_X20 = 219
ARM64_REG_X21 = 220 UC_ARM64_REG_X21 = 220
ARM64_REG_X22 = 221 UC_ARM64_REG_X22 = 221
ARM64_REG_X23 = 222 UC_ARM64_REG_X23 = 222
ARM64_REG_X24 = 223 UC_ARM64_REG_X24 = 223
ARM64_REG_X25 = 224 UC_ARM64_REG_X25 = 224
ARM64_REG_X26 = 225 UC_ARM64_REG_X26 = 225
ARM64_REG_X27 = 226 UC_ARM64_REG_X27 = 226
ARM64_REG_X28 = 227 UC_ARM64_REG_X28 = 227
ARM64_REG_V0 = 228 UC_ARM64_REG_V0 = 228
ARM64_REG_V1 = 229 UC_ARM64_REG_V1 = 229
ARM64_REG_V2 = 230 UC_ARM64_REG_V2 = 230
ARM64_REG_V3 = 231 UC_ARM64_REG_V3 = 231
ARM64_REG_V4 = 232 UC_ARM64_REG_V4 = 232
ARM64_REG_V5 = 233 UC_ARM64_REG_V5 = 233
ARM64_REG_V6 = 234 UC_ARM64_REG_V6 = 234
ARM64_REG_V7 = 235 UC_ARM64_REG_V7 = 235
ARM64_REG_V8 = 236 UC_ARM64_REG_V8 = 236
ARM64_REG_V9 = 237 UC_ARM64_REG_V9 = 237
ARM64_REG_V10 = 238 UC_ARM64_REG_V10 = 238
ARM64_REG_V11 = 239 UC_ARM64_REG_V11 = 239
ARM64_REG_V12 = 240 UC_ARM64_REG_V12 = 240
ARM64_REG_V13 = 241 UC_ARM64_REG_V13 = 241
ARM64_REG_V14 = 242 UC_ARM64_REG_V14 = 242
ARM64_REG_V15 = 243 UC_ARM64_REG_V15 = 243
ARM64_REG_V16 = 244 UC_ARM64_REG_V16 = 244
ARM64_REG_V17 = 245 UC_ARM64_REG_V17 = 245
ARM64_REG_V18 = 246 UC_ARM64_REG_V18 = 246
ARM64_REG_V19 = 247 UC_ARM64_REG_V19 = 247
ARM64_REG_V20 = 248 UC_ARM64_REG_V20 = 248
ARM64_REG_V21 = 249 UC_ARM64_REG_V21 = 249
ARM64_REG_V22 = 250 UC_ARM64_REG_V22 = 250
ARM64_REG_V23 = 251 UC_ARM64_REG_V23 = 251
ARM64_REG_V24 = 252 UC_ARM64_REG_V24 = 252
ARM64_REG_V25 = 253 UC_ARM64_REG_V25 = 253
ARM64_REG_V26 = 254 UC_ARM64_REG_V26 = 254
ARM64_REG_V27 = 255 UC_ARM64_REG_V27 = 255
ARM64_REG_V28 = 256 UC_ARM64_REG_V28 = 256
ARM64_REG_V29 = 257 UC_ARM64_REG_V29 = 257
ARM64_REG_V30 = 258 UC_ARM64_REG_V30 = 258
ARM64_REG_V31 = 259 UC_ARM64_REG_V31 = 259
# pseudo registers # pseudo registers
ARM64_REG_PC = 260 UC_ARM64_REG_PC = 260
ARM64_REG_ENDING = 261 UC_ARM64_REG_ENDING = 261
# alias registers # alias registers
ARM64_REG_IP1 = ARM64_REG_X16 UC_ARM64_REG_IP1 = UC_ARM64_REG_X16
ARM64_REG_IP0 = ARM64_REG_X17 UC_ARM64_REG_IP0 = UC_ARM64_REG_X17
ARM64_REG_FP = ARM64_REG_X29 UC_ARM64_REG_FP = UC_ARM64_REG_X29
ARM64_REG_LR = ARM64_REG_X30 UC_ARM64_REG_LR = UC_ARM64_REG_X30

238
bindings/python/unicorn/arm_const.py
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@ -2,124 +2,124 @@
# ARM registers # ARM registers
ARM_REG_INVALID = 0 UC_ARM_REG_INVALID = 0
ARM_REG_APSR = 1 UC_ARM_REG_APSR = 1
ARM_REG_APSR_NZCV = 2 UC_ARM_REG_APSR_NZCV = 2
ARM_REG_CPSR = 3 UC_ARM_REG_CPSR = 3
ARM_REG_FPEXC = 4 UC_ARM_REG_FPEXC = 4
ARM_REG_FPINST = 5 UC_ARM_REG_FPINST = 5
ARM_REG_FPSCR = 6 UC_ARM_REG_FPSCR = 6
ARM_REG_FPSCR_NZCV = 7 UC_ARM_REG_FPSCR_NZCV = 7
ARM_REG_FPSID = 8 UC_ARM_REG_FPSID = 8
ARM_REG_ITSTATE = 9 UC_ARM_REG_ITSTATE = 9
ARM_REG_LR = 10 UC_ARM_REG_LR = 10
ARM_REG_PC = 11 UC_ARM_REG_PC = 11
ARM_REG_SP = 12 UC_ARM_REG_SP = 12
ARM_REG_SPSR = 13 UC_ARM_REG_SPSR = 13
ARM_REG_D0 = 14 UC_ARM_REG_D0 = 14
ARM_REG_D1 = 15 UC_ARM_REG_D1 = 15
ARM_REG_D2 = 16 UC_ARM_REG_D2 = 16
ARM_REG_D3 = 17 UC_ARM_REG_D3 = 17
ARM_REG_D4 = 18 UC_ARM_REG_D4 = 18
ARM_REG_D5 = 19 UC_ARM_REG_D5 = 19
ARM_REG_D6 = 20 UC_ARM_REG_D6 = 20
ARM_REG_D7 = 21 UC_ARM_REG_D7 = 21
ARM_REG_D8 = 22 UC_ARM_REG_D8 = 22
ARM_REG_D9 = 23 UC_ARM_REG_D9 = 23
ARM_REG_D10 = 24 UC_ARM_REG_D10 = 24
ARM_REG_D11 = 25 UC_ARM_REG_D11 = 25
ARM_REG_D12 = 26 UC_ARM_REG_D12 = 26
ARM_REG_D13 = 27 UC_ARM_REG_D13 = 27
ARM_REG_D14 = 28 UC_ARM_REG_D14 = 28
ARM_REG_D15 = 29 UC_ARM_REG_D15 = 29
ARM_REG_D16 = 30 UC_ARM_REG_D16 = 30
ARM_REG_D17 = 31 UC_ARM_REG_D17 = 31
ARM_REG_D18 = 32 UC_ARM_REG_D18 = 32
ARM_REG_D19 = 33 UC_ARM_REG_D19 = 33
ARM_REG_D20 = 34 UC_ARM_REG_D20 = 34
ARM_REG_D21 = 35 UC_ARM_REG_D21 = 35
ARM_REG_D22 = 36 UC_ARM_REG_D22 = 36
ARM_REG_D23 = 37 UC_ARM_REG_D23 = 37
ARM_REG_D24 = 38 UC_ARM_REG_D24 = 38
ARM_REG_D25 = 39 UC_ARM_REG_D25 = 39
ARM_REG_D26 = 40 UC_ARM_REG_D26 = 40
ARM_REG_D27 = 41 UC_ARM_REG_D27 = 41
ARM_REG_D28 = 42 UC_ARM_REG_D28 = 42
ARM_REG_D29 = 43 UC_ARM_REG_D29 = 43
ARM_REG_D30 = 44 UC_ARM_REG_D30 = 44
ARM_REG_D31 = 45 UC_ARM_REG_D31 = 45
ARM_REG_FPINST2 = 46 UC_ARM_REG_FPINST2 = 46
ARM_REG_MVFR0 = 47 UC_ARM_REG_MVFR0 = 47
ARM_REG_MVFR1 = 48 UC_ARM_REG_MVFR1 = 48
ARM_REG_MVFR2 = 49 UC_ARM_REG_MVFR2 = 49
ARM_REG_Q0 = 50 UC_ARM_REG_Q0 = 50
ARM_REG_Q1 = 51 UC_ARM_REG_Q1 = 51
ARM_REG_Q2 = 52 UC_ARM_REG_Q2 = 52
ARM_REG_Q3 = 53 UC_ARM_REG_Q3 = 53
ARM_REG_Q4 = 54 UC_ARM_REG_Q4 = 54
ARM_REG_Q5 = 55 UC_ARM_REG_Q5 = 55
ARM_REG_Q6 = 56 UC_ARM_REG_Q6 = 56
ARM_REG_Q7 = 57 UC_ARM_REG_Q7 = 57
ARM_REG_Q8 = 58 UC_ARM_REG_Q8 = 58
ARM_REG_Q9 = 59 UC_ARM_REG_Q9 = 59
ARM_REG_Q10 = 60 UC_ARM_REG_Q10 = 60
ARM_REG_Q11 = 61 UC_ARM_REG_Q11 = 61
ARM_REG_Q12 = 62 UC_ARM_REG_Q12 = 62
ARM_REG_Q13 = 63 UC_ARM_REG_Q13 = 63
ARM_REG_Q14 = 64 UC_ARM_REG_Q14 = 64
ARM_REG_Q15 = 65 UC_ARM_REG_Q15 = 65
ARM_REG_R0 = 66 UC_ARM_REG_R0 = 66
ARM_REG_R1 = 67 UC_ARM_REG_R1 = 67
ARM_REG_R2 = 68 UC_ARM_REG_R2 = 68
ARM_REG_R3 = 69 UC_ARM_REG_R3 = 69
ARM_REG_R4 = 70 UC_ARM_REG_R4 = 70
ARM_REG_R5 = 71 UC_ARM_REG_R5 = 71
ARM_REG_R6 = 72 UC_ARM_REG_R6 = 72
ARM_REG_R7 = 73 UC_ARM_REG_R7 = 73
ARM_REG_R8 = 74 UC_ARM_REG_R8 = 74
ARM_REG_R9 = 75 UC_ARM_REG_R9 = 75
ARM_REG_R10 = 76 UC_ARM_REG_R10 = 76
ARM_REG_R11 = 77 UC_ARM_REG_R11 = 77
ARM_REG_R12 = 78 UC_ARM_REG_R12 = 78
ARM_REG_S0 = 79 UC_ARM_REG_S0 = 79
ARM_REG_S1 = 80 UC_ARM_REG_S1 = 80
ARM_REG_S2 = 81 UC_ARM_REG_S2 = 81
ARM_REG_S3 = 82 UC_ARM_REG_S3 = 82
ARM_REG_S4 = 83 UC_ARM_REG_S4 = 83
ARM_REG_S5 = 84 UC_ARM_REG_S5 = 84
ARM_REG_S6 = 85 UC_ARM_REG_S6 = 85
ARM_REG_S7 = 86 UC_ARM_REG_S7 = 86
ARM_REG_S8 = 87 UC_ARM_REG_S8 = 87
ARM_REG_S9 = 88 UC_ARM_REG_S9 = 88
ARM_REG_S10 = 89 UC_ARM_REG_S10 = 89
ARM_REG_S11 = 90 UC_ARM_REG_S11 = 90
ARM_REG_S12 = 91 UC_ARM_REG_S12 = 91
ARM_REG_S13 = 92 UC_ARM_REG_S13 = 92
ARM_REG_S14 = 93 UC_ARM_REG_S14 = 93
ARM_REG_S15 = 94 UC_ARM_REG_S15 = 94
ARM_REG_S16 = 95 UC_ARM_REG_S16 = 95
ARM_REG_S17 = 96 UC_ARM_REG_S17 = 96
ARM_REG_S18 = 97 UC_ARM_REG_S18 = 97
ARM_REG_S19 = 98 UC_ARM_REG_S19 = 98
ARM_REG_S20 = 99 UC_ARM_REG_S20 = 99
ARM_REG_S21 = 100 UC_ARM_REG_S21 = 100
ARM_REG_S22 = 101 UC_ARM_REG_S22 = 101
ARM_REG_S23 = 102 UC_ARM_REG_S23 = 102
ARM_REG_S24 = 103 UC_ARM_REG_S24 = 103
ARM_REG_S25 = 104 UC_ARM_REG_S25 = 104
ARM_REG_S26 = 105 UC_ARM_REG_S26 = 105
ARM_REG_S27 = 106 UC_ARM_REG_S27 = 106
ARM_REG_S28 = 107 UC_ARM_REG_S28 = 107
ARM_REG_S29 = 108 UC_ARM_REG_S29 = 108
ARM_REG_S30 = 109 UC_ARM_REG_S30 = 109
ARM_REG_S31 = 110 UC_ARM_REG_S31 = 110
ARM_REG_ENDING = 111 UC_ARM_REG_ENDING = 111
# alias registers # alias registers
ARM_REG_R13 = ARM_REG_SP UC_ARM_REG_R13 = UC_ARM_REG_SP
ARM_REG_R14 = ARM_REG_LR UC_ARM_REG_R14 = UC_ARM_REG_LR
ARM_REG_R15 = ARM_REG_PC UC_ARM_REG_R15 = UC_ARM_REG_PC
ARM_REG_SB = ARM_REG_R9 UC_ARM_REG_SB = UC_ARM_REG_R9
ARM_REG_SL = ARM_REG_R10 UC_ARM_REG_SL = UC_ARM_REG_R10
ARM_REG_FP = ARM_REG_R11 UC_ARM_REG_FP = UC_ARM_REG_R11
ARM_REG_IP = ARM_REG_R12 UC_ARM_REG_IP = UC_ARM_REG_R12

358
bindings/python/unicorn/mips_const.py
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@ -2,194 +2,194 @@
# MIPS registers # MIPS registers
MIPS_REG_INVALID = 0 UC_MIPS_REG_INVALID = 0
# General purpose registers # General purpose registers
MIPS_REG_PC = 1 UC_MIPS_REG_PC = 1
MIPS_REG_0 = 2 UC_MIPS_REG_0 = 2
MIPS_REG_1 = 3 UC_MIPS_REG_1 = 3
MIPS_REG_2 = 4 UC_MIPS_REG_2 = 4
MIPS_REG_3 = 5 UC_MIPS_REG_3 = 5
MIPS_REG_4 = 6 UC_MIPS_REG_4 = 6
MIPS_REG_5 = 7 UC_MIPS_REG_5 = 7
MIPS_REG_6 = 8 UC_MIPS_REG_6 = 8
MIPS_REG_7 = 9 UC_MIPS_REG_7 = 9
MIPS_REG_8 = 10 UC_MIPS_REG_8 = 10
MIPS_REG_9 = 11 UC_MIPS_REG_9 = 11
MIPS_REG_10 = 12 UC_MIPS_REG_10 = 12
MIPS_REG_11 = 13 UC_MIPS_REG_11 = 13
MIPS_REG_12 = 14 UC_MIPS_REG_12 = 14
MIPS_REG_13 = 15 UC_MIPS_REG_13 = 15
MIPS_REG_14 = 16 UC_MIPS_REG_14 = 16
MIPS_REG_15 = 17 UC_MIPS_REG_15 = 17
MIPS_REG_16 = 18 UC_MIPS_REG_16 = 18
MIPS_REG_17 = 19 UC_MIPS_REG_17 = 19
MIPS_REG_18 = 20 UC_MIPS_REG_18 = 20
MIPS_REG_19 = 21 UC_MIPS_REG_19 = 21
MIPS_REG_20 = 22 UC_MIPS_REG_20 = 22
MIPS_REG_21 = 23 UC_MIPS_REG_21 = 23
MIPS_REG_22 = 24 UC_MIPS_REG_22 = 24
MIPS_REG_23 = 25 UC_MIPS_REG_23 = 25
MIPS_REG_24 = 26 UC_MIPS_REG_24 = 26
MIPS_REG_25 = 27 UC_MIPS_REG_25 = 27
MIPS_REG_26 = 28 UC_MIPS_REG_26 = 28
MIPS_REG_27 = 29 UC_MIPS_REG_27 = 29
MIPS_REG_28 = 30 UC_MIPS_REG_28 = 30
MIPS_REG_29 = 31 UC_MIPS_REG_29 = 31
MIPS_REG_30 = 32 UC_MIPS_REG_30 = 32
MIPS_REG_31 = 33 UC_MIPS_REG_31 = 33
# DSP registers # DSP registers
MIPS_REG_DSPCCOND = 34 UC_MIPS_REG_DSPCCOND = 34
MIPS_REG_DSPCARRY = 35 UC_MIPS_REG_DSPCARRY = 35
MIPS_REG_DSPEFI = 36 UC_MIPS_REG_DSPEFI = 36
MIPS_REG_DSPOUTFLAG = 37 UC_MIPS_REG_DSPOUTFLAG = 37
MIPS_REG_DSPOUTFLAG16_19 = 38 UC_MIPS_REG_DSPOUTFLAG16_19 = 38
MIPS_REG_DSPOUTFLAG20 = 39 UC_MIPS_REG_DSPOUTFLAG20 = 39
MIPS_REG_DSPOUTFLAG21 = 40 UC_MIPS_REG_DSPOUTFLAG21 = 40
MIPS_REG_DSPOUTFLAG22 = 41 UC_MIPS_REG_DSPOUTFLAG22 = 41
MIPS_REG_DSPOUTFLAG23 = 42 UC_MIPS_REG_DSPOUTFLAG23 = 42
MIPS_REG_DSPPOS = 43 UC_MIPS_REG_DSPPOS = 43
MIPS_REG_DSPSCOUNT = 44 UC_MIPS_REG_DSPSCOUNT = 44
# ACC registers # ACC registers
MIPS_REG_AC0 = 45 UC_MIPS_REG_AC0 = 45
MIPS_REG_AC1 = 46 UC_MIPS_REG_AC1 = 46
MIPS_REG_AC2 = 47 UC_MIPS_REG_AC2 = 47
MIPS_REG_AC3 = 48 UC_MIPS_REG_AC3 = 48
# COP registers # COP registers
MIPS_REG_CC0 = 49 UC_MIPS_REG_CC0 = 49
MIPS_REG_CC1 = 50 UC_MIPS_REG_CC1 = 50
MIPS_REG_CC2 = 51 UC_MIPS_REG_CC2 = 51
MIPS_REG_CC3 = 52 UC_MIPS_REG_CC3 = 52
MIPS_REG_CC4 = 53 UC_MIPS_REG_CC4 = 53
MIPS_REG_CC5 = 54 UC_MIPS_REG_CC5 = 54
MIPS_REG_CC6 = 55 UC_MIPS_REG_CC6 = 55
MIPS_REG_CC7 = 56 UC_MIPS_REG_CC7 = 56
# FPU registers # FPU registers
MIPS_REG_F0 = 57 UC_MIPS_REG_F0 = 57
MIPS_REG_F1 = 58 UC_MIPS_REG_F1 = 58
MIPS_REG_F2 = 59 UC_MIPS_REG_F2 = 59
MIPS_REG_F3 = 60 UC_MIPS_REG_F3 = 60
MIPS_REG_F4 = 61 UC_MIPS_REG_F4 = 61
MIPS_REG_F5 = 62 UC_MIPS_REG_F5 = 62
MIPS_REG_F6 = 63 UC_MIPS_REG_F6 = 63
MIPS_REG_F7 = 64 UC_MIPS_REG_F7 = 64
MIPS_REG_F8 = 65 UC_MIPS_REG_F8 = 65
MIPS_REG_F9 = 66 UC_MIPS_REG_F9 = 66
MIPS_REG_F10 = 67 UC_MIPS_REG_F10 = 67
MIPS_REG_F11 = 68 UC_MIPS_REG_F11 = 68
MIPS_REG_F12 = 69 UC_MIPS_REG_F12 = 69
MIPS_REG_F13 = 70 UC_MIPS_REG_F13 = 70
MIPS_REG_F14 = 71 UC_MIPS_REG_F14 = 71
MIPS_REG_F15 = 72 UC_MIPS_REG_F15 = 72
MIPS_REG_F16 = 73 UC_MIPS_REG_F16 = 73
MIPS_REG_F17 = 74 UC_MIPS_REG_F17 = 74
MIPS_REG_F18 = 75 UC_MIPS_REG_F18 = 75
MIPS_REG_F19 = 76 UC_MIPS_REG_F19 = 76
MIPS_REG_F20 = 77 UC_MIPS_REG_F20 = 77
MIPS_REG_F21 = 78 UC_MIPS_REG_F21 = 78
MIPS_REG_F22 = 79 UC_MIPS_REG_F22 = 79
MIPS_REG_F23 = 80 UC_MIPS_REG_F23 = 80
MIPS_REG_F24 = 81 UC_MIPS_REG_F24 = 81
MIPS_REG_F25 = 82 UC_MIPS_REG_F25 = 82
MIPS_REG_F26 = 83 UC_MIPS_REG_F26 = 83
MIPS_REG_F27 = 84 UC_MIPS_REG_F27 = 84
MIPS_REG_F28 = 85 UC_MIPS_REG_F28 = 85
MIPS_REG_F29 = 86 UC_MIPS_REG_F29 = 86
MIPS_REG_F30 = 87 UC_MIPS_REG_F30 = 87
MIPS_REG_F31 = 88 UC_MIPS_REG_F31 = 88
MIPS_REG_FCC0 = 89 UC_MIPS_REG_FCC0 = 89
MIPS_REG_FCC1 = 90 UC_MIPS_REG_FCC1 = 90
MIPS_REG_FCC2 = 91 UC_MIPS_REG_FCC2 = 91
MIPS_REG_FCC3 = 92 UC_MIPS_REG_FCC3 = 92
MIPS_REG_FCC4 = 93 UC_MIPS_REG_FCC4 = 93
MIPS_REG_FCC5 = 94 UC_MIPS_REG_FCC5 = 94
MIPS_REG_FCC6 = 95 UC_MIPS_REG_FCC6 = 95
MIPS_REG_FCC7 = 96 UC_MIPS_REG_FCC7 = 96
# AFPR128 # AFPR128
MIPS_REG_W0 = 97 UC_MIPS_REG_W0 = 97
MIPS_REG_W1 = 98 UC_MIPS_REG_W1 = 98
MIPS_REG_W2 = 99 UC_MIPS_REG_W2 = 99
MIPS_REG_W3 = 100 UC_MIPS_REG_W3 = 100
MIPS_REG_W4 = 101 UC_MIPS_REG_W4 = 101
MIPS_REG_W5 = 102 UC_MIPS_REG_W5 = 102
MIPS_REG_W6 = 103 UC_MIPS_REG_W6 = 103
MIPS_REG_W7 = 104 UC_MIPS_REG_W7 = 104
MIPS_REG_W8 = 105 UC_MIPS_REG_W8 = 105
MIPS_REG_W9 = 106 UC_MIPS_REG_W9 = 106
MIPS_REG_W10 = 107 UC_MIPS_REG_W10 = 107
MIPS_REG_W11 = 108 UC_MIPS_REG_W11 = 108
MIPS_REG_W12 = 109 UC_MIPS_REG_W12 = 109
MIPS_REG_W13 = 110 UC_MIPS_REG_W13 = 110
MIPS_REG_W14 = 111 UC_MIPS_REG_W14 = 111
MIPS_REG_W15 = 112 UC_MIPS_REG_W15 = 112
MIPS_REG_W16 = 113 UC_MIPS_REG_W16 = 113
MIPS_REG_W17 = 114 UC_MIPS_REG_W17 = 114
MIPS_REG_W18 = 115 UC_MIPS_REG_W18 = 115
MIPS_REG_W19 = 116 UC_MIPS_REG_W19 = 116
MIPS_REG_W20 = 117 UC_MIPS_REG_W20 = 117
MIPS_REG_W21 = 118 UC_MIPS_REG_W21 = 118
MIPS_REG_W22 = 119 UC_MIPS_REG_W22 = 119
MIPS_REG_W23 = 120 UC_MIPS_REG_W23 = 120
MIPS_REG_W24 = 121 UC_MIPS_REG_W24 = 121
MIPS_REG_W25 = 122 UC_MIPS_REG_W25 = 122
MIPS_REG_W26 = 123 UC_MIPS_REG_W26 = 123
MIPS_REG_W27 = 124 UC_MIPS_REG_W27 = 124
MIPS_REG_W28 = 125 UC_MIPS_REG_W28 = 125
MIPS_REG_W29 = 126 UC_MIPS_REG_W29 = 126
MIPS_REG_W30 = 127 UC_MIPS_REG_W30 = 127
MIPS_REG_W31 = 128 UC_MIPS_REG_W31 = 128
MIPS_REG_HI = 129 UC_MIPS_REG_HI = 129
MIPS_REG_LO = 130 UC_MIPS_REG_LO = 130
MIPS_REG_P0 = 131 UC_MIPS_REG_P0 = 131
MIPS_REG_P1 = 132 UC_MIPS_REG_P1 = 132
MIPS_REG_P2 = 133 UC_MIPS_REG_P2 = 133
MIPS_REG_MPL0 = 134 UC_MIPS_REG_MPL0 = 134
MIPS_REG_MPL1 = 135 UC_MIPS_REG_MPL1 = 135
MIPS_REG_MPL2 = 136 UC_MIPS_REG_MPL2 = 136
MIPS_REG_ENDING = 137 UC_MIPS_REG_ENDING = 137
MIPS_REG_ZERO = MIPS_REG_0 UC_MIPS_REG_ZERO = UC_MIPS_REG_0
MIPS_REG_AT = MIPS_REG_1 UC_MIPS_REG_AT = UC_MIPS_REG_1
MIPS_REG_V0 = MIPS_REG_2 UC_MIPS_REG_V0 = UC_MIPS_REG_2
MIPS_REG_V1 = MIPS_REG_3 UC_MIPS_REG_V1 = UC_MIPS_REG_3
MIPS_REG_A0 = MIPS_REG_4 UC_MIPS_REG_A0 = UC_MIPS_REG_4
MIPS_REG_A1 = MIPS_REG_5 UC_MIPS_REG_A1 = UC_MIPS_REG_5
MIPS_REG_A2 = MIPS_REG_6 UC_MIPS_REG_A2 = UC_MIPS_REG_6
MIPS_REG_A3 = MIPS_REG_7 UC_MIPS_REG_A3 = UC_MIPS_REG_7
MIPS_REG_T0 = MIPS_REG_8 UC_MIPS_REG_T0 = UC_MIPS_REG_8
MIPS_REG_T1 = MIPS_REG_9 UC_MIPS_REG_T1 = UC_MIPS_REG_9
MIPS_REG_T2 = MIPS_REG_10 UC_MIPS_REG_T2 = UC_MIPS_REG_10
MIPS_REG_T3 = MIPS_REG_11 UC_MIPS_REG_T3 = UC_MIPS_REG_11
MIPS_REG_T4 = MIPS_REG_12 UC_MIPS_REG_T4 = UC_MIPS_REG_12
MIPS_REG_T5 = MIPS_REG_13 UC_MIPS_REG_T5 = UC_MIPS_REG_13
MIPS_REG_T6 = MIPS_REG_14 UC_MIPS_REG_T6 = UC_MIPS_REG_14
MIPS_REG_T7 = MIPS_REG_15 UC_MIPS_REG_T7 = UC_MIPS_REG_15
MIPS_REG_S0 = MIPS_REG_16 UC_MIPS_REG_S0 = UC_MIPS_REG_16
MIPS_REG_S1 = MIPS_REG_17 UC_MIPS_REG_S1 = UC_MIPS_REG_17
MIPS_REG_S2 = MIPS_REG_18 UC_MIPS_REG_S2 = UC_MIPS_REG_18
MIPS_REG_S3 = MIPS_REG_19 UC_MIPS_REG_S3 = UC_MIPS_REG_19
MIPS_REG_S4 = MIPS_REG_20 UC_MIPS_REG_S4 = UC_MIPS_REG_20
MIPS_REG_S5 = MIPS_REG_21 UC_MIPS_REG_S5 = UC_MIPS_REG_21
MIPS_REG_S6 = MIPS_REG_22 UC_MIPS_REG_S6 = UC_MIPS_REG_22
MIPS_REG_S7 = MIPS_REG_23 UC_MIPS_REG_S7 = UC_MIPS_REG_23
MIPS_REG_T8 = MIPS_REG_24 UC_MIPS_REG_T8 = UC_MIPS_REG_24
MIPS_REG_T9 = MIPS_REG_25 UC_MIPS_REG_T9 = UC_MIPS_REG_25
MIPS_REG_K0 = MIPS_REG_26 UC_MIPS_REG_K0 = UC_MIPS_REG_26
MIPS_REG_K1 = MIPS_REG_27 UC_MIPS_REG_K1 = UC_MIPS_REG_27
MIPS_REG_GP = MIPS_REG_28 UC_MIPS_REG_GP = UC_MIPS_REG_28
MIPS_REG_SP = MIPS_REG_29 UC_MIPS_REG_SP = UC_MIPS_REG_29
MIPS_REG_FP = MIPS_REG_30 UC_MIPS_REG_FP = UC_MIPS_REG_30
MIPS_REG_S8 = MIPS_REG_30 UC_MIPS_REG_S8 = UC_MIPS_REG_30
MIPS_REG_RA = MIPS_REG_31 UC_MIPS_REG_RA = UC_MIPS_REG_31
MIPS_REG_HI0 = MIPS_REG_AC0 UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0
MIPS_REG_HI1 = MIPS_REG_AC1 UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1
MIPS_REG_HI2 = MIPS_REG_AC2 UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2
MIPS_REG_HI3 = MIPS_REG_AC3 UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3
MIPS_REG_LO0 = MIPS_REG_HI0 UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0
MIPS_REG_LO1 = MIPS_REG_HI1 UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1
MIPS_REG_LO2 = MIPS_REG_HI2 UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2
MIPS_REG_LO3 = MIPS_REG_HI3 UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3

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bindings/python/unicorn/sparc_const.py
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# SPARC registers # SPARC registers
SPARC_REG_INVALID = 0 UC_SPARC_REG_INVALID = 0
SPARC_REG_F0 = 1 UC_SPARC_REG_F0 = 1
SPARC_REG_F1 = 2 UC_SPARC_REG_F1 = 2
SPARC_REG_F2 = 3 UC_SPARC_REG_F2 = 3
SPARC_REG_F3 = 4 UC_SPARC_REG_F3 = 4
SPARC_REG_F4 = 5 UC_SPARC_REG_F4 = 5
SPARC_REG_F5 = 6 UC_SPARC_REG_F5 = 6
SPARC_REG_F6 = 7 UC_SPARC_REG_F6 = 7
SPARC_REG_F7 = 8 UC_SPARC_REG_F7 = 8
SPARC_REG_F8 = 9 UC_SPARC_REG_F8 = 9
SPARC_REG_F9 = 10 UC_SPARC_REG_F9 = 10
SPARC_REG_F10 = 11 UC_SPARC_REG_F10 = 11
SPARC_REG_F11 = 12 UC_SPARC_REG_F11 = 12
SPARC_REG_F12 = 13 UC_SPARC_REG_F12 = 13
SPARC_REG_F13 = 14 UC_SPARC_REG_F13 = 14
SPARC_REG_F14 = 15 UC_SPARC_REG_F14 = 15
SPARC_REG_F15 = 16 UC_SPARC_REG_F15 = 16
SPARC_REG_F16 = 17 UC_SPARC_REG_F16 = 17
SPARC_REG_F17 = 18 UC_SPARC_REG_F17 = 18
SPARC_REG_F18 = 19 UC_SPARC_REG_F18 = 19
SPARC_REG_F19 = 20 UC_SPARC_REG_F19 = 20
SPARC_REG_F20 = 21 UC_SPARC_REG_F20 = 21
SPARC_REG_F21 = 22 UC_SPARC_REG_F21 = 22
SPARC_REG_F22 = 23 UC_SPARC_REG_F22 = 23
SPARC_REG_F23 = 24 UC_SPARC_REG_F23 = 24
SPARC_REG_F24 = 25 UC_SPARC_REG_F24 = 25
SPARC_REG_F25 = 26 UC_SPARC_REG_F25 = 26
SPARC_REG_F26 = 27 UC_SPARC_REG_F26 = 27
SPARC_REG_F27 = 28 UC_SPARC_REG_F27 = 28
SPARC_REG_F28 = 29 UC_SPARC_REG_F28 = 29
SPARC_REG_F29 = 30 UC_SPARC_REG_F29 = 30
SPARC_REG_F30 = 31 UC_SPARC_REG_F30 = 31
SPARC_REG_F31 = 32 UC_SPARC_REG_F31 = 32
SPARC_REG_F32 = 33 UC_SPARC_REG_F32 = 33
SPARC_REG_F34 = 34 UC_SPARC_REG_F34 = 34
SPARC_REG_F36 = 35 UC_SPARC_REG_F36 = 35
SPARC_REG_F38 = 36 UC_SPARC_REG_F38 = 36
SPARC_REG_F40 = 37 UC_SPARC_REG_F40 = 37
SPARC_REG_F42 = 38 UC_SPARC_REG_F42 = 38
SPARC_REG_F44 = 39 UC_SPARC_REG_F44 = 39
SPARC_REG_F46 = 40 UC_SPARC_REG_F46 = 40
SPARC_REG_F48 = 41 UC_SPARC_REG_F48 = 41
SPARC_REG_F50 = 42 UC_SPARC_REG_F50 = 42
SPARC_REG_F52 = 43 UC_SPARC_REG_F52 = 43
SPARC_REG_F54 = 44 UC_SPARC_REG_F54 = 44
SPARC_REG_F56 = 45 UC_SPARC_REG_F56 = 45
SPARC_REG_F58 = 46 UC_SPARC_REG_F58 = 46
SPARC_REG_F60 = 47 UC_SPARC_REG_F60 = 47
SPARC_REG_F62 = 48 UC_SPARC_REG_F62 = 48
SPARC_REG_FCC0 = 49 UC_SPARC_REG_FCC0 = 49
SPARC_REG_FCC1 = 50 UC_SPARC_REG_FCC1 = 50
SPARC_REG_FCC2 = 51 UC_SPARC_REG_FCC2 = 51
SPARC_REG_FCC3 = 52 UC_SPARC_REG_FCC3 = 52
SPARC_REG_FP = 53 UC_SPARC_REG_FP = 53
SPARC_REG_G0 = 54 UC_SPARC_REG_G0 = 54
SPARC_REG_G1 = 55 UC_SPARC_REG_G1 = 55
SPARC_REG_G2 = 56 UC_SPARC_REG_G2 = 56
SPARC_REG_G3 = 57 UC_SPARC_REG_G3 = 57
SPARC_REG_G4 = 58 UC_SPARC_REG_G4 = 58
SPARC_REG_G5 = 59 UC_SPARC_REG_G5 = 59
SPARC_REG_G6 = 60 UC_SPARC_REG_G6 = 60
SPARC_REG_G7 = 61 UC_SPARC_REG_G7 = 61
SPARC_REG_I0 = 62 UC_SPARC_REG_I0 = 62
SPARC_REG_I1 = 63 UC_SPARC_REG_I1 = 63
SPARC_REG_I2 = 64 UC_SPARC_REG_I2 = 64
SPARC_REG_I3 = 65 UC_SPARC_REG_I3 = 65
SPARC_REG_I4 = 66 UC_SPARC_REG_I4 = 66
SPARC_REG_I5 = 67 UC_SPARC_REG_I5 = 67
SPARC_REG_I7 = 68 UC_SPARC_REG_I7 = 68
SPARC_REG_ICC = 69 UC_SPARC_REG_ICC = 69
SPARC_REG_L0 = 70 UC_SPARC_REG_L0 = 70
SPARC_REG_L1 = 71 UC_SPARC_REG_L1 = 71
SPARC_REG_L2 = 72 UC_SPARC_REG_L2 = 72
SPARC_REG_L3 = 73 UC_SPARC_REG_L3 = 73
SPARC_REG_L4 = 74 UC_SPARC_REG_L4 = 74
SPARC_REG_L5 = 75 UC_SPARC_REG_L5 = 75
SPARC_REG_L6 = 76 UC_SPARC_REG_L6 = 76
SPARC_REG_L7 = 77 UC_SPARC_REG_L7 = 77
SPARC_REG_O0 = 78 UC_SPARC_REG_O0 = 78
SPARC_REG_O1 = 79 UC_SPARC_REG_O1 = 79
SPARC_REG_O2 = 80 UC_SPARC_REG_O2 = 80
SPARC_REG_O3 = 81 UC_SPARC_REG_O3 = 81
SPARC_REG_O4 = 82 UC_SPARC_REG_O4 = 82
SPARC_REG_O5 = 83 UC_SPARC_REG_O5 = 83
SPARC_REG_O7 = 84 UC_SPARC_REG_O7 = 84
SPARC_REG_SP = 85 UC_SPARC_REG_SP = 85
SPARC_REG_Y = 86 UC_SPARC_REG_Y = 86
SPARC_REG_XCC = 87 UC_SPARC_REG_XCC = 87
SPARC_REG_PC = 88 UC_SPARC_REG_PC = 88
SPARC_REG_ENDING = 89 UC_SPARC_REG_ENDING = 89
SPARC_REG_O6 = SPARC_REG_SP UC_SPARC_REG_O6 = UC_SPARC_REG_SP
SPARC_REG_I6 = SPARC_REG_FP UC_SPARC_REG_I6 = UC_SPARC_REG_FP