From e38b1c8af389443a98258af4f5343451e671ef88 Mon Sep 17 00:00:00 2001 From: lazymio Date: Sat, 12 Feb 2022 19:37:32 +0100 Subject: [PATCH] Fix the undefined shift --- qemu/target/arm/helper.c | 2 +- qemu/target/mips/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index d9e77e34..31682b83 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -619,7 +619,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |= (1 << 31) | (1 << 30) | (0xf << 20); + mask |= (1UL << 31) | (1 << 30) | (0xf << 20); if (!arm_feature(env, ARM_FEATURE_NEON)) { /* ASEDIS [31] bit is RAO/WI */ diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index cbff2e88..f828dbcc 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -37,7 +37,7 @@ #define MIPS_DEBUG_DISAS 0 /* MIPS major opcodes */ -#define MASK_OP_MAJOR(op) (op & (0x3FL << 26)) +#define MASK_OP_MAJOR(op) (op & (0x3FUL << 26)) enum { /* indirect opcode tables */