From f05984961bc5d476cfd2ac6c4a763c04a73a3044 Mon Sep 17 00:00:00 2001 From: Chris Eagle Date: Tue, 7 Feb 2017 17:37:41 -0800 Subject: [PATCH] Fix 16-bit address computations (#747) * Remove glib from samples makefile * changes to 16 bit segment registers needs to update segment base as well as segment selector * change how x86 segment registers are set in 16-bit mode --- qemu/target-i386/unicorn.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/qemu/target-i386/unicorn.c b/qemu/target-i386/unicorn.c index 5005c2f9..1aaae579 100644 --- a/qemu/target-i386/unicorn.c +++ b/qemu/target-i386/unicorn.c @@ -11,6 +11,10 @@ #include /* needed for uc_x86_mmr */ #include "uc_priv.h" +static void load_seg_16_helper(CPUX86State *env, int seg, uint32_t selector) +{ + cpu_x86_load_seg_cache(env, seg, selector, (selector << 4), 0xffff, 0); +} const int X86_REGS_STORAGE_SIZE = offsetof(CPUX86State, tlb_table); @@ -694,19 +698,19 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; case UC_X86_REG_ES: - X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(uint16_t *)value; + load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_ES, *(uint16_t *)value); continue; case UC_X86_REG_SS: - X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(uint16_t *)value; + load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_SS, *(uint16_t *)value); continue; case UC_X86_REG_DS: - X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(uint16_t *)value; + load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_DS, *(uint16_t *)value); continue; case UC_X86_REG_FS: - X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(uint16_t *)value; + load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_FS, *(uint16_t *)value); continue; case UC_X86_REG_GS: - X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(uint16_t *)value; + load_seg_16_helper(&X86_CPU(uc, mycpu)->env, R_GS, *(uint16_t *)value); continue; } // fall-thru