From 5a97bf7f8fe2e07cb488bd56df72ef680d48de93 Mon Sep 17 00:00:00 2001 From: Bet4 <0xbet4@gmail.com> Date: Fri, 15 Oct 2021 09:16:33 +0800 Subject: [PATCH] Update Rust constants to Unicorn2 --- bindings/rust/src/arm.rs | 30 +- bindings/rust/src/arm64.rs | 1 + bindings/rust/src/lib.rs | 3 +- bindings/rust/src/m68k.rs | 1 + bindings/rust/src/mips.rs | 10 +- bindings/rust/src/riscv.rs | 213 +++++++++++++ bindings/rust/src/sparc.rs | 11 + bindings/rust/src/unicorn_const.rs | 12 +- bindings/rust/src/x86.rs | 486 ++++++++++++++--------------- bindings/rust/tests/unicorn.rs | 24 +- 10 files changed, 505 insertions(+), 286 deletions(-) create mode 100644 bindings/rust/src/riscv.rs diff --git a/bindings/rust/src/arm.rs b/bindings/rust/src/arm.rs index 69178664..6d72cefe 100644 --- a/bindings/rust/src/arm.rs +++ b/bindings/rust/src/arm.rs @@ -123,8 +123,31 @@ pub enum RegisterARM { MSP = 115, PSP = 116, CONTROL = 117, - XPSR = 118, - ENDING = 119, + IAPSR = 118, + EAPSR = 119, + XPSR = 120, + EPSR = 121, + IEPSR = 122, + PRIMASK = 123, + BASEPRI = 124, + BASEPRI_MAX = 125, + FAULTMASK = 126, + APSR_NZCVQ = 127, + APSR_G = 128, + APSR_NZCVQG = 129, + IAPSR_NZCVQ = 130, + IAPSR_G = 131, + IAPSR_NZCVQG = 132, + EAPSR_NZCVQ = 133, + EAPSR_G = 134, + EAPSR_NZCVQG = 135, + XPSR_NZCVQ = 136, + XPSR_G = 137, + XPSR_NZCVQG = 138, + ENDING = 139, +} + +impl RegisterARM { // alias registers // (assoc) R13 = 12, // (assoc) R14 = 10, @@ -133,9 +156,6 @@ pub enum RegisterARM { // (assoc) SL = 76, // (assoc) FP = 77, // (assoc) IP = 78, -} - -impl RegisterARM { pub const R13: RegisterARM = RegisterARM::SP; pub const R14: RegisterARM = RegisterARM::LR; pub const R15: RegisterARM = RegisterARM::PC; diff --git a/bindings/rust/src/arm64.rs b/bindings/rust/src/arm64.rs index 523de02a..299b1bbf 100644 --- a/bindings/rust/src/arm64.rs +++ b/bindings/rust/src/arm64.rs @@ -1,4 +1,5 @@ #![allow(non_camel_case_types)] +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT // ARM64 registers #[repr(C)] diff --git a/bindings/rust/src/lib.rs b/bindings/rust/src/lib.rs index 8fb5ed3c..3ee73b6a 100644 --- a/bindings/rust/src/lib.rs +++ b/bindings/rust/src/lib.rs @@ -35,9 +35,10 @@ mod arm64; mod m68k; mod mips; mod ppc; +mod riscv; mod sparc; mod x86; -pub use crate::{arm::*, arm64::*, m68k::*, mips::*, ppc::*, sparc::*, x86::*}; +pub use crate::{arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, sparc::*, x86::*}; use ffi::uc_handle; use std::collections::HashMap; diff --git a/bindings/rust/src/m68k.rs b/bindings/rust/src/m68k.rs index 6c04e851..54c62920 100644 --- a/bindings/rust/src/m68k.rs +++ b/bindings/rust/src/m68k.rs @@ -21,4 +21,5 @@ pub enum RegisterM68K { D7, SR, PC, + ENDING, } diff --git a/bindings/rust/src/mips.rs b/bindings/rust/src/mips.rs index 84cec434..5f462af0 100644 --- a/bindings/rust/src/mips.rs +++ b/bindings/rust/src/mips.rs @@ -1,4 +1,5 @@ #![allow(non_camel_case_types)] +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT // MIPS registers #[repr(C)] @@ -155,7 +156,11 @@ pub enum RegisterMIPS { MPL2 = 136, CP0_CONFIG3 = 137, CP0_USERLOCAL = 138, - ENDING = 139, + CP0_STATUS = 139, + ENDING = 140, +} + +impl RegisterMIPS { // alias registers // (assoc) ZERO = 2, // (assoc) AT = 3, @@ -198,9 +203,6 @@ pub enum RegisterMIPS { // (assoc) LO1 = 46, // (assoc) LO2 = 47, // (assoc) LO3 = 48, -} - -impl RegisterMIPS { pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0; pub const AT: RegisterMIPS = RegisterMIPS::GPR1; pub const V0: RegisterMIPS = RegisterMIPS::GPR2; diff --git a/bindings/rust/src/riscv.rs b/bindings/rust/src/riscv.rs new file mode 100644 index 00000000..ca91c350 --- /dev/null +++ b/bindings/rust/src/riscv.rs @@ -0,0 +1,213 @@ +#![allow(non_camel_case_types)] +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + +// RISCV registers +#[repr(C)] +#[derive(PartialEq, Debug, Clone, Copy)] +pub enum RegisterRISCV { + INVALID = 0, + + // General purpose registers + X0 = 1, + X1 = 2, + X2 = 3, + X3 = 4, + X4 = 5, + X5 = 6, + X6 = 7, + X7 = 8, + X8 = 9, + X9 = 10, + X10 = 11, + X11 = 12, + X12 = 13, + X13 = 14, + X14 = 15, + X15 = 16, + X16 = 17, + X17 = 18, + X18 = 19, + X19 = 20, + X20 = 21, + X21 = 22, + X22 = 23, + X23 = 24, + X24 = 25, + X25 = 26, + X26 = 27, + X27 = 28, + X28 = 29, + X29 = 30, + X30 = 31, + X31 = 32, + + // Floating-point registers + F0 = 33, + F1 = 34, + F2 = 35, + F3 = 36, + F4 = 37, + F5 = 38, + F6 = 39, + F7 = 40, + F8 = 41, + F9 = 42, + F10 = 43, + F11 = 44, + F12 = 45, + F13 = 46, + F14 = 47, + F15 = 48, + F16 = 49, + F17 = 50, + F18 = 51, + F19 = 52, + F20 = 53, + F21 = 54, + F22 = 55, + F23 = 56, + F24 = 57, + F25 = 58, + F26 = 59, + F27 = 60, + F28 = 61, + F29 = 62, + F30 = 63, + F31 = 64, + PC = 65, + ENDING = 66, +} + +impl RegisterRISCV { + // Alias registers + // (assoc) ZERO = 1, + // (assoc) RA = 2, + // (assoc) SP = 3, + // (assoc) GP = 4, + // (assoc) TP = 5, + // (assoc) T0 = 6, + // (assoc) T1 = 7, + // (assoc) T2 = 8, + // (assoc) S0 = 9, + // (assoc) FP = 9, + // (assoc) S1 = 10, + // (assoc) A0 = 11, + // (assoc) A1 = 12, + // (assoc) A2 = 13, + // (assoc) A3 = 14, + // (assoc) A4 = 15, + // (assoc) A5 = 16, + // (assoc) A6 = 17, + // (assoc) A7 = 18, + // (assoc) S2 = 19, + // (assoc) S3 = 20, + // (assoc) S4 = 21, + // (assoc) S5 = 22, + // (assoc) S6 = 23, + // (assoc) S7 = 24, + // (assoc) S8 = 25, + // (assoc) S9 = 26, + // (assoc) S10 = 27, + // (assoc) S11 = 28, + // (assoc) T3 = 29, + // (assoc) T4 = 30, + // (assoc) T5 = 31, + // (assoc) T6 = 32, + // (assoc) FT0 = 33, + // (assoc) FT1 = 34, + // (assoc) FT2 = 35, + // (assoc) FT3 = 36, + // (assoc) FT4 = 37, + // (assoc) FT5 = 38, + // (assoc) FT6 = 39, + // (assoc) FT7 = 40, + // (assoc) FS0 = 41, + // (assoc) FS1 = 42, + // (assoc) FA0 = 43, + // (assoc) FA1 = 44, + // (assoc) FA2 = 45, + // (assoc) FA3 = 46, + // (assoc) FA4 = 47, + // (assoc) FA5 = 48, + // (assoc) FA6 = 49, + // (assoc) FA7 = 50, + // (assoc) FS2 = 51, + // (assoc) FS3 = 52, + // (assoc) FS4 = 53, + // (assoc) FS5 = 54, + // (assoc) FS6 = 55, + // (assoc) FS7 = 56, + // (assoc) FS8 = 57, + // (assoc) FS9 = 58, + // (assoc) FS10 = 59, + // (assoc) FS11 = 60, + // (assoc) FT8 = 61, + // (assoc) FT9 = 62, + // (assoc) FT10 = 63, + // (assoc) FT11 = 64, + pub const ZERO: RegisterRISCV = RegisterRISCV::X0; + pub const RA: RegisterRISCV = RegisterRISCV::X1; + pub const SP: RegisterRISCV = RegisterRISCV::X2; + pub const GP: RegisterRISCV = RegisterRISCV::X3; + pub const TP: RegisterRISCV = RegisterRISCV::X4; + pub const T0: RegisterRISCV = RegisterRISCV::X5; + pub const T1: RegisterRISCV = RegisterRISCV::X6; + pub const T2: RegisterRISCV = RegisterRISCV::X7; + pub const S0: RegisterRISCV = RegisterRISCV::X8; + pub const FP: RegisterRISCV = RegisterRISCV::X8; + pub const S1: RegisterRISCV = RegisterRISCV::X9; + pub const A0: RegisterRISCV = RegisterRISCV::X10; + pub const A1: RegisterRISCV = RegisterRISCV::X11; + pub const A2: RegisterRISCV = RegisterRISCV::X12; + pub const A3: RegisterRISCV = RegisterRISCV::X13; + pub const A4: RegisterRISCV = RegisterRISCV::X14; + pub const A5: RegisterRISCV = RegisterRISCV::X15; + pub const A6: RegisterRISCV = RegisterRISCV::X16; + pub const A7: RegisterRISCV = RegisterRISCV::X17; + pub const S2: RegisterRISCV = RegisterRISCV::X18; + pub const S3: RegisterRISCV = RegisterRISCV::X19; + pub const S4: RegisterRISCV = RegisterRISCV::X20; + pub const S5: RegisterRISCV = RegisterRISCV::X21; + pub const S6: RegisterRISCV = RegisterRISCV::X22; + pub const S7: RegisterRISCV = RegisterRISCV::X23; + pub const S8: RegisterRISCV = RegisterRISCV::X24; + pub const S9: RegisterRISCV = RegisterRISCV::X25; + pub const S10: RegisterRISCV = RegisterRISCV::X26; + pub const S11: RegisterRISCV = RegisterRISCV::X27; + pub const T3: RegisterRISCV = RegisterRISCV::X28; + pub const T4: RegisterRISCV = RegisterRISCV::X29; + pub const T5: RegisterRISCV = RegisterRISCV::X30; + pub const T6: RegisterRISCV = RegisterRISCV::X31; + pub const FT0: RegisterRISCV = RegisterRISCV::F0; + pub const FT1: RegisterRISCV = RegisterRISCV::F1; + pub const FT2: RegisterRISCV = RegisterRISCV::F2; + pub const FT3: RegisterRISCV = RegisterRISCV::F3; + pub const FT4: RegisterRISCV = RegisterRISCV::F4; + pub const FT5: RegisterRISCV = RegisterRISCV::F5; + pub const FT6: RegisterRISCV = RegisterRISCV::F6; + pub const FT7: RegisterRISCV = RegisterRISCV::F7; + pub const FS0: RegisterRISCV = RegisterRISCV::F8; + pub const FS1: RegisterRISCV = RegisterRISCV::F9; + pub const FA0: RegisterRISCV = RegisterRISCV::F10; + pub const FA1: RegisterRISCV = RegisterRISCV::F11; + pub const FA2: RegisterRISCV = RegisterRISCV::F12; + pub const FA3: RegisterRISCV = RegisterRISCV::F13; + pub const FA4: RegisterRISCV = RegisterRISCV::F14; + pub const FA5: RegisterRISCV = RegisterRISCV::F15; + pub const FA6: RegisterRISCV = RegisterRISCV::F16; + pub const FA7: RegisterRISCV = RegisterRISCV::F17; + pub const FS2: RegisterRISCV = RegisterRISCV::F18; + pub const FS3: RegisterRISCV = RegisterRISCV::F19; + pub const FS4: RegisterRISCV = RegisterRISCV::F20; + pub const FS5: RegisterRISCV = RegisterRISCV::F21; + pub const FS6: RegisterRISCV = RegisterRISCV::F22; + pub const FS7: RegisterRISCV = RegisterRISCV::F23; + pub const FS8: RegisterRISCV = RegisterRISCV::F24; + pub const FS9: RegisterRISCV = RegisterRISCV::F25; + pub const FS10: RegisterRISCV = RegisterRISCV::F26; + pub const FS11: RegisterRISCV = RegisterRISCV::F27; + pub const FT8: RegisterRISCV = RegisterRISCV::F28; + pub const FT9: RegisterRISCV = RegisterRISCV::F29; + pub const FT10: RegisterRISCV = RegisterRISCV::F30; + pub const FT11: RegisterRISCV = RegisterRISCV::F31; +} diff --git a/bindings/rust/src/sparc.rs b/bindings/rust/src/sparc.rs index 21e09db4..6c6892e6 100644 --- a/bindings/rust/src/sparc.rs +++ b/bindings/rust/src/sparc.rs @@ -1,3 +1,5 @@ +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + // SPARC registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] @@ -91,4 +93,13 @@ pub enum RegisterSPARC { Y = 86, XCC = 87, PC = 88, + ENDING = 89, +} + +impl RegisterSPARC { + // alias registers + // (assoc) O6 = 84, + // (assoc) I6 = 67, + pub const O6: RegisterSPARC = RegisterSPARC::SP; + pub const I6: RegisterSPARC = RegisterSPARC::FP; } diff --git a/bindings/rust/src/unicorn_const.rs b/bindings/rust/src/unicorn_const.rs index 56b3f275..9cb14da7 100644 --- a/bindings/rust/src/unicorn_const.rs +++ b/bindings/rust/src/unicorn_const.rs @@ -1,11 +1,11 @@ #![allow(non_camel_case_types)] use bitflags::bitflags; -pub const API_MAJOR: u64 = 1; +pub const API_MAJOR: u64 = 2; pub const API_MINOR: u64 = 0; -pub const VERSION_MAJOR: u64 = 1; +pub const VERSION_MAJOR: u64 = 2; pub const VERSION_MINOR: u64 = 0; -pub const VERSION_EXTRA: u64 = 2; +pub const VERSION_EXTRA: u64 = 0; pub const SECOND_SCALE: u64 = 1_000_000; pub const MILISECOND_SCALE: u64 = 1_000; @@ -93,6 +93,7 @@ pub enum Query { MODE = 1, PAGE_SIZE = 2, ARCH = 3, + TIMEOUT = 4, } bitflags! { @@ -124,7 +125,8 @@ pub enum Arch { PPC = 5, SPARC = 6, M68K = 7, - MAX = 8, + RISCV = 8, + MAX = 9, } bitflags! { @@ -154,5 +156,7 @@ bitflags! { const SPARC32 = Self::MIPS32.bits; const SPARC64 = Self::MIPS64.bits; const V9 = Self::THUMB.bits; + const RISCV32 = Self::MIPS32.bits; + const RISCV64 = Self::MIPS64.bits; } } diff --git a/bindings/rust/src/x86.rs b/bindings/rust/src/x86.rs index 03c92176..7ed65230 100644 --- a/bindings/rust/src/x86.rs +++ b/bindings/rust/src/x86.rs @@ -1,257 +1,245 @@ +#![allow(non_camel_case_types)] +// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT + // X86 registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] pub enum RegisterX86 { INVALID = 0, - AH, - AL, - AX, - BH, - BL, - BP, - BPL, - BX, - CH, - CL, - CS, - CX, - DH, - DI, - DIL, - DL, - DS, - DX, - EAX, - EBP, - EBX, - ECX, - EDI, - EDX, - EFLAGS, - EIP, - EIZ, - ES, - ESI, - ESP, - FPSW, - FS, - GS, - IP, - RAX, - RBP, - RBX, - RCX, - RDI, - RDX, - RIP, - RIZ, - RSI, - RSP, - SI, - SIL, - SP, - SPL, - SS, - CR0, - CR1, - CR2, - CR3, - CR4, - CR5, - CR6, - CR7, - CR8, - CR9, - CR10, - CR11, - CR12, - CR13, - CR14, - CR15, - DR0, - DR1, - DR2, - DR3, - DR4, - DR5, - DR6, - DR7, - DR8, - DR9, - DR10, - DR11, - DR12, - DR13, - DR14, - DR15, - FP0, - FP1, - FP2, - FP3, - FP4, - FP5, - FP6, - FP7, - K0, - K1, - K2, - K3, - K4, - K5, - K6, - K7, - MM0, - MM1, - MM2, - MM3, - MM4, - MM5, - MM6, - MM7, - R8, - R9, - R10, - R11, - R12, - R13, - R14, - R15, - ST0, - ST1, - ST2, - ST3, - ST4, - ST5, - ST6, - ST7, - XMM0, - XMM1, - XMM2, - XMM3, - XMM4, - XMM5, - XMM6, - XMM7, - XMM8, - XMM9, - XMM10, - XMM11, - XMM12, - XMM13, - XMM14, - XMM15, - XMM16, - XMM17, - XMM18, - XMM19, - XMM20, - XMM21, - XMM22, - XMM23, - XMM24, - XMM25, - XMM26, - XMM27, - XMM28, - XMM29, - XMM30, - XMM31, - YMM0, - YMM1, - YMM2, - YMM3, - YMM4, - YMM5, - YMM6, - YMM7, - YMM8, - YMM9, - YMM10, - YMM11, - YMM12, - YMM13, - YMM14, - YMM15, - YMM16, - YMM17, - YMM18, - YMM19, - YMM20, - YMM21, - YMM22, - YMM23, - YMM24, - YMM25, - YMM26, - YMM27, - YMM28, - YMM29, - YMM30, - YMM31, - ZMM0, - ZMM1, - ZMM2, - ZMM3, - ZMM4, - ZMM5, - ZMM6, - ZMM7, - ZMM8, - ZMM9, - ZMM10, - ZMM11, - ZMM12, - ZMM13, - ZMM14, - ZMM15, - ZMM16, - ZMM17, - ZMM18, - ZMM19, - ZMM20, - ZMM21, - ZMM22, - ZMM23, - ZMM24, - ZMM25, - ZMM26, - ZMM27, - ZMM28, - ZMM29, - ZMM30, - ZMM31, - R8B, - R9B, - R10B, - R11B, - R12B, - R13B, - R14B, - R15B, - R8D, - R9D, - R10D, - R11D, - R12D, - R13D, - R14D, - R15D, - R8W, - R9W, - R10W, - R11W, - R12W, - R13W, - R14W, - R15W, - IDTR, - GDTR, - LDTR, - TR, - FPCW, - FPTAG, - MSR, - MXCSR, + AH = 1, + AL = 2, + AX = 3, + BH = 4, + BL = 5, + BP = 6, + BPL = 7, + BX = 8, + CH = 9, + CL = 10, + CS = 11, + CX = 12, + DH = 13, + DI = 14, + DIL = 15, + DL = 16, + DS = 17, + DX = 18, + EAX = 19, + EBP = 20, + EBX = 21, + ECX = 22, + EDI = 23, + EDX = 24, + EFLAGS = 25, + EIP = 26, + ES = 27, + ESI = 28, + ESP = 29, + FPSW = 30, + FS = 31, + GS = 32, + IP = 33, + RAX = 34, + RBP = 35, + RBX = 36, + RCX = 37, + RDI = 38, + RDX = 39, + RIP = 40, + RSI = 41, + RSP = 42, + SI = 43, + SIL = 44, + SP = 45, + SPL = 46, + SS = 47, + CR0 = 48, + CR1 = 49, + CR2 = 50, + CR3 = 51, + CR4 = 52, + CR8 = 53, + DR0 = 54, + DR1 = 55, + DR2 = 56, + DR3 = 57, + DR4 = 58, + DR5 = 59, + DR6 = 60, + DR7 = 61, + FP0 = 62, + FP1 = 63, + FP2 = 64, + FP3 = 65, + FP4 = 66, + FP5 = 67, + FP6 = 68, + FP7 = 69, + K0 = 70, + K1 = 71, + K2 = 72, + K3 = 73, + K4 = 74, + K5 = 75, + K6 = 76, + K7 = 77, + MM0 = 78, + MM1 = 79, + MM2 = 80, + MM3 = 81, + MM4 = 82, + MM5 = 83, + MM6 = 84, + MM7 = 85, + R8 = 86, + R9 = 87, + R10 = 88, + R11 = 89, + R12 = 90, + R13 = 91, + R14 = 92, + R15 = 93, + ST0 = 94, + ST1 = 95, + ST2 = 96, + ST3 = 97, + ST4 = 98, + ST5 = 99, + ST6 = 100, + ST7 = 101, + XMM0 = 102, + XMM1 = 103, + XMM2 = 104, + XMM3 = 105, + XMM4 = 106, + XMM5 = 107, + XMM6 = 108, + XMM7 = 109, + XMM8 = 110, + XMM9 = 111, + XMM10 = 112, + XMM11 = 113, + XMM12 = 114, + XMM13 = 115, + XMM14 = 116, + XMM15 = 117, + XMM16 = 118, + XMM17 = 119, + XMM18 = 120, + XMM19 = 121, + XMM20 = 122, + XMM21 = 123, + XMM22 = 124, + XMM23 = 125, + XMM24 = 126, + XMM25 = 127, + XMM26 = 128, + XMM27 = 129, + XMM28 = 130, + XMM29 = 131, + XMM30 = 132, + XMM31 = 133, + YMM0 = 134, + YMM1 = 135, + YMM2 = 136, + YMM3 = 137, + YMM4 = 138, + YMM5 = 139, + YMM6 = 140, + YMM7 = 141, + YMM8 = 142, + YMM9 = 143, + YMM10 = 144, + YMM11 = 145, + YMM12 = 146, + YMM13 = 147, + YMM14 = 148, + YMM15 = 149, + YMM16 = 150, + YMM17 = 151, + YMM18 = 152, + YMM19 = 153, + YMM20 = 154, + YMM21 = 155, + YMM22 = 156, + YMM23 = 157, + YMM24 = 158, + YMM25 = 159, + YMM26 = 160, + YMM27 = 161, + YMM28 = 162, + YMM29 = 163, + YMM30 = 164, + YMM31 = 165, + ZMM0 = 166, + ZMM1 = 167, + ZMM2 = 168, + ZMM3 = 169, + ZMM4 = 170, + ZMM5 = 171, + ZMM6 = 172, + ZMM7 = 173, + ZMM8 = 174, + ZMM9 = 175, + ZMM10 = 176, + ZMM11 = 177, + ZMM12 = 178, + ZMM13 = 179, + ZMM14 = 180, + ZMM15 = 181, + ZMM16 = 182, + ZMM17 = 183, + ZMM18 = 184, + ZMM19 = 185, + ZMM20 = 186, + ZMM21 = 187, + ZMM22 = 188, + ZMM23 = 189, + ZMM24 = 190, + ZMM25 = 191, + ZMM26 = 192, + ZMM27 = 193, + ZMM28 = 194, + ZMM29 = 195, + ZMM30 = 196, + ZMM31 = 197, + R8B = 198, + R9B = 199, + R10B = 200, + R11B = 201, + R12B = 202, + R13B = 203, + R14B = 204, + R15B = 205, + R8D = 206, + R9D = 207, + R10D = 208, + R11D = 209, + R12D = 210, + R13D = 211, + R14D = 212, + R15D = 213, + R8W = 214, + R9W = 215, + R10W = 216, + R11W = 217, + R12W = 218, + R13W = 219, + R14W = 220, + R15W = 221, + IDTR = 222, + GDTR = 223, + LDTR = 224, + TR = 225, + FPCW = 226, + FPTAG = 227, + MSR = 228, + MXCSR = 229, + FS_BASE = 230, + GS_BASE = 231, + FLAGS = 232, + RFLAGS = 233, + ENDING = 234, } #[repr(C)] diff --git a/bindings/rust/tests/unicorn.rs b/bindings/rust/tests/unicorn.rs index 90021835..a46cfa89 100644 --- a/bindings/rust/tests/unicorn.rs +++ b/bindings/rust/tests/unicorn.rs @@ -1,11 +1,9 @@ -#![deny(rust_2018_idioms)] - use std::cell::RefCell; use std::rc::Rc; use unicorn::unicorn_const::{uc_error, Arch, HookType, MemType, Mode, Permission, SECOND_SCALE}; use unicorn::{InsnSysX86, RegisterARM, RegisterMIPS, RegisterPPC, RegisterX86}; -pub static X86_REGISTERS: [RegisterX86; 145] = [ +pub static X86_REGISTERS: [RegisterX86; 125] = [ RegisterX86::AH, RegisterX86::AL, RegisterX86::AX, @@ -32,7 +30,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [ RegisterX86::EDX, RegisterX86::EFLAGS, RegisterX86::EIP, - RegisterX86::EIZ, RegisterX86::ES, RegisterX86::ESI, RegisterX86::ESP, @@ -47,7 +44,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [ RegisterX86::RDI, RegisterX86::RDX, RegisterX86::RIP, - RegisterX86::RIZ, RegisterX86::RSI, RegisterX86::RSP, RegisterX86::SI, @@ -60,17 +56,7 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [ RegisterX86::CR2, RegisterX86::CR3, RegisterX86::CR4, - RegisterX86::CR5, - RegisterX86::CR6, - RegisterX86::CR7, RegisterX86::CR8, - RegisterX86::CR9, - RegisterX86::CR10, - RegisterX86::CR11, - RegisterX86::CR12, - RegisterX86::CR13, - RegisterX86::CR14, - RegisterX86::CR15, RegisterX86::DR0, RegisterX86::DR1, RegisterX86::DR2, @@ -79,14 +65,6 @@ pub static X86_REGISTERS: [RegisterX86; 145] = [ RegisterX86::DR5, RegisterX86::DR6, RegisterX86::DR7, - RegisterX86::DR8, - RegisterX86::DR9, - RegisterX86::DR10, - RegisterX86::DR11, - RegisterX86::DR12, - RegisterX86::DR13, - RegisterX86::DR14, - RegisterX86::DR15, RegisterX86::FP0, RegisterX86::FP1, RegisterX86::FP2,