* Handle the cpu context save in a more pythonic way, so the context can be serialized and reuse in an other process using the same emulator architecture and modes
* Fix type error ; mistakes a size_t uint64_t ; breaks in 32bit...
* update python binding samples, shellcode.py with 64bit syscall
* fix with quynh comments
* fix with more q comments
* reformatted
* reformatted and moved file
* reformatted and moved file
* delete file
* delete dead code
* deleted more dead code
* deleted more dead code / fix bugs
* fix 64bit eip intno eax
* rearrage rip
* Inconsistent print
* Python: Disable distribution of static library on linux and macos; add environment variable LIBUNICORN_PATH to let user specify location of native library; prevent build of native library if this option is enabled; closes#869
* Python: Update README.TXT to describe how to manage the building and usage of the native library
Sometimes, the finalizer for an `UcRef` runs so late that the members of the
module have already been set to `None`. We need to make sure that we don't
depend on anything in the module, or we risk getting a Exception when we try
to access the `release_handle` method of `None` (`Uc`).
* arm64eb: arm64 big endian also using little endian instructions.
* arm64: using another example that depends on endians.
example:
1. store a word: 0x12345678
2. load a byte:
* little endian : 0x78
* big endian : 0x12
* uc_reg_read & uc_reg_write now support ARM64 Neon registers
* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...
So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
Byte Value Size
0 MSR ID 4
4 MSR val 8
