3a3bc0c22d
Timeout error ( #1173 )
...
* Implement timeout state and new error for such case
* Adjust test_i386_loop sample
* Adjust test_i386_loop test
2019-12-29 00:16:54 +08:00
ba74552199
Expose different 32-bit ARM CPU models to users via UC_MODE flags ( #1165 )
2019-10-26 05:01:00 +08:00
07f94ad1fc
Added an invalid instruction hook ( #1132 )
...
* first draft for an invalid instruction hook
* Fixed documentation on return value of invalid insn hook
2019-09-23 01:53:06 +08:00
fe466d003a
callback to count number of instructions in uc_emu_start() should be executed first. fix #727
2017-06-16 13:22:38 +08:00
4b9efdc986
Adding INSN hook checks for x86 ( #833 )
...
* adding INSN hook checking for x86
* tabs to spaces
* need to return bool not uc_err
* fixed conditional after switching to bool
2017-05-14 00:16:17 +07:00
e917c9de10
Merge branch 'master' into msvc2
2017-04-21 01:17:00 +08:00
3b6779479e
cleanup uc_priv.h
2017-03-30 15:59:13 +08:00
094ca80092
fix conflicts
2017-03-30 12:23:24 +08:00
d8fe34a2e8
armeb: Add support for ARM big endian.
2017-03-13 22:32:44 +08:00
c01dcf0a14
fix merge conflicts
2017-03-10 21:04:33 +08:00
02e6c14e12
x86: add MSR API via reg API ( #755 )
...
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...
So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
Byte Value Size
0 MSR ID 4
4 MSR val 8
2017-02-24 21:37:19 +08:00
fac6a66860
platform.h move #3
2017-01-21 00:13:21 +11:00
b0ae2138fb
Merge remote-tracking branch 'unicorn-engine/master' into msvc_native
2017-01-20 22:37:51 +11:00
c6de7930c9
remove mutex code
2017-01-20 15:44:03 +08:00
42771848d6
no more spinlock
2017-01-20 14:57:33 +08:00
1aeaf5c40d
This code should now build the x86_x64-softmmu part 2.
2017-01-19 22:50:28 +11:00
47150b6df3
reg_read and reg_write now work with registers W0 through W30 in Aarch64 ( #716 )
...
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton
* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write
* Fixed WRITE_DWORD macro
reg_write would zero out the high order bits when writing to 32 bit registers
e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
2017-01-15 20:13:35 +08:00
52cb0ba78e
cleanup more synchronization code
2017-01-09 14:05:39 +08:00
428cb83060
Support for MCLASS ARM cpu (Cortex-M3) ( #700 )
...
Support for Cortex-M ARM CPU already exists in Qemu. This patch just
exposes a "cortex-m3" CPU.
"uc_open(UC_ARCH_ARM, UC_MODE_THUMB | UC_MODE_MCLASS, &uc);"
Instantiates a CPU with this feature on.
Signed-off-by: Lucian Cojocar <lucian@cojocar.com >
2016-12-27 22:49:06 +08:00
4083b87032
add new hook type UC_HOOK_MEM_READ_AFTER, adapted from PR #399 by @farmdve. updated all bindings, except Ruby & Haskell
2016-10-22 11:19:55 +08:00
80f35d3b2b
remove safety checks, for some reason
2016-10-11 13:07:14 -07:00
ea54204952
Tweak some names in a few places, encapsulate the uc_context struct to hide it from users for some reason
2016-10-10 14:04:51 -07:00
cb615fdba7
remove uc->cpus
2016-09-23 07:38:21 -07:00
69d976375e
Merge branch 'fix/self_modifying' of https://github.com/rhelmot/unicorn into rhelmot-fix/self_modifying
2016-08-30 21:20:22 +08:00
8b030ae51a
fix for issue #523
2016-08-27 21:49:11 +08:00
97b10da133
Undo the disaster that was the patch to unicorn github issue #266 and fix it correctly. makes normal self-modifying code work.
2016-08-09 19:35:20 -07:00
3a742fb6f6
fix conflicts when merging no-thread to master
2016-04-23 10:06:57 +08:00
cc6cbc5cf7
Merge branch 'memleak' into m2
2016-04-18 12:48:13 +08:00
47a7bb3c9f
Merge branch 'smaller_nothreads' of https://github.com/cseagle/unicorn into cseagle-smaller_nothreads
2016-04-17 23:37:06 +08:00
acd88856e1
add batched reg access
2016-04-04 20:51:38 -07:00
9467254fc0
strip out per cpu thread code
2016-03-25 17:24:28 -07:00
fb1ebac000
Merge branch 'master' into m1
2016-03-09 15:13:42 +08:00
c5888e5670
move macros in qemu/target-*/unicorn*.c to uc_priv.h
2016-03-02 12:43:02 +09:00
20b01a6933
fix merge conflict
2016-02-01 12:08:38 +08:00
e750a4e97c
when uc_mem_exec() remove EXE permission, quit current TB & continue emulating with TB flushed. this fixes issue in PR #378
2016-01-28 00:56:55 +08:00
48ab148d1c
Merge branch 'hook'
2016-01-26 22:52:29 +08:00
4dbad9aa9b
add new API uc_query() to query internal status of emulator at runtime
2016-01-23 17:14:44 +08:00
38d1443504
Merge branch 'hook-refactor' of https://github.com/lunixbochs/unicorn into lunixbochs-hook-refactor
2016-01-23 13:24:12 +08:00
9f9bd7098b
patch hook bounds to be inclusive
2016-01-22 19:24:45 -08:00
249e2ac0a0
Merge branch 'hook-refactor' of https://github.com/lunixbochs/unicorn into lunixbochs-hook-refactor
2016-01-23 10:58:37 +08:00
d79925f477
sparc: add SPARC32 mode (= UC_MODE_32)
2016-01-23 10:48:18 +08:00
93052f6566
refactor to allow multiple hooks for one type
2016-01-22 18:41:43 -08:00
8763d426c2
Fix uc_mode usage in source code
2016-01-23 12:08:49 +11:00
82b7599e15
Sorted uc_modes by CPU and added masks
2016-01-23 09:47:29 +11:00
036763d6ae
Fix memory leaks as reported by DrMemory and Valgrind.
...
ARM and probably the rest of the arches have significant memory leaks as
they have no release interface.
Additionally, DrMemory does not have 64-bit support and thus I can't
test the 64-bit version under Windows. Under Linux valgrind supports
both 32-bit and 64-bit but there are different macros and code for Linux
and Windows.
2016-01-08 01:42:56 +02:00
230cbd5330
add permissions to map_ptr api
2015-11-28 11:28:31 -08:00
6d21ebabea
implement host-controlled memory mapping for #261
2015-11-27 23:30:36 -08:00
2f297bdd3a
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-12 01:43:41 +08:00
389bc06b49
Fix crash on 00 opcode.
...
l1_map should be an array of pointers, thus void **
2015-11-06 14:08:12 +02:00
3a36e327ab
support memory redirection, so the issue #217 is fixed
2015-10-27 14:37:03 +08:00
