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87a391d549
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Inline uc_tracecode when there is only exactly one hook
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2021-11-21 16:44:39 +01:00 |
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640251e1aa
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Leave out size parameter in callback
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2021-11-09 00:21:34 +01:00 |
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c6fdbb3735
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Add RISCV CSR registers
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2021-11-07 20:36:04 +01:00 |
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613ddf0985
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Format
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2021-11-04 19:58:44 +01:00 |
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172a2fbe6d
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Support changing cpu model for riscv
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2021-11-04 19:13:53 +01:00 |
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09aa0f944f
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Merge QDucasse:riscv_extension_d
Fix and close #1469
Fix test for riscv float points
Fix the riscv cpu config we left out
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2021-11-03 13:20:46 +01:00 |
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bcf85be86d
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Add a new hook type UC_HOOK_TCG_OPCODE
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2021-11-03 01:46:24 +01:00 |
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3dd2e0f95d
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Basic implementation of uc_ctl
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2021-11-01 00:39:36 +01:00 |
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e62b0ef255
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Add clang-format and format code to qemu code style
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2021-10-29 12:44:49 +02:00 |
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e695686c15
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Remove AFL Integration by reverting
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2021-10-26 11:22:21 +02:00 |
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7ac7c23c12
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Fix Windows build for AFL integration
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2021-10-25 16:11:58 +02:00 |
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1fa2eb688b
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Fix UC_MODE_AFL and update config
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2021-10-25 14:39:40 +02:00 |
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dd7476a9bd
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Initial import unicornafl
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2021-10-25 00:51:16 +02:00 |
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567bd08b86
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Update riscv pc and fix #1465
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2021-10-19 23:22:13 +02:00 |
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aaaea14214
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import Unicorn2
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2021-10-03 22:14:44 +08:00 |
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