Commit Graph

131 Commits

Author SHA1 Message Date
47ecfc1b2c Handle exceptions raised in Python hook functions (#1387) 2021-10-12 08:35:52 +08:00
mio
59deed7484 Simply the setup.py 2021-10-05 14:46:04 +02:00
e8bd7ca087 bindings: update X86 register constants 2021-10-04 19:41:41 +08:00
aaaea14214 import Unicorn2 2021-10-03 22:14:44 +08:00
2874435d2f bump version to 1.0.3 2021-05-16 21:38:08 +08:00
4f9a6cfcf3 Handle exceptions raised in Python hook functions (#1387) 2021-04-26 00:35:56 +08:00
21ec6e8f83 Add ARM BE8 support (#1369)
Co-authored-by: w4kfu <gw4kfu@gmail.com>
2021-03-31 21:22:35 +08:00
1044403d38 Implement uc_context_free (#1336)
* Implement uc_context_free

* Use uc_context_free for python bindings

* Format code

* Simplify code

* Move next,context inside while loop

* Add my name to CREDITS.TXT
2020-09-24 22:28:55 +08:00
4441394258 Fix context saving (#1335)
* Fix context size

* Make UcContext convertible to bytes and picklable

Fix when updaing context

* Test context pickling

* Fix double free when the context is pickled from bytes
2020-09-24 00:53:23 +08:00
2e0f753e6f save cpu->jmp_env in saving context, so uc_emu_start() can be reentrant. also improved Python binding on handling context 2020-06-05 20:12:44 +08:00
fbef45b18f remove UC_ERR_TIMEOUT, so timeout on uc_emu_start() is not considered error. added UC_QUERY_TIMEOUT to query exit reason 2020-05-24 23:54:45 +08:00
cf3451c37a bindings: update ARM64 registers 2020-05-10 21:51:14 +08:00
625399774c X64 base regs (#1166)
* x86: setup FS & GS base

* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)

* FS reg comes before GS so the base regs do so, too

* added shebang to const_generator.py

* Added base regs to and added 'all' support to const_generator

Co-authored-by: naq <aquynh@gmail.com>
2020-05-05 08:34:51 +08:00
b0d5837c61 bindings: add UC_ERR_TIMEOUT 2019-12-29 00:19:34 +08:00
naq
3b17db0d84 bindings: update after the last commit on adding ARM modes 2019-10-26 05:02:39 +08:00
07f94ad1fc Added an invalid instruction hook (#1132)
* first draft for an invalid instruction hook

* Fixed documentation on return value of invalid insn hook
2019-09-23 01:53:06 +08:00
8987ad0fff Handle serialization of cpu context save (#1129)
* Handle the cpu context save in a more pythonic way, so the context can be serialized and reuse in an other process using the same emulator architecture and modes

* Fix type error ; mistakes a size_t uint64_t ; breaks in 32bit...
2019-09-07 19:09:17 +08:00
24f55a7973 Removed hardcoded CP0C3_ULRI (#1098)
* activate CP0C3_ULRI for CONFIG3, mips

* updated with mips patches

* updated with mips patches

* remove hardcoded config3

* git ignore vscode

* fix spacing issue and turn on floating point
2019-07-06 17:53:02 +08:00
55d8d073bd support for YMM registers ymm8-ymm15 (#1079) 2019-04-01 11:00:34 +08:00
07cafff76a bindings: update for latest ARM registers addition 2019-03-07 08:38:41 +08:00
6d47b38b7f bindings: update after recent addition of ARM_REG_IPSR 2019-02-28 09:56:29 +08:00
738d102989 bindings: add newly added register MXCSR 2019-02-15 13:01:27 +08:00
41cc047b87 bindings: update after #922 2017-12-20 22:13:29 +08:00
12642c2555 Cleanups/fixes for the library issue conglomerate (#897)
* Python: Disable distribution of static library on linux and macos; add environment variable LIBUNICORN_PATH to let user specify location of native library; prevent build of native library if this option is enabled; closes #869

* Python: Update README.TXT to describe how to manage the building and usage of the native library
2017-09-24 22:33:01 +08:00
b0b5f8442d python: Fix exception in finalizer at exit (#873)
Sometimes, the finalizer for an `UcRef` runs so late that the members of the
module have already been set to `None`. We need to make sure that we don't
depend on anything in the module, or we risk getting a Exception when we try
to access the `release_handle` method of `None` (`Uc`).
2017-09-15 22:21:25 +07:00
3fdb2d2442 add architecture query (#842) 2017-05-21 09:47:02 +08:00
014ccfb94a Aarch64 add thread registers (#834)
* add thread registers to AArch64

* update bindings to add AArch64 thread registers

* fix indentation for register read/write switch-case in unicorn_aarch64.c
2017-05-14 14:42:49 +07:00
5385baba39 Implemented read and write access to the YMM registers (#819) 2017-05-05 09:02:58 +08:00
187b470245 add arm64 CPACR_EL1 register support (#814) 2017-05-02 14:51:19 +08:00
2e973a13f0 arm64eb: add support for ARM64 big endian. 2017-04-24 23:30:01 +08:00
5dbc640b9a bump UC_VERSION_EXTRA to 1 2017-04-20 14:14:24 +08:00
7441cfe4e5 Update unicorn.py
space
2017-04-18 07:46:12 +08:00
4f07910eae handle not having a path (#798) 2017-04-18 07:44:48 +08:00
b3a5eae81c uc_reg_read & uc_reg_write now support ARM64 Neon registers (#774)
* uc_reg_read & uc_reg_write now support ARM64 Neon registers

* Do not reuse uc_x86_xmm for uc_arm64_neon128. TODO: refactor both classes to use the same parent.
2017-03-07 21:29:34 +08:00
f4325f8c4e bindings: update to support X86 MSR id 2017-02-24 21:51:01 +08:00
02e6c14e12 x86: add MSR API via reg API (#755)
Writing / reading to model specific registers should be as easy as
calling a function, it's a bit stupid to write shell code and run them
just to write/read to a MSR, and even worse, you need more than just a
shellcode to read...

So, add a special register ID called UC_X86_REG_MSR, which should be
passed to uc_reg_write()/uc_reg_read() as the register ID, and then a
data structure which is uc_x86_msr (12 bytes), as the value (always), where:
	Byte	Value		Size
	0	MSR ID		4
	4       MSR val		8
2017-02-24 21:37:19 +08:00
b616115df1 update ChangeLog 2017-01-25 12:00:18 +08:00
a735576dd3 python: support uc_mem_regions() API 2017-01-24 12:47:27 +08:00
5a1e86d46b update Windows DLL dependency 2017-01-22 00:39:21 +08:00
d2b7d13443 Fixed circular refs preventing Uc instances from being GC'd. Added a test case, requires objgraph module. 2017-01-11 18:23:21 +03:00
bc569f5a54 rename API uc_mem_free() to uc_free(). see #662 2017-01-10 20:59:14 +08:00
fdbbdc6216 rename uc_context_free() to uc_mem_free(). see #373 2017-01-09 20:52:14 +08:00
me
1d85d1763d Merge branch 'master' into noglib 2016-12-24 13:21:53 +08:00
a7dddf6c5f python bindings: restore FreeBSD support (#698)
* python bindings: restore FreeBSD support

* python binding: use libunicorn.so if the platform is unknown
2016-12-24 00:59:19 +08:00
e46545f722 remove glib dependency by provide compatible replacements 2016-12-18 14:56:58 -08:00
bd339533ca python: comment out a debug code 2016-12-04 20:46:52 +07:00
4613580e07 python: typo 'prebuilt' dir 2016-12-04 18:18:24 +08:00
e34812c7dd fix merge conflict 2016-11-20 16:36:56 +08:00
75d90aff52 Make cleanup (#666)
* make cleanup

* Update .travis.yml
Update eflags_nosync.c
Update sigill2.c
Update ro_mem_test.c
Update ro_mem_test.c
Update nr_mem_test.c
Update mem_fuzz.c
Update mem_double_unmap.c
Update emu_stop_in_hook_overrun.c
Update eflags_nosync.c
remove unused
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update mem_64_c.c
Update mem_64_c.c
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update Makefile
Update .travis.yml
try android ndk build
Update unicorn.py
Update unicorn.py
Update Makefile
Update unicorn.py
Update unicorn.py
remove an untrue comment

if a dll/so/dylib gets loaded at runtime is dependent on many different factors, primarily the LD/DYLD paths. Those do not always include the current working directory
Update Makefile
Update .appveyor.yml
Update .travis.yml
Update Makefile
Update .appveyor.yml
Fix bad sample

* Update Makefile

* Update Makefile

* Update install-cmocka-linux.sh

* remove verbose option from tar

* add upgrade to pacman for cmake

* pacman double update, needed to get new packages

* enable cmocka unit testing

* rejigger commands to fail on any step

should get fails in msys builds for cmocka

* fix quote

* make cmocka in cygwin only

* add msys cache
2016-11-19 17:17:48 +08:00
876570c8d7 Fixes to make python distribution for windows work 2016-11-05 09:18:50 -07:00